PROTECTED VIRTUAL ADDRESS MODE (PVAM)

80286 is the first processor to support the concepts of virtual memory and memory management.
The virtual memory does not exist physically it still appears to be available within the system.
The concept of VM is implemented using Physical memory that the CPU can directly access and
secondary memory that is used as storage for data and program, which are stored in secondary
memory initially. The Segment of the program or data required for actual execution at that
instant is fetched from the secondary memory into physical memory. After the execution of this
fetched segment, the next segment required for further execution is again fetched from the
secondary memory, while the results of the executed segment are stored back into the secondary
memory for further references. This continues till the complete program is executed.
During the execution the partial results of the previously executed portions are again fetched into
the physical memory, if required for further execution. The procedure of fetching the chosen
program segments or data from the secondary storage into physical memory is called swapping.
The procedure of storing back the partial results or data back on the secondary storage is called
unswapping. The virtual memory is allotted per task.
The 80286 is able to address 1 G byte (2 30 bytes) of virtual memory per task. The complete
virtual memory is mapped on to the 16Mbyte physical memory. If a program larger than
16Mbyte is stored on the hard disk and is to be executed, if it is fetched in terms of data or
program segments of less than 16Mbyte in size into the program memory by swapping
sequentially as per sequence of execution. Whenever the portion of a program is required for
execution by the CPU, it is fetched from the secondary memory and placed in the physical
memory is called swapping in of the program. A portion of the program or important partial
results required for further execution may be saved back on secondary storage to make the PM
free for further execution of another required portion of the program is called swapping out of
the executable program.

80286 uses the 16-bit content of a segment register as a selector to address a descriptor stored in
the physical memory. The descriptor is a block of contiguous memory locations containing
information of a segment, like segment base address, segment limit, segment type, privilege
level, segment availability in physical memory, descriptor type and segment use another task.

Physical address calculation

A virtual address, like a real address, is made up of a 16-bit segment selector and a 16-bit
offset

From the diagram, we can see that there are 213entries in each descriptor table and, as
with real mode, each segment can reference up to 216bytes of memory which give us up
to 230bytes or 1GB of virtual address space

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Virtual Address

16 bit selector
15

Index

TI

16 bit offset
1

RPL

TI=0

TI=1

Base Address

Physical Address

We can also see that the calculated physical address is 24-bits which means that we can
address 224bytes or 16MB of memory

Because the virtual address space is far bigger than the physical address space, not all of
it can exist in memory simultaneously

The OS can leave data that hasnt been accessed on an auxiliary storage device such as a
hard disk and copy it to memory when needed, or can make more room in memory by
moving not recently used data to the disk

A list of the virtual to physical mappings is stored in memory and is looked up whenever
memory is accessed

The 80286 has a single Global Descriptor Table (GDT) which is shared between all
tasks and addresses up to 512MB of the virtual address space

Each task will have its own Local Descriptor Table (LDT) which is a private 512MB of
address space

The following registers are involved in address translation:

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The following steps are involved in address translation:

1) Obtain the selector from a segment register
2) If TI = 0, then obtain the global descriptor table address from the GDT register
and go to step 4
3) If TI = 1 indicating the local descriptor table then:
i. Get the selector for the LDTs segment from the LDT register
ii. Extract the index from this selector and multiply by 8
iii. Add this to the GDT address from the GDT register
iv. Fetch the addressed descriptor from memory
v. Extract from this the base address of the LDT
4) Extract the index from the segment register and multiply by 8 and add it to the
descriptor table address. Fetch the descriptor from memory
5) Extract from the descriptor the segment base address

6) Add the offset to the segment base address. This is the desired physical address
7) Perform the desired memory access at this location
DESCRIPTORS
Descriptors define the use of memory. Special types of descriptors also define new functions for
transfer of control and task switching. The 80286 has segment descriptors for code, stack and
data segments and system control descriptors for special system data segments and control
transfer operations. Descriptor accesses are performed as locked bus operations to assure
descriptor integrity in multi-processor systems.

CODE AND DATA SEGMENT DESCRIPTORS

(S = 1)
Besides segment base addresses, code and datadescriptors contain other segment attributes
including segment size (1 to 64K bytes), access rights (read only, read/write, execute only, and
execute/read), and presence in memory (for virtual memory systems). Any segment usage
violating a segment attribute indicated by the segment descriptor will prevent the memory cycle
and cause an exception or interrupt.

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Code and data (including stack data) are stored in two types of segments: code segments and data
segments. Both types are identified and defined by segment descriptors (S = 1). Code segments
are identified by the executable (E) bit set to 1 in the descriptor access rights byte. The access
rights

byte

of both code and data segment descriptor types have three fields in common: present (P) bit,
Descriptor Privilege Level (DPL), and accessed (A) bit. If P = 0, any attempted use of this
segment will cause a not-present exception. DPL specifies the privilege level of the segment
descriptor. DPL controls when the descriptor may be used by a task. The A bit shows whether the
segment has been previously accessed for usage profiling, a necessity for virtual memory
systems. The CPU will always set this bit when accessing the descriptor.
Data segments (S = 1, E = 0) may be either read only or read write as controlled by the W bit of
the access rights byte. Read-only (W = 0) data segments may not be written into. Data segments
may grow in two directions, as determined by the Expansion Direction (ED) bit: upwards (ED =
0) for data segments, and downwards (ED = 1) for a segment containing a stack. The limit field
for a data segment descriptor is interpreted differently depending on the ED bit.

A code segment (S = 1, E = 1) may be execute-only or execute/read as determined by the

Readable (R) bit. Code segments may never be written into and execute-only code segments (R =
0) may not be read. A code segment may also have an attribute called conforming (C). A
conforming code segment may be shared by programs that execute at different privilege levels.
The DPL of a conforming code segment defines the range of privilege levels at which the
segment may be. The limit field identifies the last byte of a code segment.

SYSTEM SEGMENT DESCRIPTORS(S= 0, TYPE = 1-3)

In addition to code and data segment descriptors, the protected mode 80286 defines System
Segment Descriptors. These descriptors define special system data segments which contain a
table of descriptors (Local Descriptor Table Descriptor) or segments which contain the execution
state of a task (Task State Segment Descriptor).
Figure

shown

below

gives

the

formats

for

the

special

system

data segment descriptors. The descriptors contain a 24-bit base address of the segment and a 16bit limit. The access byte defines the type of descriptor, its state and privilege level. The
descriptor contents are valid and the segment is in physical memory if P = 1. If P = 0, the
segment is not valid. The DPL field is only used in Task State Segment descriptors and
indicates the privilege level at which the descriptor may be used (see Privilege). Since the Local
Descriptor Table descriptor may only be used by a special privileged instruction, the DPL field Is
not used. Bit 4 of the access byte is 0 to indicate that it is a system control descriptor. The type
field specifies the descriptor type.

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GATE DESCRIPTORS (S = 0, TYPE = 4-7)

Gates are used to control access to entry points within the target code segment. The gate
descriptors are call gates, task gates, interrupt gates and trap gates. Gates provide a level of
indirection between the source and destination of the control transfer. This indirection allows the
CPU to automatically perform protection checks and control entry point of the destination. Call
gates are used to change privilege levels, task gates are used to perform a task switch, and
interrupt and trap gates are used to specify interrupt service routines. The interrupt gate disables
interrupts (resets IF) while the trap gate does not.

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Figure shows the format of the gate descriptors. The descriptor contains a destination pointer that
points to the descriptor of the target segment and the entry point offset. The destination selector
in an interrupt gate, trap gate, and call gate must refer to a code segment descriptor. These gate
descriptors

contain

the

entry

point

to

prevent

program

from

constructing and using an illegal entry point. Task gates may only refer to a task state segment.
Since task gates invoke a task switch, the destination off- set is not used in the task gate.

Exception 13 is generated when the gate is used if a destination selector does not refer to the
correct descriptor type. The word count field is used in the call gate descriptor to indicate the
number of parameters (0-31 words) to be automatically copied from the caller's stack to the stack
of the called routine when a control transfer changes privilege levels. The word count field is not
used by any other gate descriptor. The access byte format is the same for all gate descriptors. P =
1 indicates that the gate contents are valid. P = 0 indicates the contents are not valid and causes
exception 11 if referenced. DPL is the descriptor privilege level and specifies when this
descriptor may be used by a task. Bit 4 must equal 0 to indicate a system control descriptor. The
type field specifies the descriptor type as indicated in Figure.

Segment Descriptor Cache Registers

A concept of caching was introduced in 80286 to minimize the time required for fetching
the frequently required descriptor information from the main memory. The caching is nothing but
maintaining the most frequently required data for execution in a high speed memory called cache
memory. A 6-byte segment descriptor cache register is assigned to each of the four segments, i.e.
CS, DS, SS and ES. A segment descriptor is automatically loaded in a segment descriptor cache
register, whenever the associated segment register is loaded with a selector. Once a cache register
is loaded, all the information regarding the segment is obtained from the cache register, instead
of referring to the main memory for the descriptor again and again. These cache registers are not
available for programming. They automatically change when a segment register is reloaded.
Figure shows the 6-byte format of the cache registers and the corresponding segment registers.

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Selector Fields
In the protected mode, the contents of the segment registers are known as selectors. The selector
contains three fields in its 16-bit format. The 2-bit field D0-D2 is called as RPL field i.e.
requested privilege level that describes the desired privilege of the segment. The D 2 bit indicates
the descriptor table type, i.e. local descriptor table, if it is 1 and global descriptor table, if it is 0.
The index field D3-D15 points to the required descriptor base in the descriptor table. Figure 9.11
shows the selector field format.

LOCAL AND GLOBAL DESCRIPTOR TABLE

Two tables of descriptors, called descriptor tables, contain all descriptors accessible by a task at
any given time. A descriptor table is a linear array of up to 8192 descriptors. The upper 13 bits of
the selector value are an index into a descriptor table. Each table has a 24-bit base register to
locate the descriptor table in physical memory and a 16-bit limit register that confine descriptor
access to the defined limits of the table as shown in Figure. A restartable exception (13) will
occur if an attempt is made to reference a descriptor outside the table limits. One table, called the
Global Descriptor table (GDT) contains descriptors available to all tasks. The other table, called
the Local Descriptor Table (LDT), contains descriptors that can be private to a task. Each task
may have its own private LDT. The GDT may contain all descriptor types except interrupt and
trap descriptors. The LDT may contain' only segment, task gate, and call gate descriptors. A
segment cannot be accessed by a task if its segment descriptor does not exist in either descriptor
table at the time of access.

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The LGDT and LLDT instructions load the base and limit of the. global and local descriptor
tables. LGDT and LLDT are privileged, i.e. they may only be executed by trusted programs
operating at level 0. The LGDT Instruction loads a six byte field containing the 16-bit table limit
and

24-bit

physical

base

address

of

the Global Descriptor Table as shown in Figure 17. The LLDT instruction loads a selector which
refers to a Local Descriptor Table descriptor containing the base addresses and limit for an LDT,
as shown in figure shown below.

Interrupt Descriptor Table

The protected mode 80286 has a third descriptor table, called the Interrupt Descriptor Table
(IDT), used to define up to 256 interrupts. It may contain only task gates, interrupt gates and trap
gates. The IDT (Interrupt Descriptor Table) has a 24-bit physical base and 16-bit limit register in
the CPU. The privileged LIDT instruction loads these registers with a six byte value of identical
form to that of the LGDT instruction.

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