Scribd Logo
Upload

Welcome to Scribd!

  • 149 views

    Sheet 3 - Solution

    Uploaded by

    Majid Helmy
    The document discusses MOS transistor parameters and calculations. It provides examples of calculating threshold voltage, determining transistor operation regions, deriving expressions for voltage levels in source follower and other circuits, and computing transistor capacitances. It includes multiple circuit examples and questions requiring analysis of transistor behavior.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Sheet 3 - Solution

    Uploaded by

    Majid Helmy
    149 views10 pages
    The document discusses MOS transistor parameters and calculations. It provides examples of calculating threshold voltage, determining transistor operation regions, deriving expressions for voltage levels in source follower and other circuits, and computing transistor capacitances. It includes multiple circuit examples and questions requiring analysis of transistor behavior.

    Original Description:

    Sheet 3_ Solution

    Original Title

    Sheet 3_ Solution

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document discusses MOS transistor parameters and calculations. It provides examples of calculating threshold voltage, determining transistor operation regions, deriving expressions for voltage levels in source follower and other circuits, and computing transistor capacitances. It includes multiple circuit examples and questions requiring analysis of transistor behavior.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    149 views10 pages

    Sheet 3 - Solution

    Uploaded by

    Majid Helmy
    The document discusses MOS transistor parameters and calculations. It provides examples of calculating threshold voltage, determining transistor operation regions, deriving expressions for voltage levels in source follower and other circuits, and computing transistor capacitances. It includes multiple circuit examples and questions requiring analysis of transistor behavior.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 10

    Solution

    ECE-438, MOS Transistor


    Chapter 3, Digital Integrated Circuits, J. M. Rabaey, 2nd Edition

    1) Given the data in the table below for a short channel NMOS transistor with
    VDSAT=0.6V and kc=100PA/V2, calculate VT0, O, J, 2If and W/L.

    1
    2
    3
    4
    5

    VGS
    2.5
    2
    2
    2
    2

    VDS
    1.8
    1.8
    2.5
    1.8
    1.8

    VBS
    0
    0
    0
    -1
    -2

    ID(PA)
    1812
    1297
    1361
    1146
    1039

    For Short-Channel device:


    W
    V2
    ID kc Vmin(VGS  VT )  min (1  OVDS ) ,
    L
    2
    where Vmin= min(VGS-VT, VDS, VDSAT).
    To begin with: the operation regions need to be determined.
    For any of these data to be in saturation:
    VT should be: VGS VT > VDSAT
    2- VT > 0.6 => 1.4 > VT
    This is a quite high value in our process. Thus, we can assume that all data are taken in
    velocity saturation. We will check this assumption later.
    In Velocity Sat.:
    ID

    kc

    V
    W
    VDSAT (VGS  VT  DSAT )(1  OVDS )
    L
    2

    Eq.1

    VDSAT and VDS are constant in 1 & 2 =>


    V
    VGS 1  VT  DSAT
    I D1
    2 =>
    V DSAT
    I D2
    VGS 2  VT 
    2
    1812
    1297

    2.5  VT  0.3
    => VT0 = 0.44V
    2  VT  0.3

    Page: 1

    In 2 & 3 VDSAT and VGS are constant =>

    1297
    1361

    1  1.8O
    O
    1  2.5O

    0.08V 1

    Using data 2 & 4: VT = 0.587 V (1)


    Using data 2 & 5: VT = 0.691 V (2)
    Both these values satisfy VT < 1.4 V so all the data in our table were taken in velocity
    saturation.
    VT 0  J

    VT

     2I F  VSB 

     2I F

    (1) and (2) can be used along with VT0 = 0.44 V to conclude:

    0.29V

    1
    2

    and 2 IF

    0.6 V

    also using 2nd set of data


    ID = 1297PA and Eq.1 =>

    W
    L

    15

    2) An NMOS device is plugged into the test configuration shown below in Figure P1.
    The input Vin=2V and the current source draws a constant current of 50PA. R is a
    variable resistor that can assume values between 10k: and 30k:. Transistor M1
    experiences short channel effects and has following transistor parameters:
    kc=110u10-6V/A2, VT=0.4 and VDSAT=0.6V. The transistor has a W/L=2.5/0.25. For
    simplicity, body effect and channel length modulation can be neglected.
    a) When R=10k: find the operation region, VD and VS.
    b) When R=30k: again determine the operation region, VD and VS.

    Figure P1

    Page: 2

    (a) R=10 K: therefore V D 2.5  10 u 0.05 2V


    we can assume transistor is in SAT.
    kc W
    VGS  VT 2
    ID
    2 L
    110 u 10 6 2.5
    2
    50 u 10 6
    u
    u 2  VS  0.4
    2
    0.25
    Therefore, VS 1.3 V.
    As VGS  VT 0.3 , VDS 0.7 and V DSAT 0.6 , our assumption is correct and the
    device is in saturation region.

    (b) R 30 K: therefore V D 2.5  30 u 0.05 1V


    It is obvious that in this case the transistor is not in velocity saturation (because VS
    Would be 1.22 which is greater than VD ) .
    Assuming the device is in linear region
    V 2
    W
    ID kc VDS (VGS  VT  DS )
    L
    2
    2
    1  VS

    6
    6
    50 u 10
    110 u 10 u 10(1  VS )(2  VS  0.9 
    )
    2
    VS 0.93
    To check our assumption:
    VGS 2  0.93 1.07
    V DS 0.07
    So our first assumption is correct and VS 0.93

    Page: 3

    3) Consider the circuit shown in Figure P2.


    a) Write down the equations (and only those) which are needed to determine the
    voltage at node X. Do NOT plug in any values yet. Neglect short channel effects
    and assume that Pp = 0.
    b) Draw the (approximate) load lines for both PMOS transistor and resistor. Mark
    some of the significant points.
    c) Determine the required width of the transistor (for L = 0.25m) such that X
    equals 1.5 V.
    d) We have, so far, assumed that M1 is a long-channel device. Redraw the load
    lines Assuming that M1(PMOS) is velocity-saturated. Will the voltage at X rise or
    fall?
    (Use Table 3-2, Page 103)

    Figure P2
    PMOS is always in Saturation.

    a)

    kpc W
    VX  VTp
    2 L

    2.5  VX
    R

    b)
    VDD/R
    =2.5/20k=125uA

    c)
    30 x10 6 W
    2
    1.5  0.4
    2
    L

    VSD, VX

    1
    20k:

    Page: 4

    W/L = 2.755 , W = 0.69 Pm

    d)

    VSD, VX

    Voltage at node X would go up since the current drive of PMOS is lower.

    4) The circuit of Figure P3 is known as a source-follower configuration. It achieves a DC


    level shift between the input and output. The value of this shift is determined by the
    current I0. Assume device is in saturation J = 0.4, 2|If| = 0.6 V, VT0 = 0.43 V, kc = 115
    A/V2, and O = 0. The NMOS device has W/L = 5.4/1.2 such that the short channel
    effects are not observed.
    a) Derive an expression giving Vi as a function of Vo and VT(Vo). If we neglect
    body effect, what is the nominal value of the level shift performed by this circuit?
    b) The NMOS transistor experiences a shift in VT due to the body effect. Find VT
    as a function of Vo for Vo ranging from 0 to 1.5V with 0.25 V intervals. Plot VT vs.
    Vo.
    c) Plot Vo vs. Vi as Vo varies from 0 to 1.5 V with 0.25 V intervals. Plot two
    curves: one neglecting the body effect and one accounting for it. How does the
    body-effect influence the operation of the level converter? At Vo (body effect) =
    1.5 V, find Vo (ideal) and, thus, determine the maximum error introduced by body
    effect.

    Figure P2
    Page: 5

    knc W
    (Vi  Vo  Vt )2
    2 L

    a) ID
    2ID
    W
    knc
    L

    Vi  Vo  VT

    Neglecting body effect VT=VT0


    Vi

    2ID
     Vo  V T0
    W
    knc
    L
    2ID
     Vt 0
    W
    knc
    L

    Level  Shift

    LS = 0.8V

    b)
    VT

    VT 0  J

    VT

    0.43  0.4

     2I F  VSB 

     2I F

    Vo  0.6  0.6

    Page: 6

    c)
    Vo

    Vi 

    2ID
    W
    knc
    L

     Vt
    o

    Plot Vi versus Vo for two different cases:


    1) VT = VT0 (neglecting body effect, =0)
    If body effect is neglected, Vi=Vo+constant (linear relation)
    Vo=1.5 V ==> Vi=2.3V

    2) VT= VT(Vo) (accounting for body effect, =0.4)


    Vo=1.5V ==> Vi=2.57 V
    Maximum error due to body effect=2.57-2.3=0.27 V.

    Page: 7

    5) The curves below in Figure P4 represent the gate voltage (VGS) vs. drain current (IDS)
    of two NMOS devices, which are on the same die and operate in sub-threshold region.
    Due to process variations on the same die the curves do not overlap.
    Also assume that the transistors are within the same circuit configurations as Figure P5 in
    If the input voltages are both Vin = 0.2V. What would be the respective durations to
    discharge the load of CL = 1pF attached to the drains of these devices.
    (Assume voltage charge for CL is 1V)

    Figure P4

    Figure P5

    Page: 8

    Vin = 0.2
    IDS = 3 e8 A (1)
    Or
    Vin = 0.2
    IDS = 5 e9 A (2)
    'V
    I

    't

    't1

    1pF

    1
    3x10 8

    33.3P s

    't2

    1pF

    1
    5x10 9

    200 P s

    6) Compute the gate and diffusion capacitances for transistor M1 of Figure P6.
    Assume that drain and source areas are rectangular, and are 1 m wide and 0.25
    0.5 m long.
    Use the parameters of Example 3.5 to determine the capacitance values. Assume mj = 0.5
    and mjsw = 0.44. Also compute the total charge stored at input node, for the following
    initial conditions:
    a) Vin = 2.5 V, Vout = 2.5 V, 0.5 V, and 0 V.
    b) Vin = 0 V, Vout = 2.5 V, 0.5 V, and 0 V.

    Figure P6

    Page: 9

    Cox = 6 fF/Pm2, MOS dimensions L = 0.25Pm and W = 1Pm


    Cut-off : Cg = Cox.WL + 2Co.W
    Linear
    : Cg = Cox.WL + 2Co.W
    Sat-Vel.Sat: Cg = 0.66Cox.WL + 2Co.W
    Diffusion Cap (Cd) NOTE: Ldrain=0.5um (drain length) is not L for the MOSFET
    Cd=Cj*Area+Cjsw*perimeter
    Cd Area=W*Ldrain
    C j LDWD  C jsw (2LP
    Drain
    Drain Perimeter=W+2Ldrain

     WD )

    Cj0

    Cj

    mj
    VDS
    D
    1-
    m j
    I0

    C jsw

    C jsw 0
    D mjsw
    VDS
    1-
    m
    I0 jsw

    a) Vin = 2.5V,
    Vout = 2.5V Vel. Saturation.
    Cg = 1.62 fF , Q = 4.05 fC = 4.05 e 15 C
    Cd = 0.827 fF
    Vout = 0.5 V Linear Reg.
    Cg = 2.12 fF , Q = 5.3 fC
    Cd = 1.263 fF
    Vout = 0 V Linear Reg.
    Cg = 2.12 fF , Q = 5.3 fC
    Cd = 1.56 fF
    b) Vin = 0V => Cut off
    Regardless of VDS
    Cg = Cox.WL
    Cg = 2.12 fF, Q =0
    And Cds are the same as Part a.
    Vin = 2.5V => Cd = 0.827 fF
    Vout = 0.5 V => Cd = 1.263 fF
    Vout = 0 V => Cd = 1.56 fF

    Page: 10

    You might also like