Something We Cant Build (Yet)

What if you were given the following design specification:

button

Sequential Logic

What makes this circuit so different

from those weve discussed before?
1. State i.e. the circuit has memory
2. The output was changed by a input
event (pushing a button) rather
than an input value

Reminder: Lab #2 due Thursday!

Lecture 4

Digital State

6.111 Fall 2009

Combinational
Logic

LOAD

Input

Output

Plan: Build a Sequential Circuit with stored digital STATE

CLK

Memory stores CURRENT state, produced at output

Combinational Logic computes

NEXT state (from input, current state)
OUTPUT bit (from input, current state)
State changes on LOAD control input
6.111 Fall 2009

The edge-triggered D register: on

the rising edge of CLK, the value of
D is saved in the register and then
shortly afterwards appears on Q.

New
State
Current
State

Lecture 4

Our next building block: the D register

One model of what wed like to build

Memory
Device

light

The light should change

state within a second
of the button press

Digital state: the D-Register

Timing constraints for D-Registers
Specifying registers in Verilog
Blocking and nonblocking assignments
Verilog execution semantics: concurrency & nondeterminism
Examples

6.111 Fall 2009

When the button is pushed:

1) Turn on the light if
it is off
2) Turn off the light if
it is on

Lecture 4

When Output depends on input

and current state, circuit is
called a Mealy machine. If
Output depends only on the
current state, circuit is called
a Moore machine.

6.111 Fall 2009

Lecture 4

D-Register Timing - I

D-Register Timing - II
D Q
reg1

!tPD
"tCD

tCLK
tPD,reg1

CLK

CLK
tPD,logic

D
"tSETUP

tCD,reg1

"tHOLD

tCD: minimum contamination delay, CLK !Q

tCD,logic

tSETUP: setup time

tHOLD: hold time

How long D must be stable after the rising edge of CLK

Lecture 4

tCD,reg1 + tCD,logic " tHOLD,reg2

5

6.111 Fall 2009

Single-clock Synchronous Circuits

Does that
symbol
register?

Lecture 4

Well use Registers in a highly constrained way to build digital

systems:

D Q
reg1

Single-clock Synchronous Discipline

CLK

CLKreg1

Single clock signal shared among

all clocked devices (one clock
domain)
Only care about value of
combinational circuits just before
rising edge of clock

The bad news: you have to change

your design if this constraint isnt
met.

In the real world the clock signal

arrives at different registers at
different times. The difference in
arrival times (pos or neg) is called
the clock skew tskew.

D Q
reg2

logic

skew

We can update our two timing

constraints to reflect the worstcase skew:

tPD,reg1+ tPD,logic

tPD,reg1+tPD,logic+ tSETUP,reg2 ! tCLK tskew

tCD,reg1+tCD,logic
" tSETUP,reg2

Clock period greater than every

combinational delay

CLKreg2

Change saved state after noiseinducing logic transitions have

stopped!

CLKreg2 rising edge might fall

anywhere in this region.

Lecture 4

The good news: you can

choose tCLK so that this
constraint is satisfied!

D-Register Timing With Skew

No combinational cycles

6.111 Fall 2009

" tSETUP,reg2

tPD,reg1 + tPD,logic + tSETUP,reg2 ! tCLK

How long D must be stable before the rising edge of CLK

6.111 Fall 2009

D Q
reg2

CLK

tPD: maximum propagation delay, CLK !Q

logic

6.111 Fall 2009

" tHOLD,reg2

Lecture 4

tCD,reg1+tCD,logic " tHOLD,reg2+ tskew

Thus clock skew increases the
minimum cycle time of our design
and makes it harder to meet
register hold times.
8

Sequential Circuit Timing

tCD,R = 1ns
tPD,R = 3ns
tS,R = 2ns
tH,R = 2ns

The Sequential always Block

Edge-triggered circuits are described using a sequential always
block

New
State
Current
State

Clock

Combinational
Logic
tCD,L = ?
tPD,L = 5ns

Input

Sequential

Combinational
module comb(input a, b, sel,
output reg out);

module seq(input a, b, sel, clk,

output reg out);

always @(*) begin

if (sel) out = b;
else out = a;
end

Output

always @(posedge clk) begin

if (sel) out <= b;
else out <= a;
end

endmodule

endmodule

Questions:
Constraints on tCD for the logic?

> 1 ns

Minimum clock period?

> 10 ns (tPD,R+tPD,L+ tSETUP,R)

Setup, Hold times for Inputs?

tSETUP,Input = tPD,L +tSETUP,R

tHOLD,Input = tHOLD,R -tCD,L

This is a simple Finite State Machine more on next time!

6.111 Fall 2009

Lecture 4

Importance of the Sensitivity List

always @(*) begin

x = a | b;
// 1. evaluate a|b, assign result to x
y = a ^ b ^ c; // 2. evaluate a^b^c, assign result to y
z = b & ~c;
// 3. evaluate b&(~c), assign result to z
end

module dff_async_clear(
input d, clearb, clock,
output reg q
);
always @(negedge clearb or posedge clock)
begin
if (!clearb) q <= 1'b0;
else q <= d;
end
endmodule

Nonblocking assignment (<=): all assignments deferred to end of

simulation time step after all right-hand sides have been
evaluated (even those in other active always blocks)

always block entered immediately when

always block entered only at

always @(*) begin

x <= a | b;
// 1. evaluate
y <= a ^ b ^ c; // 2. evaluate
z <= b & ~c;
// 3. evaluate
// 4. end of time step: assign
end

(active-low) clearb is asserted

each positive clock edge

Note: The following is incorrect syntax: always @(clear or negedge clock)

If one signal in the sensitivity list uses posedge/negedge, then all signals must.

! Assign any signal or variable from only one always block. Be wary
of race conditions: always blocks with same trigger execute
concurrently
6.111 Fall 2009

Lecture 4

10

Verilog supports two types of assignments within always blocks,

with subtly different behaviors.
Blocking assignment (=): evaluation and assignment are immediate

D-Register with asynchronous clear

module dff_sync_clear(
input d, clearb, clock,
output reg q
);
always @(posedge clock)
begin
if (!clearb) q <= 1'b0;
else q <= d;
end
endmodule

Lecture 4

Blocking vs. Nonblocking Assignments

The use of posedge and negedge makes an always block

sequential (edge-triggered)
Unlike a combinational always block, the sensitivity list does
determine behavior for synthesis!
D-Register with synchronous clear

6.111 Fall 2009

a|b, but defer assignment to x

a^b^c, but defer assignment to y
b&(~c), but defer assignment to z
new values to x, y and z

Sometimes, as above, both produce the same result. Sometimes, not!

11

6.111 Fall 2009

Lecture 4

12

Use Nonblocking for Sequential Logic

Assignment Styles for Sequential Logic

What we want:
Register Based
Digital Delay Line

Will nonblocking and blocking assignments both produce the

desired result? (old means value before clock edge, new means

always @(posedge clk) begin

q1 <= in;
q2 <= q1;
// uses old q1
out <= q2; // uses old q2
end

always @(posedge clk) begin

q1 = in;
q2 = q1;
// uses new q1
out = q2; // uses new q2
end

At each rising clock edge, q1, q2, and

out simultaneously receive the old
values of in, q1, and q2.!

At each rising clock edge, q1 = in. "

After that, q2 = q1. "
After that, out = q2. "
Therefore out = in.!

the value after most recent assignment)

module nonblocking(
input in, clk,
output reg out
);
reg q1, q2;
always @(posedge clk) begin
q1 <= in;
q2 <= q1;
// uses old q1
out <= q2; // uses old q2
end

module blocking(
input in, clk,
output reg out
);
reg q1, q2;
always @(posedge clk) begin
q1 = in;
q2 = q1;
// uses new q1
out = q2; // uses new q2
end

endmodule
6.111 Fall 2009

Blocking assignments do not reflect the intrinsic behavior of multistage sequential logic
Guideline: use nonblocking assignments for sequential always blocks

endmodule
Lecture 4

13

6.111 Fall 2009

Verilog Events

Lecture 4

14

Verilog Execution Semantics

while (there are events) {
From Section 5.4 of the
if (no active events) {
IEEE 1364-2001 Verilog
if (there are inactive events) {
standard.
activate all inactive events;
} else if (there are nonblocking assign update events) {
activate all nonblocking assign update events;
} else if (there are monitor events) {
activate all monitor events;
} else {
advance T to the next event time;
activate all inactive events for time T;
Active events can be processed
}
in any order, but update events
}
from same always block will
E = any active event;
happen in order.
if (E is an update event) {
update the modified object;
add evaluation events for sensitive processes to event queue;
} else { /* E is an evaluation event */
evaluate the process;
A process evaluation might be
add update events to the event queue;
suspended in favor of other
}
processes.
}

IEEE 1364-2001 Verilog Standard: Section 5.3 The stratified event queue
The Verilog event queue is logically segmented into five different regions. Events
are added to any of the five regions but are only removed from the active region.
1.Events that occur at the current simulation time and can be processed in any order.
These are the active events.
2.Events that occur at the current simulation time, but that shall be processed after all
the active events are processed. These are the inactive events.
3.Events that have been evaluated during some previous simulation time, but that
shall be assigned at this simulation time after all the active and inactive events are
processed. These are the nonblocking assign update events.
4.Events that shall be processed after all the active, inactive, and nonblocking assign
update events are processed. These are the monitor events.
5.Events that occur at some future simulation time. These are the future events.
Future events are divided into future inactive events, and future nonblocking
assignment update events.

For more info see: http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf

6.111 Fall 2009

Lecture 4

15

6.111 Fall 2009

Lecture 4

16

Coding Guidelines

= vs. <= inside always

The following helpful guidelines are from the Cummings paper

referenced on the previous slide. If followed, they ensure your
simulation results will match what the synthesized hardware will
do:

Lecture 1

always @(posedge clk) begin

a <= b; // non-blocking assignment
b <= a; // eval all RHSs first
end

C
initial begin
clk = 0; a = 0; b = 1;
D
#10 clk = 1;
#10 $display("a=%d b=%d\n",a,b);
$finish;
E
end
endmodule

always @(posedge clk) a = b;

always @(posedge clk) b = a;
always @(posedge clk) a <= b;
always @(posedge clk) b <= a;
always @(posedge clk) begin
a <= b;
b = a;
// urk! Be consistent!
end

Rule: always change state using <= (e.g., inside always @(posedge clk))
17

6.111 Fall 2009

Implementation for on/off button

Lecture 4

18

Synchronous on/off button

button

When designing a system that accepts many inputs it would be hard

to have input changes serve as the system clock (which input would
we use?). So well use a single clock of some fixed frequency and
have the inputs control what state changes happen on rising clock
edges.

light

For most of our lab designs well use a 27MHz system clock (37ns
clock period).

module onoff(input button, output reg light);

always @(posedge button) light <= ~light;
endmodule

6.111 Fall 2009

always @(posedge clk) begin

a = b;
// blocking assignment
b = a;
// execute sequentially
end

module main;
reg a,b,clk;

1.When modeling sequential logic, use nonblocking assignments.

2.When modeling latches, use nonblocking assignments.
3.When modeling combinational logic with an always block, use
blocking assignments.
4.When modeling both sequential and combinational logic within
the same always block, use nonblocking assignments.
5.Do not mix blocking and nonblocking assignments in the same
always block.
6.Do not make assignments to the same variable from more than
one always block.
7.Use $strobe to display values that have been assigned using
nonblocking assignments.
8.Do not make assignments using #0 delays.
6.111 Fall 2009

Lecture 4

module onoff_sync(input clk, button,

output reg light);
always @ (posedge clk) begin
if (button) light <= ~light;
end
endmodule

19

6.111 Fall 2009

Lecture 4

20

Resetting to a known state

Clocks are fast, were slow!

Usually one cant rely on registers powering-on to a particular initial

state*. So most designs have a RESET signal that when asserted
initializes all the state to known, mutually consistent initial values.

The circuit on the last slide toggles the light on every rising clock
edge for which button is 1. But clocks are fast (27MHz!) and our
fingers are slow, so how do we press the button for just one clock
edge? Answer: we cant, but we can can add some state that
remembers what button was last clock cycle and then detect the
clock cycles when button changes from 0 to 1.

module onoff_sync(input clk, reset, button,

output reg light);
always @ (posedge clk) begin
if (reset) light <= 0;
else if (button) light <= ~light;
end
endmodule

module onoff_sync(input clk, reset, button,

output reg light);
reg old_button; // state of button last clk
always @ (posedge clk) begin
if (reset)
begin light <= 0; old_button <= 0; end
else if (old_button==0 && button==1)
// button changed from 0 to 1
light <= ~light;
old_button <= button;
end
endmodule

* Actually, our FPGAs will reset all registers to 0 when the device is
programmed. But its nice to be able to press a reset button to return to a
known state rather than starting from scratch by reprogramming the
device.
6.111 Fall 2009

Lecture 4

21

Asynchronous Inputs in Sequential Systems

Lecture 4

All of them can be, if more than one happens simultaneously

within the same circuit.

Cant guarantee
setup and hold
times will be met!

Guideline: ensure that external signals directly feed

exactly one flip-flop

Clock

Clocked
Synchronous
System

When an asynchronous signal causes a setup/hold

violation...
I

II

22

Asynchronous Inputs in Sequential Systems

What about external signals?

Sequential System

6.111 Fall 2009

III

D Q

Sequential System

Q0

Clock

Async
Input

Clock

Q1

Clock

Clock
Transition is missed
on first clock cycle,
but caught on next
clock cycle.
6.111 Fall 2009

Transition is caught
on first clock cycle.

Output is metastable
for an indeterminate
amount of time.

This prevents the possibility of I and II occurring in different places in

the circuit, but what about metastability?

Q: Which cases are problematic?

Lecture 4

23

6.111 Fall 2009

Lecture 4

24

Handling Metastability

One last little problem

Preventing metastability turns out to be an impossible problem

High gain of digital devices makes it likely that metastable conditions will
resolve themselves quickly
Solution to metastability: allow time for signals to stabilize
Can be
metastable
right after
sampling

Very unlikely to
be metastable for
>1 clock cycle

D Q

D Q D Q

Mechanical buttons exhibit contact

bounce when they change position,
leading to multiple output transitions
before finally stabilizing in the new
position:

Extremely unlikely
to be metastable for
>2 clock cycle

Lecture 4

endmodule

25

6.111 Fall 2009

On/off button: final answer

Lecture 4

26

Example: A Simple Counter

module onoff_sync(input clk, reset, button_in,

output reg light);
// synchronizer
reg button,btemp;
always @(posedge clk)
{button,btemp} <= {btemp,button_in};

Isn t this a lot like

Exercise 1 in Lab 2?

0
+1

4
count

// debounce push button

wire bpressed;
debounce db1(.clock(clk),.reset(reset),
.noisy(button),.clean(bpressed));

enb

reg old_bpressed; // state last clk cycle

always @ (posedge clk) begin
if (reset)
begin light <= 0; old_bpressed <= 0; end
else if (old_bpressed==0 && bpressed==1)
// button changed from 0 to 1
light <= ~light;
old_bpressed <= bpressed;
end
endmodule

Lecture 4

always @(posedge clock)

if (reset)
// return to known state
begin
count <= 0;
new <= noisy;
clean <= noisy;
end
else if (noisy != new)
// input changed
begin
new <= noisy;
count <= 0;
end
else if (count == DELAY) // stable!
clean <= new;
else
// waiting
count <= count+1;

We need a debouncing circuit!

How many registers are necessary?

Depends on many design parameters (clock speed, device speeds, )
In 6.111, a pair of synchronization registers is sufficient

6.111 Fall 2009

reg [18:0] count;

reg new;

Complicated
Sequential Logic
System

Clock

6.111 Fall 2009

// Switch Debounce Module

// use your system clock for the clock input
// to produce a synchronous, debounced output
// DELAY = .01 sec with a 27Mhz clock
module debounce #(parameter DELAY=270000)
(input reset, clock, noisy,
output reg clean);

clr

clk

// 4-bit counter with enable and synchronous clear

module counter(input clk,enb,clr,
output reg [3:0] count);
wire [3:0] next_count = clr ? 4b0 :
enb ? count+1 :
count;
always @(posedge clk) count <= next_count;
endmodule

27

6.111 Fall 2009

Lecture 4

28