CS220

Spring 2015
Practice Problems #8 Solutions

Problem 1: Assuming the following timings for the components of the datapath. All other components have no
delay.
Data/Instruction Memory Read: 200ps
Adders: 80ps
Data Memory Write: 100ps
ALUs: 200ps
Register File Read: 100ps
Logical Shifter/Sign Extension: 30ps
Register File Write: 50ps
Multiplexors and other gates: 10ps
a. Calculate the delay for each clock cycle of the multicycle datapath finite state machine (each stage of each
instruction, i.e. each bubble). See attached pages
b. What is the minimum clock cycle period at which the multicycle datapath can operate properly? 270ps
What is the length of each instruction type in ps (Rtype, lw, sw, beq, j)?
lw 270*5 = 1350ps
sw/rtype 270*4 = 1080 ps
beq/j 270*3 = 810 ps

Problem 2: MIPS Execution
Examine the following MIPS program P.

add $t0, $s4, $s3
and $t2, $t0, $s1
add $t1, $t1, $t1
add $t2, $t2, $t2
lw
$t3, OPTION
beq $s0, $t3, PARSE_WRITE_SP_LE
and $t0, $t1, 0xff
and $t1, $t1, 0xff00
or
$t1, $t1, $t0
and $t0, $t2, 0xff
and $t2, $t2, 0xff00
or
$t2, $t2, $t0
PARSE_WRITE_SP_LE:
sw $t1, 0($a1)
lw $v0, WRITE_FILE
sw $t2, 0($a1)
a. In the multicycle datapath, in which clock cycle is the lw $t3, OPTION instruction fetched? 17th cycle
b. In the multicycle datapath, how many cycles does it take Program P to execute, assuming the branch is not
taken? 61 clock cycles
c. Which values (eg. MEM[$s0], branch address, Instruction[15:0], etc) are stored in the A, B, ALUOut, and MDR
registers during the execution cycle of the following instruction: sw $t1, 0($a1)
A: Reg[rs] = Reg[$a1]
B: Reg[rt] = Reg[$t1]
ALUOut: Reg[rs] + Instr[15:0] = Reg[$a1] + 0
MDR: Value read from memory (since Mem Rd = 0, it is the value last time read from the memory), which is the
sw instruction itself.

Problem 3: Multicycle datapath

In class we covered the MIPS multicycle implementation also which operates for the same basic subset of MIPS
instructions as in the singlecycle basic implementation. In this problem you will introduce functionality for
additional MIPS instructions. Use the Multicycle handout posted on PIAZZA to specify your changes. In all cases,
try to find a solution that minimizes the number of clock cycles required for the new instruction. Additional
functional units can be added (adder, ALU, Sign Extension, Registers, etc), but only when absolutely necessary.
Explicitly state how many cycles it takes to execute the new instruction in your modified finite state machine.

Modify the datapath and the finite state machine to implement the following instructions INDEPENDANTLY:
a. Implement 'addi' instruction

Reg[rt] Reg[rs] + immed[15:0];
# register rs is added to immediate value in the instruction and stored in rt

b. Implement 'jal' instruction.
Reg[31] PC+4 # $ra register stores the return address
PC PC+4[31:28], (Instruction[25:0] << 2)
# PC is the top 4 bits of the PC+4 value concatenated with the lowest 26 bits of the jump address
# shifted the left by 2 bits

c. Implement a new 'wai' instruction. The instruction, wai rt, stands for "where am i" and puts the
instruction address into a register specified by the rt field. (Immediate format)
Reg[rt] PC # $ra register stores the return address

d. Implement bne
if(Reg[rs] != Reg[rt]) PC PC+4 + Instruction[15:0] << 2

e. Implement beqi (Assume the rs field is a 5bit 2s complement value)
if(Reg[rt] == 2s complement value in rs field)
PC PC+4 + Instruction[15:0] << 2

f. Implement bgtz (Assume the rt register is set to $0)
if(Reg[rs] >= 0) PC PC+4 + Instruction[15:0] << 2

g. Implement a new 'incbeq' instruction. The instruction, incbeq rs, rt, label, stands for "increment
and branch on equal". Increment always occurs!
if(Reg[rs] == Reg[rt]) PC PC+4 + Instruction[15:0] << 2
Reg[rs] Reg[rs] +4 #the increment always occurs

h. Implement a new 'sneg' instruction. The instruction, sneg rs, stands for "set on negative. (Immediate
format)
if (Reg[rs] < 0) Reg[rt] = 1 , else Reg[rt] 0

i. Implement a new lwdec instructon. The instruction lwdec rs, offset(rt), loads a value and
decrements the rs value by one memory word.
Reg[rt] Mem[Reg[rs] + signextended offset]
Reg[rs] Reg[rs] 4

j. Implement a new swr instruction. The instruction swr rd, rt(rs), uses a register value for the offset
when calculating the memory address to store data to.
Mem[Reg[rs] + Reg[rt]] = Reg[rd]

k. Implement a new slti instruction. The instruction sets slti rs, rt, immediate sets the rs register
to the immediate value if the value in register rs is less than register rt.
if(Reg[rs] < Reg[rt])
Reg[rs] 2s complement immediate value


Problem 4: Show how the jump register instruction 'jr' can be implemented to the multicycle datapath by simply
making changes to the finite state machine. (Hint: $0 = $zero = 0)

rt field of the instruction should be register $0, which always holds the value 0.

Problem 5: Calculate the delay in the datapath after the addition of ALL instructions in Problem 3. Assume the
same delays. What is the minimum clock cycle period at which this design can operate properly?
The answer will depend on how you implemented each instruction

Problem 6: Consider changes to the original multicycle datapath that alters the register file so that it has only one
read port. Describe any changes that will need to be made to the datapath in order to support this modification.
Use the datapath diagram to illustrate the changes. Modify the finite state machine to indicate how the instructions
will work given your new datapath.

You will need to add control lines to Write registers A and B and a multiplexer (with a control line) to select
between the Rs and Rt fields of the instruction.
State 1 is modified with select Rs and WriteA asserted. A new state has to be added before states 6 and 8 to select
Rt and WriteB. After the new state control branches to either state 6 or state 8 based upon the opcode. Other
states are not affected as on RFormat and branch instruction use input from two registers. Additionally, State 2
must be modified to additionally read the Rt register and store the contents in B. While, lw does not require to read
Rt, the store word does. By making the modification to State 2, where the Register file is not being used, we do not

increase the number of clock cycles required for a sw instruction. Control signals to select Rt and WriteB must be
specified.
Problem 7: Consider eliminating the two shift left by 2 units in the multicycle datapath. Instead of these units, the
ALU will be used for shifting the values instead. What impact does this have on the original 5 instructions (lw, sw,
Rtype, beq, j)?

If the shift left by 2 is eliminated, then any time this happens will require that the ALU is used.
First, since the Decode stage adds the immediate value shifted left by 2 to calculate the branch address, now a stage
in between the Fetch and Decode stages would need to be added to do the shifting of the sign extended value. The
value would be in ALUOut and the input 3 of ALUSrcB would need to modified to be the valued from the ALUOut
register.

The second Shift left unit is used in stage 9 for the Jump instruction. If this was removed, the datapath would need
to go through the ALU and the PCSource mux could eliminate input 2, and use the value out of the ALU instead.


Problem 8: In the single cycle datapath control unit for the original 5 instructions (lw, sw, Rtype, beq, j), the
MemtoReg control signal can be eliminated and the MemRead or ALUSrc control signals can be used to control the
multiplexor instead. This reduces the number of control signals required (less logic gates to implement).
a. Which other signals in the single cycle datapath can be eliminated and replaced by another existing control
signal, or the inverse (NOT) of the signal.

RegDst and ALUOp1
RegDst & MemRead
Branch & AluOp0

b. Are there any signals in the multicycle datapath (basic 5 instructions only) which can be eliminated and
replaced?

Yes, MemtoReg is only used in Stage 4 &7. It can be replaced with RegDst (which is also only used in Stage
4 & 7)