Ad82587d PDF

ESMT/EMP
AD82587D
Preliminary
2X20W Stereo / 1X40W Mono Digital Audio Amplifier

Features
z Anti-pop design
z 16/18/20/24-bit input with I2S, Left-alignment
z Short circuit and over-temperature protection
and Right-alignment data format
z I2C control interface with selectable device address
z PSNR & DR(A-weighting)
z Internal PLL
Loudspeaker: 97dB (PSNR), 105dB (DR) @ 24V
z LV Under-voltage shutdown and HV Under-voltage
z Multiple sampling frequencies (Fs)
detection
32kHz / 44.1kHz / 48kHz and
z Power saving mode
64kHz / 88.2kHz / 96kHz and
z Dynamic temperature control
128kHz/176.4kHz/192kHz
z System clock = 64x, 128x, 256x, 384x, 512x, 768x,
Applications
1024x Fs
z TV audio
256x~1024x Fs for 32kHz / 44.1kHz / 48kHz
z Boom-box, CD and DVD receiver, docking system
128x~512x Fs for 64kHz / 88.2kHz / 96kHz
z Powered speaker
64x~256x Fs for 128kHz /176.4kHz/192kHz
z Wireless audio
z Supply voltage
3.3V for digital circuit
10V~26V for loudspeaker driver
Description
z Loudspeaker output power for Stereo@ 24V
AD82587D is a digital audio amplifier capable of
10W x 2ch into 8 @ 0.16% THD+N
driving a pair of 8,20W or a single 4,40W speaker,
both which operate with play music at a 24V supply
without external heat-sink or fan requirement.
z Loudspeaker output power for Mono@ 24V
Using I2C digital control interface, the user can control
AD82587Ds input format selection, mute and volume
control functions. AD82587D has many built-in
z Sounds processing including:
protection circuits to safeguard AD82587D from
Volume control (+24dB~-103dB, 0.125dB/step)
connection errors.
Dynamic range control
Power clipping
Channel mixing
User programmed noise gate with hysteresis window
DC-blocking high-pass filter
ORDERING INFORMATION
Product ID
AD82587D-LG48NAY
AD82587D-QG24NAT
Package
E-LQFP-48L
(7x7 mm)
E-TSSOP 24L
Packing / MPQ
Comments
2.5K Units / Small Box

(250 Units / Tray, 10 Trays /
Green
Small Box
62 Units / Tube
100 Tubes / Small Box
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Green
Publication Date: Apr. 2013

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Pin Assignment (Top View)

RA
N.C.
GNDR
N.C.
RB
VDDRB
VDDLB
LB
N.C.
GNDL
N.C.
LA
AD82587D
37
38
39
40
41
42
43
44
45
46
47
48
VDDLA
N.C.
N.C.
N.C.
N.C.
PLL
MCLK
CLK_OUT
DGND
DVDD
DEF
SDATA
VDDRA
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DVDD
DGND
SDA
36
35
34
33
5
6
32
AD82587D
31
30
E-LQFP-48L
8
9
10
29
28
27
11
26
12
25
VDDLA
PD
24
ERROR
23
NC
SDATA
22
LA
LRCIN
21
GNDL
SDA
20
LB
SCL
19
VDDLB
RESET
18
VDDRB
VSS
17
RB
VDD
16
GNDR
RA
24
23
22
21
20
19
18
17
16
15
14
13
SA0
10
15
MCLK
11
14
NC
BCLK
12
13
VDDRA
E-TSSOP-24L
SCL
N.C.
N.C.
SA1
SA0
RESET
ERROR
PD
BCLK
LRCIN
MONO
N.C.
Pin Description
NAME
E-LQFP E-TSSOP
TYPE
DESCRIPTION
CHARACTERISTICS
48L
24L
VDDLA
24
N.C.
NA
NC
N.C.
NA
NC
N.C.
NA
NC
N.C.
NA
NC
PLL
NA
PLL enable, low active
Schmitt trigger TTL input buffer
MCLK
11
Master clock input
CLK_OUT
NA
Clock output from PLL
TTL output buffer
DGND
NA
Digital Ground
DVDD
10
NA
Digital Power
DEF
11
NA
Default volume setting
SDATA
12
Serial audio data input
N.C.
13
NA
NC
MONO
14
NA
MONO mode enable, high active Schmitt trigger TTL input buffer
LRCIN
15
Left/Right clock input (Fs)
BCLK
16
12
Bit clock input (64Fs)
PD
17
Power down, low active
ERROR
18
Error status, low active
Open-drain output
Left channel supply A

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ESMT/EMP
RESET
19
Preliminary
I
Reset, low active

2
AD82587D
SA0
20
10
I C select address 0
SA1
21
NA
I2C select address 1
N.C.
22
NA
NC
N.C.
23
NA
NC
SCL
24
I2C serial clock input
SDA
25
I/O
I C bi-directional serial data
DGND
26
Digital Ground
DVDD
27
Digital Power
N.C.
28
NA
NC
N.C.
29
NA
NC
N.C.
30
NA
NC
N.C.
31
NA
NC
N.C.
32
NA
NC
N.C.
33
NA
NC
N.C.
34
NA
NC
N.C.
35
NA
NC
VDDRA
36
13
Right channel supply A
RA
37
15
Right channel output A
N.C.
38
14
NC
GNDR
39
16
N.C.
40
NA
NC
RB
41
17
Right channel output B
VDDRB
42
18
Right channel supply B
VDDLB
43
19
Left channel supply B
LB
44
20
Left channel output B
N.C.
45
NA
NC
GNDL
46
21
N.C.
47
23
NC
LA
48
22
Right channel ground
Left channel ground
Left channel output A

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ESMT/EMP
AD82587D
Preliminary
Functional Block Diagram
Available Package
Package Type
Device No.
ja(/W)
jt(/W)
jt(/W)
22.9
1.05
34.9
26.8
0.35
27.1
E-LQFP-48L
Exposed Thermal Pad
AD82587D
E-TSSOP 24L
Yes (Note1)
Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal performance,
soldering the thermal pad to the PCBs ground plane is suggested.
Note 1.2: ja is measured on a room temperature (TA=25), natural convection environment test board, which
is constructed with a thermally efficient, 4-layers PCB (2S2P). The measurement is tested using the
JEDEC51-5 thermal measurement standard.
Note 1.3: jt represents the heat resistance for the heat flow between the chip and the packages top surface.
Note 1.4: jt represents the heat resistance for the heat flow between the chip and the packages top surface
center.
Absolute Maximum Ratings

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Symbol
Parameter
Min
Max
Units
DVDD
Supply for Digital Circuit
-0.3
3.6
VDDL/R
Supply for Driver Stage
-0.3
30
Vi
Input Voltage
-0.3
3.6
Tstg
Storage Temperature
-65
150
150
TJ
Junction Operating Temperature
C
C

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Recommended Operating Conditions

Symbol
Parameter
Typ
Units
DVDD
Supply for Digital Circuit
3.15~3.45
VDDL/R
Supply for Driver Stage
10~26
TJ
Junction Operating Temperature
TA
Ambient Operating Temperature
0~125
0~70
C
C
General Electrical Characteristics

Condition: TA=25 oC (unless otherwise specified).
Symbol
Parameter
Condition
Min
Typ Max Units
IPD(HV)
PVDD Supply Current during Power Down
PVDD=24V
40
200
uA
IPD(LV)
DVDD Supply Current during Power Down
DVDD=3.3V
20
uA
160
Temperature Hysteresis for Recovery from Shutdown
35
UVH
Under Voltage Disabled (For DVDD)
2.8
UVL
Under Voltage Enabled (For DVDD)
2.7
TSENSOR
Junction Temperature for Driver Shutdown
C
C
PVDD=24V,
Id=500mA
260
175
L(R) Channel Over-Current Protection (Note 2)
PVDD=24V
5.2
Mono Channel Over-Circuit Protection (Note 2)
PVDD=24V
10.4
VIH
High-Level Input Voltage
DVDD=3.3V
VIL
Low-Level Input Voltage
DVDD=3.3V
VOH
High-Level Output Voltage
DVDD=3.3V
VOL
Low-Level Output Voltage
DVDD=3.3V
CI
Input Capacitance
Rds-on
ISC
Static Drain-to-Source On-state Resistor, PMOS

Static Drain-to-Source On-state Resistor, NMOS
2.0
V
0.8
2.4
V
V
0.4
6.4
V
pF
Note 2: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly
connected with external LC filters. Please refer to the application circuit example for recommended
LC filter configuration.
Marking Information
AD82587D
Line 1 : LOGO
Line 2 : Product no.
Line 3 : Tracking Code
Line 4 : Date Code
E-LQFP 48L
E-TSSOP-24L

Revision: 0.4
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ESMT/EMP
Preliminary
AD82587D
Application Circuit Example for Stereo

Revision: 0.4
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ESMT/EMP
Preliminary
AD82587D
Application Circuit Example for Stereo (Economic type, moderate EMI suppression)

Revision: 0.4
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ESMT/EMP
Preliminary
AD82587D
Application Circuit Example for Mono

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Electrical Characteristics and Specifications for Loudspeaker

z Stereo output with 24V supply voltage
Condition: TA=25 oC, DVDD=3.3V, VDDL=VDDR=24V, FS=48kHz, Load=8 with passive LC lowpass filter
(L=22H with RDC=0.12, C=470nF); Input is 1kHz sinewave. Volume is 0dB unless otherwise specified.
Symbol
Parameter
Condition
Input Level Min
Typ
RMS Output Power (THD+N=0.21%)
PO
(Note 9)
Max Units
20
15
10
0.14
+8dB volume
THD+N
Total Harmonic Distortion + Noise
PO=7.5W
SNR
Signal to Noise Ratio (Note 8)
+8dB volume
-9dB
97
dB
DR
Dynamic Range (Note 8)
+8dB volume
-68dB
105
dB
PSRR
Power Supply Rejection Ratio
77
dB
70
dB
VRIPPLE=1VRMS
at 1kHz
Channel Separation (non-shield choke) PO=1W at 1kHz

Note 8: Measured with A-weighting filter.
Note 9: Thermal dissipation is limited by package type and PCB design, the external heat-sink or system
cooling method should be adopted for RMS power output.
Total Harmonic Distortion + Noise vs. Output Power (Stereo)

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Total Harmonic Distortion + Noise vs. Frequency (Stereo)
Cross-talk (Stereo)
Frequency Response (Stereo)

+1
+1
24V, 8
Stereo
PO=1W
+0.8
dBr
+0.6
+0.8
+0.6
+0.4
+0.4
+0.2
+0.2
+0
+0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
-1
Frequency (Hz)

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Efficiency (Stereo)
Efficiency vs. Output Power (Stereo)
100
90
80
12V
15V
18V
24V
Efficiency(%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
2CH Output Power(W)
Efficiency (Stereo) for PWM of Power Saving Mode

Efficiency vs. Output Power (Stereo)
100
90
80
Efficiency(%)
70
Power saving mode enable

W/O power saving mode
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
2CH Output Power(W)

Revision: 0.4
11/45
ESMT/EMP
AD82587D
Preliminary
Electrical Characteristics and Specifications for Loudspeaker

z Mono output with 24V supply voltage
Condition: TA=25 oC, DVDD=3.3V, VDDL=VDDR=24V, FS=48kHz, Load=4 with passive LC lowpass filter
(L=10H with RDC=27m, C=470nF); Input is 1kHz sinewave. Volume is 0dB unless otherwise specified.
Symbol
Parameter
Condition
RMS Output Power (THD=0.24%)
+8dB volume
40
+8dB volume
30
+8dB volume
20
THD+N
Total Harmonic Distortion + Noise
Po=15W
0.15
SNR
Signal to Noise Ratio(Note 8)
+8dB volume
-9dB
97
dB
DR
Dynamic Range(Note 8)
+8dB volume
-68dB
105
dB
PSRR
Power Supply Rejection Ratio
77
dB
PO
(Note 9)
Input Level Min
VRIPPLE=1VRMS at
1kHz
Typ
Max Units
Note 8: Measured with A-weighting filter.

Note 9: Thermal dissipation is limited by package type and application PCB design, the external heat-sink or
system cooling method should be adopted for maximum power output.
THD+N (%)
Total Harmonic Distortion + Noise vs. Output Power (Mono)

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Total Harmonic Distortion + Noise vs. Frequency (Mono)
Frequency Response (Mono)

+1
+1
24V, 4
Mono
PO=1W
+0.8
dBr
+0.6
+0.8
+0.6
+0.4
+0.4
+0.2
+0.2
+0
+0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
-1
Frequency (Hz)

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Efficiency (Mono)
Efficiency vs. Output Power (Mono)
100
90
80
12V
15V
18V
24V
Efficiency(%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
Output Power(W)
Efficiency (Mono) for PWM of Power Saving Mode

Efficiency vs. Output Power (Mono)
100
90
80
Efficiency(%)
70
Power saving mode enable

W/O power saving mode
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Output Power(W)

Revision: 0.4
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ESMT/EMP
Preliminary
AD82587D
Interface Configuration
z I 2S
z Left-Alignment
z Right-Alignment
z System Clock Timing
z Timing Relationship (Using I2S format as an example)

Revision: 0.4
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ESMT/EMP
Symbol
AD82587D
Preliminary
Parameter
Min
Typ
10.41
Max
Units
31.25
tLR
LRCIN Period (1/FS)
tBL
BCLK Rising Edge to LRCIN Edge
50
ns
tLB
LRCIN Edge to BCLK Rising Edge
50
ns
tBCC
BCLK Period (1/64FS)
162.76
488.3
ns
tBCH
BCLK Pulse Width High
81.38
244
ns
tBCL
BCLK Pulse Width Low
81.38
244
ns
tDS
SDATA Set-Up Time
50
ns
tDH
SDATA Hold Time
50
ns
z I2C Timing
Parameter
Symbol
Standard Mode
Fast Mode
Unit
MIN.
MAX.
MIN.
MAX.
fSCL
100
400
kHz
tHD,STA
4.0
---
0.6
---
LOW period of the SCL clock
tLOW
4.7
---
1.3
---
HIGH period of the SCL clock
tHIGH
4.0
---
0.6
---
tSU;STA
4.7
---
0.6
---
Hold time for I C bus data
tHD;DAT
3.45
0.9
Setup time for I2C bus data
tSU;DAT
250
---
100
---
ns
Rise time of both SDA and SDL signals
tr
---
1000
20+0.1Cb
300
ns
Fall time of both SDA and SDL signals
tf
---
300
20+0.1Cb
300
ns
tSU;STO
4.0
---
0.6
---
tBUF
4.7
---
1.3
---
400
pF
SCL clock frequency

Hold time for repeated START condition
Setup time for repeated START condition

2
Setup time for STOP condition

Bus free time between STOP and the next
START condition
Capacitive load for each bus line
Noise margin at the LOW level for each
connected device (including hysteresis)
Noise margin at the HIGH level for each
connected device (including hysteresis)
Cb
400
VnL
0.1VDD
---
0.1VDD
---
VnH
0.2VDD
---
0.2VDD
---

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
Operation Description
z Reset
When the RESET pin is lowered, AD82587D will clear the stored data and reset the register table to
default values. AD82587D will exit reset state at the 256th MCLK cycle after the RESET pin is raised to
high.
z Power down control

AD82587D has a built-in volume fade-in/fade-out design for PD/Mute function. The relative PD timing
diagrams for loudspeakers are shown below.
(10
t arg et ( dB )
80
10
original ( dB )
80
) x512 x(1 / 96 K )
The volume level will be decreased to -dB in several LRCIN cycles. Once the fade-out procedure is
finished, AD82587D will turn off the power stages, clock signals (for digital circuits) and current (for analog
circuits). After PD pin is pulled low, AD82587D requires Tfade to finish the forementioned work before
entering power down state. Users can not program AD82587D during power down state. Also, all settings in
the registers will remain intact unless DVDD is removed.
If the PD signal is removed during the fade-out procedure (above, right figure), AD82587D will still execute
the fade-in procedure. In addition, AD82587D will establish the analog circuits bias current and send the
clock signals to digital circuits. Afterwards, AD82587D will return to its normal status.

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
z Internal PLL ( PLL )

AD82587D has a built-in PLL with multiple MCLK/FS ratio, which is selected by I2C control interface. If PLL
pin is pulled low, the built-in PLL is enabled; if PLL pin is pulled high, an external clock source for MCLK
less than 50MHz should be provided. The MCLK/FS ratio will be fixed at 1024x, 512x, or 256x with a sample
frequency of 48kHz, 96kHz, or 192kHz respectively.
When using AD82587D without I2C control interface, the operation is as follows.
PLL pin is set to high:

Internal PLL is bypassed (Disable). The following master clock frequency is inputted into a MCLK pin by
the sampling frequency. When the following master clock frequency cannot be inputted, PLL pin is set
low. A career clock frequency is the frequency divided by 128 of master clock.
Fs
MCLK frequency
48kHz
49.152MHz
44.1kHz
45.158MHz
32kHz
32.768MHz
PLL pin is set to low:

Internal PLL is enabled. The master clock inputted into the MCLK pin becomes the frequency of quad
edge evaluation. A career clock frequency is the frequency divided by 32 of master clock.
z Anti-pop design
AD82587D will generate appropriate control signals to suppress pop sounds during initial power on/off,
power down/up, mute, and volume level changes.
z Default volume (DEF)

The volume of AD82587D is +1.625dB when DEF pin is high, and the volume is muted when DEF pin low.
When using AD82587D without I2C control interface, user should set the pin high. The user can change the
values of the register table setting for volume control. For detailed information, refer to the register table
section.

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
z Self-protection circuits
AD82587D has built-in protection circuits including thermal, short-circuit and under-voltage detection circuits.
(i) When the internal junction temperature is higher than 160, power stages will be turned off and
AD82587D will return to normal operation once the temperature drops to 125. The temperature values
may vary around 10%.
(ii) The short-circuit protection circuit protects the output stage when the wires connected to loudspeakers
are shorted to each other or GND/VDD. For normal 24V operations, the current flowing through the
power stage will be less than 5A for stereo configuration or less than 10A for mono configuration.
Otherwise, the short-circuit detectors may pull the ERROR pin to DGND, disabling the output stages.
When the over-temperature or short-circuit condition occurs, the open-drain ERROR pin will be pulled
low and latched into ERROR state. Once the over-temperature or short-circuit condition is removed,
AD82587D will exit ERROR state when one of the following conditions is met: (1) RESET pin is pulled
low, (2) PD pin is pulled low, (3) Master mute is enabled through the I2C interface.
(iii) Once the DVDD voltage is lower than 2.7V, AD82587D will turn off its loudspeaker power stages and
cease the operation of digital processing circuits. When DVDD becomes larger than 2.8V, AD82587D
will return to normal operation.
(iv) If the master clock inputted into MCLK pin stops during the period for 500 ns or more, AD82587D detect
the stop of MCK. In this state, amplifier outputs are forced to Weak Low. If master clock is inputted
normally again, ERROR pin is set to low. AD82587D wont leave ERROR state until one of the
following conditions: (1) Reset pin is pulled low, (2) PD pin is pulled low, (3) Programming master mute
via I2C interface.
PD pin is set to low, when stop the clock inputted into MCLK, BCLK, and LRCIN during operation.
(v) If it will be in the state where PVDD power supply is OFF and DVDD power supply is ON, ERROR pin
is set to Low.

Revision: 0.4
19/45
ESMT/EMP
AD82587D
Preliminary
z Power on sequence
Hereunder is AD82587Ds power on sequence. Please note that we suggested users set DEF pin at low
state initially, and than give a de-mute command via I2C when the whole system is stable.
Symbol
Condition
Min
Max
Units
t1
msec
t2
msec
t3
10
msec
t4
msec
t5
10
msec
t6
10
msec
t7
msec
t8
200
msec
t9
20
msec
t10
DEF=L
0.1
msec
t11
DEF=H
0.1
msec
t12
25
msec
t13
25
msec
t14
22
msec
0.1
msec
t15
DEF= L or H

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
z Power off sequence

Hereunder is AD82587Ds power off sequence.
Symbol
Condition
Min
Max
Units
t1
35
msec
t2
0.1
msec
t3
msec
t4
msec
t5
msec

Revision: 0.4
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ESMT/EMP
AD82587D
Preliminary
I2C-Bus Transfer Protocol

z Introduction
AD82587D employs I2C-bus transfer protocol. Two wires, serial data and serial clock carry information
between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can
operate as either a transmitter or a receiver. The master device initiates a data transfer and provides the
serial clock on the bus. AD82587D is always an I2C slave device.
z Protocol
START and STOP condition
START is identified by a high to low transition of the SDA signal.. A START condition must precede
any command for data transfer. A STOP is identified by a low to high transition of the SDA signal. A
STOP condition terminates communication between AD82587D and the master device on the bus. In
both START and STOP, the SCL is stable in the high state.
Data validity
The SDA signal must be stable during the high period of the clock. The high or low change of SDA only
occurs when SCL signal is low. AD82587D samples the SDA signal at the rising edge of SCL signal.
Device addressing
The master generates 7-bit address to recognize slave devices. When AD82587D receives 7-bit
address matched with 0110x0y (where x and y can be selected by external SA0 and SA1 pins,
respectively), AD82587D will acknowledge at the 9th bit (the 8th bit is for R/W bit). The bytes following
the device identification address are for AD82587D internal sub-addresses.
Data transferring
Each byte of SDA signaling must consist of 8 consecutive bits, and the byte is followed by an
acknowledge bit. Data is transferred with MSB first, as shown in the figure below. In both write and
read operations, AD82587D supports both single-byte and multi-byte transfers. Refer to the figure
below for detailed data-transferring protocol.

Revision: 0.4
22/45
ESMT/EMP
AD82587D
Preliminary
Register Table
The audio signal processing data flow is shown as the following figure. Users can control these function by
programming appropriate setting to register table. In this section, the register table is summarized first. The
definition of each register follows in the next section.
Address
Register
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
0X00
SCTL1
IF[2]
IF[1]
IF[0]
LREXC
PWML_X
PWMRX
PwmMode
NGE
0X01
SCTL 2
FS[1]
FS[0]
PMF[3]
PMF[2]
PMF[1]
PMF[0]
0X02
SCTL 3
EN_CLKO
HPB
LV_UVSEL
SW_RSTB
MUTE
CM1
CM2
CompSDMEn
0X03
MVOL
MV[7]
MV[6]
MV[5]
MV[4]
MV[3]
MV[2]
MV[1]
MV[0]
0X04
C1VOL
C1V[7]
C1V[6]
C1V[5]
C1V[4]
C1V[3]
C1V[2]
C1V[1]
C1V[0]
0X05
C2VOL
C2V[7]
C2V[6]
C2V[5]
C2V[4]
C2V[3]
C2V[2]
C2V[1]
C2V[0]
0X06
HVUV
DIS_HVUV
HVUVSEL[3]
HVUVSEL[2]
HVUVSEL[1]
HVUVSEL[0]
0X07
SCTL 4
C1MX_EN
C2MX_EN
PC_EN
DRC_EN
MONO_EN
0X08
LAR
LA[3]
LA[2]
LA[1]
LA[0]
LR[3]
LR[2]
LR[1]
LR[0]
QTS[4]
QTS[3]
QTS[2]
QTS[1]
QTS[0]
Reserved
0X09 QT_SW_LEVEL
Reserved
Reserved
0X0A
Reserved
Reserved
0X0B
OC SET
Reserved
0X0C
STATUS
Reserved
0X0D
ACFG
Reserved
0X0E
TM_CTRL
Reserved
0X0F
PWM_CTRL
Reserved
0X10
ATT
0X11
ATM
ATM[7]
ATM[6]
0X12
ATB
ATB[7]
ATB[6]
Reserved
ATT[4]
ATT[3]
ATT[2]
ATT[1]
ATT[0]
ATM[5]
ATM[4]
ATM[3]
ATM[2]
ATM[1]
ATM[0]
ATB[5]
ATB [4]
ATB [3]
ATB [2]
ATB [1]
ATB [0]

Revision: 0.4
23/45
ESMT/EMP
AD82587D
Preliminary
0X13
PCT
0X14
PCM
PCM[7]
PCM[6]
0X15
PCB
PCB[7]
PCB[6]
0X16
NGG
Reserved
PCT[4]
PCT[3]
PCT[2]
PCT[1]
PCT[0]
PCM[5]
PCM[4]
PCM[3]
PCM[2]
PCM[1]
PCM[0]
PCB[5]
PCB [4]
PCB [3]
PCB [2]
PCB [1]
PCB [0]
NG_GAIN[1]
NG_GAIN[0]
DIS_ZD
Reserved
Reserved
_FADE
0X17
VFT
MV_FT[1]
MV_FT[0]
0X18
DTC
DTC_EN
DTC_TH[1]
C1V_FT[1]
C1V_FT[0]
C2V_FT[1]
C2V_FT[0]
DTC_TH[0] DTC_RATE[1] DTC_RATE[0]
0X19
Reserved
Reserved
Reserved
0X1A
NGALT
NGALT[7]
NGALT[6]
NGALT[5]
NGALT[4]
NGALT[3]
NGALT[2]
NGALT[1]
NGALT[0]
0X1B
NGALM
NGALM[7]
NGALM[6]
NGALM[5]
NGALM[4]
NGALM[3]
NGALM[2]
NGALM[1]
NGALM[0]
0X1C
NGALB
NGALB[7]
NGALB [6]
NGALB [5]
NGALB [4]
NGALB [3]
NGALB [2]
NGALB [1]
NGALB [0]
0X1D
NGRLT
NGRLT[7]
NGRLT[6]
NGRLT[5]
NGRLT[4]
NGRLT[3]
NGRLT[2]
NGRLT[1]
NGRLT[0]
0X1E
NGRLM
NGRLM[7]
NGRLM[6]
NGRLM[5]
NGRLM[4]
NGRLM[3]
NGRLM[2]
NGRLM[1]
NGRLM[0]
0X1F
NGRLB
NGRLB[7]
NGRLB [6]
NGRLB[5]
NGRLB[4]
NGRLB [3]
NGRLB [2]
NGRLB [1]
NGRLB [0]
0X20
DRC_ECT
DRC_ECT[7]
DRC_ECT[6]
DRC_ECT[5] DRC_ECT[4]
DRC_ECT[3]
DRC_ECT[2]
DRC_ECT[1]
DRC_ECT[0]
0X21
DRC_ECB
DRC_ECB[7]
DRC_ECB[6]
DRC_ECB[5] DRC_ECB[4]
DRC_ECB[3]
DRC_ECB[2]
DRC_ECB[1]
DRC_ECB[0]
0X22
RTT
RTT[4]
RTT[3]
RTT[2]
RTT[1]
RTT[0]
0X23
RTM
RTM[7]
RTM[6]
RTM[5]
RTM[4]
RTM[3]
RTM[2]
RTM[1]
RTM[0]
0X24
RTB
RTB[7]
RTB[6]
RTB[5]
RTB [4]
RTB [3]
RTB [2]
RTB [1]
RTB [0]
Reserved

Revision: 0.4
24/45
ESMT/EMP
AD82587D
Preliminary
Detail Description for Register

In this section, please note that the highlighted columns are the default value of these tables. If no highlighted, it
is because the default setting of this bit is determined by external pin.
z Address 0X00 : State control 1

AD82587D support multiple serial data input formats including I2S, Left-alignment and Right-alignment.
These formats is chosen by user via bit7~bit5 of address 0.
BIT
B[7:5]
NAME
IF[2:0]
DESCRIPTION
I S 16-24 bits
001
Left-alignment 16-24 bits
010
Right-alignment 16 bits
011
100
101
other
Reversed
Left/Right (L/R)
No exchanged
Channel Exchanged
L/R exchanged
No exchange
Exchange
No exchange
Exchange
Quarternary+Ternary
Quarternary
Disable
Enable
Input Format
LREXC
B[3]
PWML_X
LA/LB Exchange
B[2]
PWMR_X
RA/RB Exchange
B[0]
PwmMode
NGE
FUNCTION
2
000
B[4]
B[1]
VALUE
PWM Mmode
Noise Gate Enable

Revision: 0.4
25/45
ESMT/EMP
AD82587D
Preliminary

AD82587D has built-in PLL which can be bypassed by pull high the PLL pin. When PLL is enabled, multiple
MCLK/FS ratio is supported. Detail setting is shown as the above table.
BIT
NAME
DESCRIPTION
B[7:6]
Reserved
B[5:4]
FS
Sampling Frequency
VALUE
FUNCTION
00
32/44.1/48kHz
01
32/44.1/48kHz
10
64/88.2/96kHz
11
128/176.4/192kHz
Multiple MCLK/FS ratio setting table
BIT
NAME DESCRIPTION VALUE B[5:4]=00/01
Multiple
B[3:0] PMF[3:0]
MCLK/FS
Ratio Setting
B[5:4]=10
B[5:4]=11
Reset
Reset
Reset
Default
Default
Default
(256x)
(128x)
(64x)
0010
512x
256x
128x
0011
768x
384x
192x
0100
1024x
512x
256x
0001

Revision: 0.4
26/45
ESMT/EMP
AD82587D
Preliminary

To prevent the DC current from damaging the speaker, a high pass filter (3dB frequency = 5Hz ) is built into
the AD82587D. It can be enabled or disabled by bit 6 of address 2.
AD82587D has a mute function which includes master mute and individual channel mute modes. When the
master mute mode is enabled, both left and right processing channels are muted. On the other hand, either
channel can be muted by using the channel mute mode. When the mute function is enabled or disabled, the
fade-out or fade-in process will be initiated.
The default settings of B[3:1] are determined by DEF pin. When DEF pin is pulled low or high, the default
setting is muted or unmated.
BIT
B[7]
NAME
EN_CLK_
OUT
DESCRIPTION
VALUE
FUNCTION
Disabled
Enabled
DC Blocking HPF
Enable
Bypass
Disabled
LV Under Voltage
2.7V
Selection
3.0V
Reset
Normal operating
Un-Mute (DEF=1)
Mute (DEF=0)
Un-Mute (DEF=1)
Mute (DEF=0)
Un-Mute (DEF=1)
Mute (DEF=0)
Compensate SDM
Disable
Frequency Response
Enable
PLL Clock Output
B[6]
HPB
B[5]
LV_UVSEL
B[4]
SW_RSTB
Software reset
B[3]
MUTE
Master Mute
B[2]
CM1
Channel 1 Mute
B[1]
CM2
Channel 2 Mute
B[0]
CompSDMEn

Revision: 0.4
27/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X03 : Master volume

AD82587D supports both master-volume and channel-volume control for the stereo processing channels.
Both master volume control (Address 0X03) and channel volume (Address 0X04 and 0X05 ) settings range
from +12dB ~ -102dB. Given master volume level, say, Level A (in dB unit) and channel volume level, say
Level B (in dB unit), the total volume equals to Level A plus with Level B and its range is from +24dB ~
-102dB, i.e., -103dB Total Volume ( Level A + Level B ) +24dB.
BIT
B[7:0]
NAME
MV[7:0]
DESCRIPTION
Master Volume
VALUE
FUNCTION
00000000
+12dB
00000001
+11.5dB
00000010
+11dB
00010111
0.5dB
00011000
0dB
00011001
-0.5dB
11100110
-103dB
11100101
-dB
1111111
-dB
VALUE
FUNCTION
00000000
+12dB
00000001
+11.5dB
00010100
2dB
00011000
0dB
00011001
-0.5dB
11100110
-103dB
11100101
-dB
1111111
-dB
z Address 0X04 : Channel1 volume

BIT
B[7:0]
NAME
C1V[7:0]
DESCRIPTION
Channel 1 Volume

Revision: 0.4
28/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X05 : Channel2 volume

BIT
B[7:0]
NAME
C2V[7:0]
DESCRIPTION
Channel 2 Volume
VALUE
FUNCTION
00000000
+12dB
00000001
+11.5dB
00010100
2dB
00011000
0dB
00011001
-0.5dB
11100110
-103dB
11100101
-dB
1111111
-dB
z Address 0X06 : Under voltage selection for high voltage supply

AD82587D provides HV under voltage detection which can be enable or disable via bit 7. The under-voltage
detection level is programmable via bit3~ bit0. Once the output stage voltage drops below the preset value
(see table), AD82587D will fade out audio signals to turn off the speaker.
BIT
NAME
B[7]
Dis_HVUV
B[6:4]
B[3:0] HVUVSEL[3:0]
DESCRIPTION
VALUE
FUNCTION
Disable HV Under
Enable
Voltage Circuit
Disable
Other
9.7V
1100
19.5V
HV Under Voltage
0100
15.5V
Selection (Active)
0011
13.2V
0001
9.7V
0000
8.2V
Reserved

Revision: 0.4
29/45
ESMT/EMP
AD82587D
Preliminary

AD82587D provides channel mix, power clipping, and dynamic range control (DRC) function. These
functions can be enable or not as the following table.
BIT
NAME
B[7]
C1MX_EN
B[6]
C2MX_EN
B[5]
PC_EN
B[4]
DRC_EN
B[3]
MONO_EN
B[2:0]
DESCRIPTION
VALUE
FUNCTION
Channel1 Mixing
Disable(MONO=0)
Enable
Enable (MONO=1)
Channel2 Mixing
Disable(MONO=0)
Enable
Enable(MONO=1)
Power Clipping
Disable
Enable
Enable
Disable
Enable
MONO or Stereo
Stereo
Configure
MONO
DRC Enable
Reserved

Revision: 0.4
30/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X08 : Attack rate and Release rate for Dynamic Range Control (DRC)
The attack/release rates of AD82587D are defined as following table,
BIT
B[7:5]
B[3:0]
NAME
LA[3:0]
LR[3:0]
DESCRIPTION
DRC Attack Rate
DRC Release Rate
VALUE
FUNCTION
0000
3 dB/ms
0001
2.667 dB/ms
0010
2.182 dB/ms
0011
1.846 dB/ms
0100
1.333 dB/ms
0101
0.889 dB/ms
0110
0.4528 dB/ms
0111
0.2264 dB/ms
1000
0.15 dB/ms
1001
0.1121 dB/ms
1010
0.0902 dB/ms
1011
0.0752 dB/ms
1100
0.0645 dB/ms
1101
0.0563 dB/ms
1110
0.0501 dB/ms
1111
0.0451 dB/ms
0000
0.5106 dB/ms
0001
0.1371 dB/ms
0010
0.0743 dB/ms
0011
0.0499 dB/ms
0100
0.0360 dB/ms
0101
0.0299 dB/ms
0110
0.0264 dB/ms
0111
0.0208 dB/ms
1000
0.0198 dB/ms
1001
0.0172 dB/ms
1010
0.0147 dB/ms
1011
0.0137 dB/ms
1100
0.0134 dB/ms
1101
0.0117 dB/ms
1110
0.0112 dB/ms
1111
0.0104 dB/ms

Revision: 0.4
31/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X09 : Power saving mode switching level

If the PWM exceeds the programmed switching power level (default 30*40ns), the modulation algorithm will
change from quaternary to ternary modulation. Ternary modulation has less switching loss, resulting in
higher power efficiency during larger power output operations. If the PWM drops below the programmed
switching power level, the modulation algorithm will change back to quaternary modulation.
BIT
NAME
DESCRIPTION
B[7:5]
Reserved
B[4:0]
QTS[4:0]
VALUE
FUNCTION
11111
62
11110
60
Quaternary and
10000
32
Ternary Switching
01111
30
Level
01110
28
01101
26
00001
00000
Total Harmonic Distortion + Noise v.s. Output Power

2
Quaternary
Q+T level 20
0.7
Q+T level 40
0.5
%
24V, 8
Q+T level 30
Q+T level 46
0.3
0.2
0.08
0.06
0.04
9 10
20

Revision: 0.4
32/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X10 : Top 5 bits of attack threshold for Dynamic Range Control (DRC)
The AD82587D provides dynamic range control function. When the input RMS exceeds the programmable
attack threshold value, the output power will be limited by this threshold power level via gradual gain
reduction. Attack threshold is defined by 21-bit representation composed of registers controlled by I2C. The
device addresses of DRC attack threshold are 0X10, 0X11, and 0X12.
BIT
NAME
DESCRIPTION
VALUE
FUNCTION
B[7:5]
Reserved
B[4:0]
ATT[4:0]
Top 5 Bits of Attack
User programmed
Threshold
01000
0dB
z Address 0X11 : Middle 8 bits of attack threshold

BIT
NAME
B[7:0]
ATM[7:0]
DESCRIPTION
VALUE
FUNCTION
Middle 8 Bits of Attack
User programmed
Threshold
00000000
0dB
DESCRIPTION
VALUE
FUNCTION
Bottom 8 bits of attack
User programmed
threshold
00000000
0dB
z Address 0X12 : Bottom 8 bits of attack threshold

BIT
NAME
B[7:0]
ATB[7:0]

Revision: 0.4
33/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X13 : Top 8 bits of power clipping

The AD82587D provides power clipping function to avoid excessive signal that may destroy loud speaker.
The power clipping level is defined by 21-bit representation composed of registers controlled by I2C. The
device addresses of power clipping threshold are 0X13, 0X14, and 0X15.
BIT
NAME
DESCRIPTION
VALUE
FUNCTION
B[7:5]
Reserved
B[4:0]
PCT[4:0]
Top 5 Bits of Power
User programmed
Clipping Level
01000
0dB
DESCRIPTION
VALUE
FUNCTION
Middle 8 Bits of Power
User programmed
Clipping Level
00000000
0dB
z Address 0X14 : Middle 8 bits of power clipping

BIT
NAME
B[7:0]
PCM[7:0]
z Address 0X15 : Bottom 8 bits of power clipping level

BIT
NAME
B[7:0]
PCB[7:0]
DESCRIPTION
VALUE
FUNCTION
Bottom 8 Bits of Power
User programmed
Clipping Level
00000000
0dB
The following table shows the power clipping levels numerical representation.
Sample calculation for power clipping
Max
Hex
dB
Linear
Decimal
PVDD
524288
80000
PVDD*0.707
-3
0.707
370727
5A827
PVDD*0.5
-6
0.5
262144
40000
PVDD*L
D=524288xL
H=dec2hex(D)
amplitude
L=10(x/20)
(2.19 format)

Revision: 0.4
34/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X16 : Noise gate gain control

AD82587D provide noise gate function if receiving 2048 signal sample points less than noise gate attack
level. User can change noise gate gain via bit1~ bit0. When noise gate function occurs, input signal will
multiply noise gate gain (x1/8, x1/4 x1/2, x0). User can select fade out or not via bit 4.
BIT
NAME
DESCRIPTION
B[7:5]
Reserved
B[4]
DIS_NG_FADE
B[3:2]
B[1:0]
NG_GAIN
VALUE
FUNCTION
Disable Noise Gate
Fade
Fade
No fade
00
x1/8
Noise Gate
01
x1/4
Detection Gain
10
x1/2
11
Mute
Reserved
z Address 0X17 : Volume fine tune

AD82587D supports both master-volume fine tune and channel-volume control fine tune modes. Both
volume control settings range from 0dB ~ -0.375dB and 0.125dB per step. Note that the master volume fine
tune is added to the individual channel volume fine tune as the total volume fine tune.
BIT
B[7:6]
B[5:4]
B[3:2]
B[1:0]
NAME
MV_FT
C1V_FT
C2V_FT
DESCRIPTION
VALUE
FUNCTION
00
0dB
Master Volume Fine
01
-0.125dB
Tune
10
-0.25dB
11
-0.375dB
00
0dB
Channel 1 Volume Fine
01
-0.125dB
Tune
10
-0.25dB
11
-0.375dB
00
0dB
Channel 2 Volume Fine
01
-0.125dB
Tune
10
-0.25dB
11
-0.375dB
Reserved

Revision: 0.4
35/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X18 : Dynamic Temperature Control (DTC)

AD82587D supports dynamic temperature control. The table describes the setting of DTC.
BIT
NAME
DESCRIPTION
B[7]
DTC_EN
DTC Enable
B[6:5]
B[4:3]
B[2:0]
DTC_TH
DTC_RATE
VALUE
FUNCTION
Disable
Enable
00
110 oC
01
120 oC
10
130 oC
11
140 oC
00
1dB/sec
DTC Attack and
01
0.5dB/sec
Release Rate
10
0.33dB/sec
11
0.25dB/sec
DTC Threshold
Reserved
Release threshold is always 10 oC smaller than attack threshold.

For example:
DTC threshold (attack threshold) =130 oC, the release threshold = 120 oC.
DTC threshold (attack threshold) =120 oC, the release threshold = 110 oC.
If junction temperature (Tj) exceeds 130 oC, amplifier gain will be lowered to timing of 1dB/sec. If amplifier
gain falls and junction temperature (Tj) turns into less than 130 oC and larger than 120 oC, the gain will not
increase or decrease. If amplifier gain falls and junction temperature (Tj) turns into less than 120 oC,
amplifier gain will be raised to timing of 1dB/sec.

Revision: 0.4
36/45
ESMT/EMP
Preliminary
AD82587D
z Address 0X1A : Top 8 bits of noise gate attack level

When both left and right signals have 2048 consecutive sample points less than the programmable noise
gate attack level, the audio signal will multiply noise gate gain, which can be set at x1/8, x1/4, x1/2, or zero if
the noise gate function is enabled. Noise gate attack level is defined by 24-bit representation composed of
registers controlled by I2C. The device addresses of noise gate attack level are 0X1A, 0X1B, and 0X1C
BIT
NAME
B[7:0]
NGALT[7:0]
DESCRIPTION
VALUE
FUNCTION
Top 8 Bits of Noise
User programmed
Gate Attack Level
00000000
-110dB
z Address 0X1B : Middle 8 bits of noise gate attack level

BIT
NAME
B[7:0]
NGALM[7:0]
DESCRIPTION
VALUE
FUNCTION
Middle 8 Bits of Noise
User programmed
Gate Attack Level
00000000
-110dB
z Address 0X1C : Bottom 8 bits of noise gate attack level

BIT
NAME
B[7:0]
NGALB[7:0]
DESCRIPTION
VALUE
FUNCTION
Bottom 8 Bits of Noise
User programmed
Gate Attack Level
00011010
-110dB

Revision: 0.4
37/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X1D : Top 8 bits of noise gate release level

After entering the noise gating status, the noise gain will be removed whenever AD82587D receives any
input signal that is more than the noise gate release level. Noise gate release level is defined by 24-bit
representation composed of registers controlled by I2C. The device addresses of noise gate release level
are 0X1D, 0X1E, and 0X1F.
BIT
NAME
B[7:0]
NGRLT[7:0]
DESCRIPTION
VALUE
FUNCTION
Top 8 Bits of Noise
User programmed
Gate Release Level
00000000
-100dB
z Address 0X1E : Middle 8 bits of noise gate release level

BIT
NAME
B[7:0]
NGRLM[7:0]
DESCRIPTION
VALUE
FUNCTION
Middle 8 Bits of Noise
User programmed
Gate Release Level
00000000
-100dB
z Address 0X1F : Bottom 8 bits of noise gate release level

BIT
NAME
B[7:0]
NGRLB[7:0]
DESCRIPTION
VALUE
FUNCTION
Bottom 8 Bits of Noise
User programmed
Gate Release Level
01010011
-100dB
The following table shows the noise gate attack and release threshold levels numerical representation.
Sample calculation for noise gate attack and release level
Input amplitude
(dB)
0
Decimal
8388607
7FFFFF
83
53
26
1A
D=8388607xL
H=dec2hex(D)
-5
-100
10
-110
10-5.5
Hex
Linear
L=10
(x/20)
(1.23 format)

Revision: 0.4
38/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X20 : Top 8 bits of DRC energy coefficient

BIT
NAME
B[7:0] DRC_ECT [7:0]
DESCRIPTION
VALUE
FUNCTION
Top 8 Bits of DRC
User programmed
Energy Coefficient
00000000
1/256
z Address 0X21 : Bottom 8 bits of DRC energy coefficient

BIT
B[7:0]
NAME
DESCRIPTION
VALUE
FUNCTION
DRC_ECB
Bottom 8 Bits of DRC
User programmed
[7:0]
Energy Coefficient
00010000
1/256
The above figure illustrates the digital processing of calculating RMS signal power. In this processing, a DRC
energy coefficient is required, which can be programmed for different frequency range. Energy coefficient is
defined by 16-bit representation composed of registers controlled by I2C. The device addresses of DRC energy
coefficient are 0X20, and 0X21. The following table shows the DRC energy coefficient numerical representation.
Sample calculation for DRC energy coefficient
DRC energy
Hex
dB
Linear
Decimal
4095
FFF
1/256
-48.2
1/256
16
10
1/1024
-60.2
1/1024
D=4095xL
H=dec2hex(D)
coefficient
L=10
(x/20)
(1.12 format)

Revision: 0.4
39/45
ESMT/EMP
AD82587D
Preliminary
z Address 0X22 : Top 8 bits of release threshold for Dynamic Range Control (DRC)
After AD82587D has reached the attack threshold, its output power will be limited to that level. The output
power level will be gradually adjusted to the programmable release threshold level. Release threshold is
defined by 21-bit representation composed of registers controlled by I2C. The device addresses of release
threshold are 0X22, 0X23, and 0X24.
BIT
NAME
DESCRIPTION
VALUE
FUNCTION
B[7:5]
Reserved
B[4:0]
RTT[4:0]
Top 5 Bits of
User programmed
Release Threshold
00000010
-6dB
DESCRIPTION
VALUE
FUNCTION
Middle 8 Bits of
User programmed
Release Threshold
00000000
-6dB
DESCRIPTION
VALUE
FUNCTION
Bottom 8 Bits of
User programmed
Release Threshold
00000000
-6dB
z Address 0X23 : Middle 8 bits of release threshold

BIT
NAME
B[7:0]
RTM[7:0]
z Address 0X24 : Bottom 8 bits of release threshold

BIT
NAME
B[7:0]
RTB[7:0]
The following table shows the attack and release thresholds numerical representation.
Sample calculation for attack and release threshold
Hex
Power
dB
Linear
Decimal
(PVDD^2)/R
524288
80000
(PVDD^2)/2R
-3
0.5
262144
40000
(PVDD^2)/4R
-6
0.25
131072
20000
D=524288xL
H=dec2hex(D)
((PVDD^2)/R)*L
L=10
(x/10)
(2.19 format)

Revision: 0.4
40/45
ESMT/EMP
AD82587D
Preliminary
To best illustrate the dynamic range control function, please refer to the following figure.

Revision: 0.4
41/45
ESMT/EMP
AD82587D
Preliminary
Package Dimensions
z E-LQFP 48L (7x7mm)
Symbol
A
A1
b
c
D
D1
E
E1
e
L
Dimension in mm
Min
Max
-1.60
0.05
0.15
0.17
0.27
0.09
0.20
6.90
7.10
8.90
9.10
6.90
7.10
8.90
9.10
0.50 BSC
0.45
0.75
Exposed pad
D2
E2
Dimension in mm
Min
Max
4.31
5.21
4.31
5.21

Revision: 0.4
42/45
ESMT/EMP
Preliminary
AD82587D
Package Dimensions
z E-TSSOP 24L
Symbol
A
A1
b
c
D
E
E1
e
L
Dimension in mm
Min
Max
1.00
1.20
0.00
0.15
0.19
0.30
0.09
0.20
7.70
7.90
4.30
4.50
6.30
6.50
0.65 BSC
0.45
0.75
Exposed pad
Dimension in mm
D2
3.70
4.62
E2
2.20
2.85

Revision: 0.4
43/45
ESMT/EMP
AD82587D
Preliminary
Revision History
Revision
Date
0.1
2012.08.27
Original.
2013.01.07
1) Update address 0X02, register table B[4] content.

2) Improved OC protection level on this version.
3) Updated package thermal data2.
4) Added Power-OFF sequence into this datasheet.
0.2
0.3
2013.02.08
Description
1) Fade-out and fade-in time formula revised.

2) Added DTC explanation at address 0X18.
3) Showed jt values to replace of jb.
0.4
2013.04.26
1) Modify the typical value of ISC in General Electrical

Characteristics.
2) Modify color for curve and legend.

Revision: 0.4
44/45
ESMT/EMP
Preliminary
AD82587D
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express, implied
or otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.

Revision: 0.4
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ESMT/EMP

2X20W Stereo / 1X40W Mono Digital Audio Amplifier

2.5K Units / Small Box

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Pin Assignment (Top View)

PLL enable, low active

Schmitt trigger TTL input buffer

Master clock input

Schmitt trigger TTL input buffer

Clock output from PLL

TTL output buffer

Default volume setting

Schmitt trigger TTL input buffer

Serial audio data input

Schmitt trigger TTL input buffer

Left/Right clock input (Fs)

Schmitt trigger TTL input buffer

Bit clock input (64Fs)

Schmitt trigger TTL input buffer

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Schmitt trigger TTL input buffer

Error status, low active

Left channel supply A

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Reset, low active

Schmitt trigger TTL input buffer

I2C select address 1

Schmitt trigger TTL input buffer

I2C serial clock input

Schmitt trigger TTL input buffer

I C bi-directional serial data

Right channel supply A

Right channel output A

Right channel output B

Right channel supply B

Left channel supply B

Left channel output B

Schmitt trigger TTL input buffer

Right channel ground

Left channel ground

Left channel output A

Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.

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Functional Block Diagram

Exposed Thermal Pad

Absolute Maximum Ratings

Supply for Digital Circuit

Supply for Driver Stage

Junction Operating Temperature

Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.

Publication Date: Apr. 2013

Recommended Operating Conditions

Supply for Digital Circuit

Supply for Driver Stage

Junction Operating Temperature

Ambient Operating Temperature

General Electrical Characteristics