PSD Computation Using Modified Welch Algorithm
PSD Computation Using Modified Welch Algorithm
ABSTRACT
Power Spectral Density (PSD) shows strength of energy
as a function of frequency. PSD computation can be
done by the method called FFT. Welch algorithm is used
to calculate Power Spectral Density. High computational
complexity is the main drawback of Welch method. By
using 50% overlap we are reducing the computational
complexity of Welch method. Here N/2 point FFT is
computed instead of N-point FFT and we are using
Windowing in frequency domain for high performance.
In this approach even samples are computed exactly but
odd samples required half sample delay shift. So,
overlap method reduces the computational complexity as
half of the normal method. To reduce area, pipeline stage
is introduced instead of parallel structure.
Keywords - Power Spectral Density, Low complexity,
Low power, Welch method, Windowing, Fast Fourier
Transform.
1. INTRODUCTION
PSD is used for analysis and tracking the signal. PSD
shows input signal over range of frequencies. PSD is
divided into two groups Parametric and Non-parametric.
Parametric generate underlay signal and it consist of
different methods such as, autoregressive moving
average(ARMA), model identification, minimum
variance distortion less response method (MVDR) and
Eigen decomposition based methods. Non-parametric
method consist of two methods periodogram based
method and multiple-window method. The periodogram
methods include the computation of the Fourier
transform of the signals. Welch PSD method is to
estimate the power spectral density and is a nonparametric approach based on the periodogram method.
This low-complexity architecture suitable for low-power
embedded systems. Parameters such area, performance
and power consumption should be a consideration while
PSD computation into biomedical monitoring systems.
FFT is the main part of the Welch method. Here 50%
overlap is used and dividing the input signal into
multiple segments. Also 50% overlap is used and
dividing the input signal into multiple segments. Half of
the samples are same over two consecutive FFT
functions.
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 9, September 2015
3. WELCH ALGORITHM
New method for PSD [1] computation is described as,
The input is divided into (L+1) non overlap
segment where L is the number of segments.
An N/2-point FFT is applied to segment.
N-point FFT is computed by combining two
N/2-point FFT.
Windowing is applied in frequency domain.
The periodogram of each window segment is
computed.
Taking the average of modified periodogram.
The main components are FFT and absolute-square
multiple accumulator (AMAC) circuit. This is actually
used to compute FFT.AMAC circuit is to compute the
periodogram and average them over segment. AMAC
block, which stores the values of L different
periodograms. To correctly accumulate the periodogram
outputs the control block which controls the address
decoder and multiplexer. In the case of overlap method
952
International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 9, September 2015
AREA(s)
DELAY(ns)
EXISTING
METHOD
6527
16.29
MODIFIED
METHOD
1215
18.33
Table.1Simulation results
Simulation Waveforms
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953
International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 9, September 2015
6. CONCLUSION
In the presented paper designed a pipelined architecture
instead of parallel architecture in Welch PSD calculation
which gives better complexity reduction than parallel
design. The main advantage of this design is, it reduces
area. Similarly, it could increase maximum throughput
by designing in pipelined architecture. Overlapping
(50%) technique is used to reduce complexity of PSD
computation. Another benefit of this design is that it
technology independent. This design gives maximum
performance in FPGA.This paper discussed about
Pipeline Digit-Slicing Multiplier less circuit for FFT
structure. It concluded that FPGA Implementation of
Pipeline Digit-Slicing Multiplier-Less circuit for FFT
Structure is an enabler in solving problems that affect
communications capability in FFT and possesses huge
potentials for future related works and research areas.
REFERENCES
[1]Keshab K. Parhi, Fellow, IEEE, and Manohar
Ayinala, Member, IEEE, Low Complexity Welch
Power Spectral Density Computation. Vol. 61, No. 1,
January 2014.
[2]Yazan Samir Algnabi,RozitaTeymourzadeh, Masuri
Othman, MdShabiul Islam, FPGA Implementation of
Pipeline Digit-Slicing Multiplier-Less Radix 22 DIF
SDF Butterfly for Fast Fourier Transform Structure.
UniversitiKebangsaan Malaysia, 43600 Bangi, Selangor,
Malaysia.
[3] Y. Zhou, J. M. Noras, and S. J. Shephend, "Novel
design of multiplier-less FFT processors," Signal Proc.,
vol. 87, pp. 1402-1407, 2007.
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