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The document contains 11 questions related to digital circuits and computer architecture topics such as: 1. The maximum and minimum values for 16-bit 2's complement and 1's complement numbers. 2. The maximum number of logic functions possible for n variables. 3. Whether physical or virtual addresses are typically larger. 4. The purpose of a Translation Lookaside Buffer (TLB) in computing. 5. Designing a state machine to implement a noise eliminator circuit. 6. Implementing logic functions using multiplexers without gates. 7. Writing a C/C++ program to implement a stack with basic functions. 8. Calculating the required clock frequency

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1K views1 page

N VIDIA

The document contains 11 questions related to digital circuits and computer architecture topics such as: 1. The maximum and minimum values for 16-bit 2's complement and 1's complement numbers. 2. The maximum number of logic functions possible for n variables. 3. Whether physical or virtual addresses are typically larger. 4. The purpose of a Translation Lookaside Buffer (TLB) in computing. 5. Designing a state machine to implement a noise eliminator circuit. 6. Implementing logic functions using multiplexers without gates. 7. Writing a C/C++ program to implement a stack with basic functions. 8. Calculating the required clock frequency

Uploaded by

rAM
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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1-6 are multiple choice questions)

1. The max. value and min. value of 16-bit 2's complement (hex, dec,
binary)?
2. The max.,min. value of 16-bit 1's complement (hex, dec, binary)?
3. max. no. of logic functions for n-variables? ans: 2^2^n
4. about physical and virtual address, which is greater?
5. TLB (Translation Lookahead Buffer) is used for ?
options:
1. L1 cache misses
2. L2 cache miss
3. some thing page miss (not remembered exactly)

6. Minimum no. of P and N Mos transistors required to implement The


logic
Function Y= !(A | B & C) using CMOS
1. 1 p & 3 n
2. 3 p & 1 n
3. 3 p & 3 n

7.One shot digital circuit

8.Noise eliminator (both -ve and +ve pulses of one clock cycle duration)
__ __ __ __ __ __ __ __ __
__| |__| |__| |__| |__| |__| |__| |__| |__| | --> Clock
__ __ __ __ __ __ _________ --> Input
________| |___________| |_____|
__ __ __ ____________ --> Output
________________________________|

Observe the one clock delay in output.

Design a state machine for this operation.

9. Implement the following 2 functions using only 2x1 MUX without gates.
U can use 1 or 0 for inputs.

a) Y = AB+not(C) b) Y = A xor B

10. Write a program in C or C++ to implement Stack and its functions


such as
isEmpty, isFull, Push, Pop, Init etc. (I think based on the question
given,
array implementation is sufficient)

11. Question on clock frequency required for given Sequential ckt.


Given 2 F/Fs, 3 delays ( 2 delays for clock dly1, dly2 and 1 delay
dly3 of
combinational circuit ) given setup, hold and propagation times

Ans: T+(dly2-dly1) >= Tpd + dly3 + Tsetup


Tpd + dly3 > Thold + (dly2-dly1)

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