Configurable

Mixed-Signal Array
with On-board Controller
CY8C25122, CY8C26233, CY8C26443, CY8C26643
Device Data Sheet for Silicon Revision D
Programmable System-on-Chip (PSoC)

CYPRESS MICROSYSTEMS

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

CYPRESS MICROSYSTEMS

Getting Started in the PSoC World!

The award winning PSoC Designer software and PSoC silicon are an integrated unit. The quickest path to understanding the PSoC silicon is through the PSoC Designer software GUI. This data sheet is useful for understanding the
details of the PSOC integrated circuit, but is not a good starting point for a new PSoC developer seeking to get a general overview of this new technology.
PSoC developers are NOT required to build their own ADCs, DACs, and other peripherals. Embedded in the PSoC
Designer software are the individual data sheets, performance graphs, and PSoC User Modules (graphically selected
code packets) for the peripherals, such as the incremental ADCs, DACs, LCD controllers, op amps, low-pass filters,
etc. With simple GUI-based selection, placement, and connection, the basic architecture of a design may be
developed within PSoC Designer software without ever writing a single line of code.
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress.com
http://www.onfulfillment.com/cypressstore/ Online Store also contains development kits, C compilers, and all accessories for PSoC development.
PSoC "Tele-training" is available for beginners every Friday at 10 am Pacific Time taught by a live marketing or application engineer over the phone. Please see http://www.cypress.com/ under Support >> Tele-Training for more details.
Five training classes are available to accelerate the learning curve including introduction, designing, debugging,
advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus.
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or
become a PSoC Consultant go to the following web site, http://www.cypress.com/support/cypros.cfm.
Finally, PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.

Cypress MicroSystems / Cypress Semiconductor

2700 162nd Street SW, Building D
Lynnwood, WA 98037
Phone: 425.787.4400
Fax: 425.787.4641
Application Support Hotline: 425.787.4814
http://www.cypressmicro.com/ http://www.cypress.com/aboutus/sales_locations.cfm [email protected]

Cypress MicroSystems, Inc. 2000-2003. All rights reserved. PSoC (Programmable System-on-Chip) and PSoC Desgner are trademarks of Cypress
MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not
authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in life-support system applications implies that the manufacturer assumes all
risk of such use and in doing so, indemnifies Cypress MicroSystems against all charges.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

The PSoC CY8C25122/CY8C26233/CY8C26443/CY8C26643 family of programmable system-on-chip devices replace multiple MCU-based system components with one single-chip, configurable device. A PSoC device includes configurable analog and digital peripheral blocks, a fast
CPU, Flash program memory, and SRAM data memory in a range of convenient pin-outs and
memory sizes. The driving force behind this innovative programmable system-on-chip comes
from user configurability of the analog and digital arrays: the PSoC blocks.
Programmable System-on-Chip (PSoC) Blocks

Partial Flash updates

On-chip, user configurable analog and digital

peripheral blocks

Flexible protection modes

PSoC blocks can be used individually or in combination

EEPROM emulation in Flash, up to 2,304 bytes

12 Analog PSoC blocks provide:

Up to 11 bit Delta-Sigma ADC

Up to 8 bit Successive Approximation ADC
Up to 12 bit Incremental ADC
Up to 9 bit DAC
Programmable gain amplifier
Programmable filters
Differential comparators

8 Digital PSoC blocks provide:

Multipurpose timers: event timing, real-time clock,

pulse width modulation (PWM) and PWM with

deadband

CRC modules
Full-duplex UARTs
SPI master or slave configuration
Flexible clocking sources for analog PSoC blocks
Powerful Harvard Architecture Processor with Fast
Multiply/Accumulate

M8C processor instruction set

Programmable Pin Configurations

Schmitt trigger TTL I/O pins

Logic output drive to 25 mA with internal pull-up or

pull-down resistors, High Z, or strong driver

Interrupt on pin change

Analog output drive to 40 mA

Precision, Programmable Clocking

Internal 24/48 MHz Oscillator (+/- 2.5%, no external

components)

External 32.768 kHz Crystal Oscillator (optional precision source for PLL)

Internal Low Speed Oscillator for Watchdog and

Sleep

Dedicated Peripherals

Watchdog and Sleep Timers

Low Voltage Detection with user-configurable

threshold voltages

On-chip voltage reference

Fully Static CMOS Devices using advanced Flash

technology

Processor speeds to 24 MHz

Register speed memory transfers
Flexible addressing modes
Bit manipulation on I/O and memory
8x8 multiply, 32-bit accumulate

Flexible On-Chip Memory

Low power at high speed

Operating voltage from 3.0 to 5.25 V

Operating voltage down to 1.0 V using on-chip

switch mode voltage pump

Wide temperature range: -40 oC to + 85 oC

Flash program storage, 4K to 16K bytes, depending

on device

Complete Development Tools

50,000 erase/write cycles

Powerful integrated development environment

(PSoC Designer)

Low-cost, in-circuit emulator and programmer

256 bytes SRAM data storage

In-System Serial Programming (ISSP)

August 18, 2003

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

CYPRESS MICROSYSTEMS
This page has intentionally been left blank.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Table of Contents

1.0 Functional Overview ......................................................................................................................14

1.1 Key Features ..............................................................................................................................14
1.2 Pin-out Descriptions ...................................................................................................................15
2.0 CPU Architecture ............................................................................................................................19
2.1 Introduction ................................................................................................................................19
2.2 CPU Registers ...........................................................................................................................20
2.3 Addressing Modes .....................................................................................................................21
2.4 Instruction Set Summary ...........................................................................................................25
3.0 Memory Organization .....................................................................................................................26
3.1 Flash Program Memory Organization ........................................................................................26
3.2 RAM Data Memory Organization ...............................................................................................26
4.0 Register Organization ....................................................................................................................26
4.1 Introduction ................................................................................................................................26
4.2 Register Bank 0 Map .................................................................................................................27
4.3 Register Bank 1 Map ................................................................................................................28
5.0 I/O Ports ...........................................................................................................................................29
5.1 Introduction ................................................................................................................................29
6.0 I/O Registers ...................................................................................................................................31
6.1 Port Data Registers ...................................................................................................................31
6.2 Port Interrupt Enable Registers .................................................................................................31
6.3 Port Global Select Registers .....................................................................................................32
7.0 Clocking ..........................................................................................................................................35
7.1 Oscillator Options .......................................................................................................................35
7.2 System Clocking Signals ............................................................................................................38
8.0 Interrupts .........................................................................................................................................42
8.1 Overview ....................................................................................................................................42
8.2 Interrupt Control Architecture .....................................................................................................44
8.3 Interrupt Vectors .........................................................................................................................44
8.4 Interrupt Masks ..........................................................................................................................45
8.5 Interrupt Vector Register ...........................................................................................................46
8.6 GPIO Interrupt ............................................................................................................................47
9.0 Digital PSoC Blocks .......................................................................................................................48
9.1 Introduction ................................................................................................................................48
9.2 Digital PSoC Block Bank 1 Registers .........................................................................................49
9.3 Digital PSoC Block Bank 0 Registers .........................................................................................54
9.4 Global Inputs and Outputs .........................................................................................................60
9.5 Available Programmed Digital Functionality ...............................................................................60
10.0 Analog PSoC Blocks ....................................................................................................................71
10.1 Introduction ..............................................................................................................................71
10.2 Analog System Clocking Signals .............................................................................................72
10.3 Array of Analog PSoC Blocks .................................................................................................72
10.4 Analog Reference Control ........................................................................................................73
10.5 Analog PSoC Block Clocking Options ......................................................................................76
10.6 Analog Clock Select Register ..................................................................................................77
10.7 Analog Continuous Time PSoC Blocks ....................................................................................80

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.8 Analog Switch Cap Type A PSoC Blocks ................................................................................85

10.9 Analog Switch Cap Type B PSoC Blocks ................................................................................94
10.10 Analog Comparator Bus .......................................................................................................101
10.11 Analog Synchronization .......................................................................................................101
10.12 Analog I/O ............................................................................................................................103
10.13 Analog Modulator .................................................................................................................106
10.14 Analog PSoC Block Functionality .........................................................................................107
10.15 Temperature Sensing Capability ..........................................................................................108
11.0 Special Features of the CPU ......................................................................................................109
11.1 Multiplier/Accumulator ............................................................................................................109
11.2 Decimator ...............................................................................................................................112
11.3 Reset ......................................................................................................................................114
11.4 Sleep States ...........................................................................................................................116
11.5 Supply Voltage Monitor ..........................................................................................................118
11.6 Switch Mode Pump ................................................................................................................119
11.7 Internal Voltage Reference ....................................................................................................120
11.8 Supervisor ROM/System Supervisor Call Instruction .............................................................120
11.9 Flash Program Memory Protection ........................................................................................122
11.10 Programming Requirements and Step Descriptions ............................................................122
11.11 Programming Wave Forms .................................................................................................124
11.12 Programming File Format ....................................................................................................124
12.0 Development Tools ...................................................................................................................125
12.1 Overview ................................................................................................................................125
12.2 Integrated Development Environment Subsystems ...............................................................126
12.3 Hardware Tools ......................................................................................................................126
13.0 DC and AC Characteristics ........................................................................................................127
13.1 Absolute Maximum Ratings ..................................................................................................127
13.2 DC Characteristics .................................................................................................................129
13.3 AC Characteristics .................................................................................................................138
14.0 Packaging Information ..............................................................................................................143
14.1 Thermal Impedances per Package .......................................................................................148
15.0 Ordering Guide ..........................................................................................................................149
16.0 Document Revision History .......................................................................................................150

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

List of Tables

Table 1: Device Family Key Features......................................................................................................... 14

Table 2: Pin-out 8 Pin ................................................................................................................................. 15
Table 3: Pin-out 20 Pin ............................................................................................................................... 15
Table 4: Pin-out 28 Pin ............................................................................................................................... 16
Table 5: Pin-out 44 Pin ............................................................................................................................... 16
Table 6: Pin-out 48 Pin ............................................................................................................................... 17
Table 7: CPU Registers and Mnemonics ................................................................................................... 19
Table 8: Flags Register .............................................................................................................................. 20
Table 9: Accumulator Register (CPU_A).................................................................................................... 20
Table 10: Index Register (CPU_X) ............................................................................................................. 21
Table 11: Stack Pointer Register (CPU_SP) ..............................................................................................21
Table 12: Program Counter Register (CPU_PC)........................................................................................ 21
Table 13: Source Immediate ...................................................................................................................... 21
Table 14: Source Direct.............................................................................................................................. 22
Table 15: Source Indexed .......................................................................................................................... 22
Table 16: Destination Direct ....................................................................................................................... 22
Table 17: Destination Indexed.................................................................................................................... 23
Table 18: Destination Direct Immediate ..................................................................................................... 23
Table 19: Destination Indexed Immediate .................................................................................................. 23
Table 20: Destination Direct Direct............................................................................................................. 24
Table 21: Source Indirect Post Increment .................................................................................................. 24
Table 22: Destination Indirect Post Increment............................................................................................ 24
Table 23: Instruction Set Summary (Sorted by Mnemonic)........................................................................ 25
Table 24: Flash Program Memory Map ...................................................................................................... 26
Table 25: RAM Data Memory Map ............................................................................................................. 26
Table 26: Bank 0 ........................................................................................................................................ 27
Table 27: Bank 1 ........................................................................................................................................ 28
Table 28: Port Data Registers .................................................................................................................... 31
Table 29: Port Interrupt Enable Registers .................................................................................................. 31
Table 30: Port Global Select Registers ...................................................................................................... 32
Table 31: Port Drive Mode 0 Registers ...................................................................................................... 32
Table 32: Port Drive Mode 1 Registers ...................................................................................................... 33
Table 33: Port Interrupt Control 0 Registers............................................................................................... 33
Table 34: Port Interrupt Control 1 Registers............................................................................................... 34
Table 35: Internal Main Oscillator Trim Register ........................................................................................ 35
Table 36: Internal Low Speed Oscillator Trim Register .............................................................................. 36
Table 37: External Crystal Oscillator Trim Register.................................................................................... 37
Table 38: Typical Package Capacitances .................................................................................................. 37
Table 39: System Clocking Signals and Definitions ................................................................................... 38
Table 40: Oscillator Control 0 Register....................................................................................................... 40
Table 41: Oscillator Control 1 Register....................................................................................................... 40
Table 42: 24V1/24V2 Frequency Selection ................................................................................................ 41
Table 43: Interrupt Vector Table................................................................................................................. 44
Table 44: General Interrupt Mask Register ................................................................................................ 45
Table 45: Digital PSoC Block Interrupt Mask Register ............................................................................... 46

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 46: Interrupt Vector Register ............................................................................................................ 46

Table 47: Digital Basic Type A/ Communications Type A Block xx Function Register............................... 50
Table 48: Digital Basic Type A / Communications Type A Block xx Input Register ................................... 51
Table 49: Digital Function Data Input Definitions ....................................................................................... 52
Table 50: Digital Basic Type A / Communications Type A Block xx Output Register................................. 53
Table 51: Digital Function Outputs ............................................................................................................. 54
Table 52: Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2........................... 54
Table 53: R/W Variations per User Module Selection ................................................................................ 55
Table 54: Digital Basic Type A / Communications Type A Block xx Control Register 0 ............................. 55
Table 55: Digital Basic Type A/Communications Type A Block xx Control Register 0... ............................ 56
Table 56: Digital Communications Type A Block xx Control Register 0... .................................................. 57
Table 57: Digital Communications Type A Block xx Control Register 0... .................................................. 58
Table 58: Digital Communications Type A Block xx Control Register 0... .................................................. 59
Table 59: Global Input Assignments...........................................................................................................60
Table 60: Global Output Assignments........................................................................................................ 60
Table 61: Analog System Clocking Signals................................................................................................ 72
Table 62: AGND, RefHI, RefLO Operating Parameters ............................................................................. 74
Table 63: Analog Reference Control Register............................................................................................ 75
Table 64: Analog Column Clock Select Register........................................................................................ 76
Table 65: Analog Clock Select Register ..................................................................................................... 77
Table 66: Analog Continuous Time Block xx Control 0 Register................................................................ 82
Table 67: Analog Continuous Time Block xx Control 1 Register................................................................ 83
Table 68: Analog Continuous Time Type A Block xx Control 2 Register ................................................... 84
Table 69: Analog Switch Cap Type A Block xx Control 0 Register ............................................................ 88
Table 70: Analog Switch Cap Type A Block xx Control 1 Register ............................................................ 90
Table 71: Analog Switch Cap Type A Block xx Control 2 Register ............................................................ 92
Table 72: Analog Switch Cap Type A Block xx Control 3 Register ............................................................ 93
Table 73: Analog Switch Cap Type B Block xx Control 0 Register ............................................................ 95
Table 74: Analog Switch Cap Type B Block xx Control 1 Register ............................................................ 97
Table 75: Analog Switch Cap Type B Block xx Control 2 Register ............................................................ 99
Table 76: Analog Switch Cap Type B Block xx Control 3 Register ..........................................................100
Table 77: Analog Comparator Control Register .......................................................................................101
Table 78: Analog Frequency Relationships..............................................................................................102
Table 79: Analog Synchronization Control Register.................................................................................102
Table 80: Analog Input Select Register ....................................................................................................104
Table 81: Analog Output Buffer Control Register .....................................................................................106
Table 82: Analog Modulator Control Register ..........................................................................................107
Table 83: Multiply Input X Register...........................................................................................................110
Table 84: Multiply Input Y Register...........................................................................................................110
Table 85: Multiply Result High Register ...................................................................................................111
Table 86: Multiply Result Low Register ....................................................................................................111
Table 87: Accumulator Result 1 / Multiply/Accumulator Input X Register ................................................111
Table 88: Accumulator Result 0 / Multiply/Accumulator Input Y Register ................................................111
Table 89: Accumulator Result 3 / Multiply/Accumulator Clear 0 Register ................................................112
Table 90: Accumulator Result 2 / Multiply/Accumulator Clear 1 Register ................................................112
Table 91: Decimator/Incremental Control Register ..................................................................................113
Table 92: Decimator Data High Register..................................................................................................113
Table 93: Decimator Data Low Register...................................................................................................113
Table 94: Processor Status and Control Register ....................................................................................114
Table 95: Reset WDT Register.................................................................................................................116
Table 96: Voltage Monitor Control Register .............................................................................................118
Table 97: Bandgap Trim Register.............................................................................................................120
Table 98: CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM) ..........................121
Table 99: Table Read for Supervisory Call Functions ..............................................................................122

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Table 100: Flash Program Memory Protection.........................................................................................122

Table 101: Programmer Requirements ....................................................................................................122
Table 102: Absolute Maximum Ratings....................................................................................................127
Table 103: Temperature Specifications....................................................................................................128
Table 104: DC Operating Specifications ..................................................................................................129
Table 105: 5V DC Operational Amplifier Specifications ...........................................................................130
Table 106: 3.3V DC Operational Amplifier Specifications ........................................................................131
Table 107: DC Analog Input Pin with Multiplexer Specifications ..............................................................132
Table 108: DC Analog Input Pin to SC Block Specifications ....................................................................132
Table 109: 5V DC Analog Output Buffer Specifications ...........................................................................132
Table 110: 3.3V DC Analog Output Buffer Specifications ........................................................................133
Table 111: DC Switch Mode Pump Specifications ...................................................................................134
Table 112: 5V DC Analog Reference Specifications ................................................................................135
Table 113: 3.3V DC Analog Reference Specifications .............................................................................136
Table 114: DC Analog PSoC Block Specifications...................................................................................136
Table 115: DC Programming Specifications.............................................................................................137
Table 116: AC Operating Specifications...................................................................................................138
Table 117: 5V AC Operational Amplifier Specifications ...........................................................................139
Table 118: 3.3V AC Operational Amplifier Specifications ........................................................................140
Table 119: 5V AC Analog Output Buffer Specifications ...........................................................................141
Table 120: 3.3V AC Analog Output Buffer Specifications ........................................................................142
Table 121: AC Programming Specifications.............................................................................................142
Table 122: Thermal Impedances..............................................................................................................148
Table 123: Ordering Guide .......................................................................................................................149
Table 124: Document Revision History ....................................................................................................150

August 18, 2003

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

List of Figures

Figure 1: Block Diagram ............................................................................................................................ 13

Figure 2: CY8C25122 ................................................................................................................................ 15
Figure 3: CY8C26233 ................................................................................................................................ 15
Figure 4: 26443 PDIP/SOIC/SSOP ...........................................................................................................16
Figure 5: 26643 TQFP ............................................................................................................................... 17
Figure 6: 26643 PDIP/SSOP ..................................................................................................................... 18
Figure 7: General Purpose I/O Pins .......................................................................................................... 30
Figure 8: External Crystal Oscillator Connections ..................................................................................... 37
Figure 9: PSoC MCU Clock Tree of Signals ..............................................................................................39
Figure 10: Interrupts Overview .................................................................................................................. 43
Figure 11: GPIO Interrupt Enable Diagram ............................................................................................... 47
Figure 12: Digital Basic and Digital Communications PSoC Blocks .......................................................... 49
Figure 13: Polynomial LFSR ...................................................................................................................... 65
Figure 14: Polynomial PRS ....................................................................................................................... 65
Figure 15: SPI Waveforms ........................................................................................................................ 68
Figure 16: Array of Analog PSoC Blocks ................................................................................................... 72
Figure 17: Analog Reference Control Schematic ...................................................................................... 73
Figure 18: NMux Connections ................................................................................................................... 78
Figure 19: PMux Connections ................................................................................................................... 79
Figure 20: RBotMux Connections .............................................................................................................. 79
Figure 21: Analog Continuous Time PSoC Blocks .................................................................................... 81
Figure 22: Analog Switch Cap Type A PSoC Blocks ................................................................................. 86
Figure 23: AMux Connections ................................................................................................................... 87
Figure 24: CMux Connections ................................................................................................................... 87
Figure 25: BMuxSCA/SCB Connections ................................................................................................... 88
Figure 26: Analog Switch Cap Type B PSoC Blocks ................................................................................. 95
Figure 27: Analog Input Muxing ...............................................................................................................103
Figure 28: Analog Output Buffers ............................................................................................................105
Figure 29: Multiply/Accumulate Block Diagram .......................................................................................110
Figure 30: Decimator Coefficients ...........................................................................................................112
Figure 31: Execution Reset .....................................................................................................................115
Figure 32: Three Sleep States .................................................................................................................117
Figure 33: Switch Mode Pump ................................................................................................................119
Figure 34: Programming Wave Forms ....................................................................................................124
Figure 35: PSoC Designer Functional Flow ............................................................................................125
Figure 36: CY8C25xxx/CY8C26xxx Voltage Frequency Graph ..............................................................127
Figure 37: 44-Lead Thin Plastic Quad Flat Pack A44 .............................................................................143
Figure 38: 20-Pin Shrunk Small Outline Package O20 ...........................................................................144
Figure 39: 28-Lead (210-Mil) Shrunk Small Outline Package O28 .........................................................145
Figure 40: 48-Lead Shrunk Small Outline Package O48 .........................................................................145
Figure 41: 20-Lead (300-Mil) Molded DIP P5 ..........................................................................................146
Figure 42: 28-Lead (300-Mil) Molded DIP P21 ........................................................................................146
Figure 43: 48-Lead (600-Mil) Molded DIP P25 ........................................................................................146
Figure 44: 20-Lead (300-Mil) Molded SOIC S5 .......................................................................................147
Figure 45: 28-Lead (300-Mil) Molded SOIC S21 .....................................................................................147

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11

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Figure 46: 8-Lead (300-Mil) Molded DIP .................................................................................................148

12

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P5

P4

P3

P2

P1

P0

I/O Ports

Analog Input
Muxing

Analog Output
Drivers

A
C
A
0
0

A
C
A
0
1

A
C
A
0
2

A
C
A
0
3

A
S
A
1
0

A
S
B
1
1

A
S
A
1
2

A
S
B
1
3

A
S
B
2
0

A
S
A
2
1

A
S
B
2
2

A
S
A
2
3

Global I/O
Programmable Interconnect

Clocks to
Analog

Comparator
Outputs

D
B
A
0
0

Array of Analog PSoC Blocks

D
B
A
0
1

D
B
A
0
2

D
B
A
0
3

D
C
A
0
4

D
C
A
0
5

D
C
A
0
6

D
C
A
0
7

Array of Digital PSoC Blocks

Flash Program
Memory

Oscillator
and PLL
MAC
Multiply
Accumulate

SRAM
Memory

M8C CPU
Core

Internal System Bus

Decimator

Watchdog/
Sleep Timer

LVD/POR

Interrupt
Controller

Figure 1: Block Diagram

August 18, 2003

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13

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

1.0

Functional Overview

The CPU heart of this next generation family of microcontrollers is a high performance, 8-bit, M8C Harvard
architecture microprocessor. Separate program and
memory busses allow for faster overall throughput. Processor clock speeds to 24 MHz are available. The processor may also be run at lower clock speeds for powersensitive applications. A rich instruction set allows for
efficient low-level language support.
All devices in this family include both analog and digital
configurable peripherals (PSoC blocks). These blocks
enable the user to define unique functions during configuration of the device. Included are twelve analog PSoC
blocks and eight digital PSoC blocks. Potential applications for the digital PSoC blocks are timers, counters,
UARTs, CRC generators, PWMs, and other functions.
The analog PSoC blocks can be used for SAR ADCs,
Multi-slope ADCs, programmable gain amplifiers, programmable filters, DACs, and other functions. Higher
order User Modules such as modems, complex motor
controllers, and complete sensor signal chains can be
created from these building blocks. This allows for an
unprecedented level of flexibility and integration in microcontroller-based systems.
A Multiplier/Accumulator (MAC) is available on all
devices in this family. The MAC is implemented on this
device as a peripheral that is mapped into the register
space. When an instruction writes to the MAC input registers, the result of an 8x8 multiply and a 32-bit accumulate are available to be read from the output registers on
the next instruction cycle.
The number of general purpose I/Os available in this
family of parts range from 6 to 44. Each of these I/O pins
has a variety of programmable options. In the output

1.1
Table 1:

Multiple oscillator options are available for use in clocking the CPU, analog PSoC blocks and digital PSoC
blocks. These options include an internal main oscillator
running at 48/24 MHz, an external crystal oscillator for
use with a 32.768 kHz watch crystal, and an internal lowspeed oscillator for use in clocking the PSoC blocks and
the Watchdog/Sleep timer. User selectable clock divisors
allow for optimizing code execution speed and power
trade-offs.
The different device types in this family provide various
amounts of code and data memory. The code space
ranges in size from 4K to 16K bytes of user programmable Flash memory. This memory can be programmed
serially in either a programming Pod or on the user
board. The endurance on the Flash memory is 50,000
erase/write cycles. The data space is 256 bytes of user
SRAM.
A powerful and flexible protection model secures the
users sensitive information. This model allows the user
to selectively lock blocks of memory for read and write
protection. This allows partial code updates without
exposing proprietary information.
Devices in this family range from 8 pins through 48 pins
in PDIP, SOIC and SSOP packages.

Key Features
Device Family Key Features

Operating Frequency
Operating Voltage
Program Memory (KBytes)
Data Memory (Bytes)
Digital PSoC Blocks
Analog PSoC Blocks
I/O Pins
External Switch Mode Pump
Available Packages

14

mode, the user can select the drive strength desired.

Any pin can serve as an interrupt source, and can be
selected to trigger on positive edges, negative edges, or
any change. Digital signal sources can be routed directly
from a pin to the digital PSoC blocks. Some pins have
additional capability to route analog signals to the analog
PSoC blocks.

CY8C25122
93.7kHz - 24MHz
3.0 - 5.25V
4
256
8
12
6
No
8 PDIP

CY8C26233
93.7kHz - 24MHz
3.0 - 5.25V
8
256
8
12
16
Yes
20 PDIP
20 SOIC
20 SSOP

CY8C26443
93.7kHz - 24MHz
3.0 - 5.25V
16
256
8
12
24
Yes
28 PDIP
28 SOIC
28 SSOP

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

CY8C26643
93.7kHz - 24MHz
3.0 - 5.25V
16
256
8
12
40/44
Yes
48 PDIP
48 SSOP
44 TQFP

August 18, 2003

Functional Overview

1.2

Pin-out Descriptions

Table 2:
Name

Pin-out 8 Pin
I/O

Pin

Pin-out 20 Pin

Table 3:
Description

Name

I/O

Pin

Description

I/O

1 Port 0[7] (Analog Input)

P0[7]

I/O

1 Port 0[7] (Analog Input)

P0[5]

I/O

2 Port 0[5] (Analog Input/Output)

P0[5]

I/O

2 Port 0[5] (Analog Input/Output)

P1[1]

I/O

3 Port 1[1] / XtalIn / SCLK

P0[3]

I/O

3 Port 0[3] (Analog Input/Output)

Vss

Power

4 Ground

P0[1]

I/O

4 Port 0[1] (Analog Input)

P1[0]

I/O

5 Port 1[0] / XtalOut / SDATA

SMP

5 Switch Mode Pump

P0[2]

I/O

6 Port 0[2] (Analog Input/Output)

P1[7]

I/O

6 Port 1[7]

P0[4]

I/O

7 Port 0[4] (Analog Input/Output)

P1[5]

I/O

7 Port 1[5]

Vcc

Power

8 Supply Voltage

P1[3]

I/O

8 Port 1[3]

P1[1]

I/O

9 Port 1[1] / XtalIn / SCLK

Vss

Power

P1[0]

I/O

11 Port 1[0] / XtalOut / SDATA

P1[2]

I/O

12 Port 1[2]

P1[4]

I/O

13 Port 1[4]

P1[6]

I/O

14 Port 1[6]

P0[7]
P0[5]
XtalIn/SCLK/P1[1]

Vss

1
2
3
4

CY8C25122

P0[7]

8
7
6
5

Vcc
P0[4]
P0[2]

P1[0]/XtalOut/SDATA

Figure 2: CY8C25122

10 Ground

XRES I

15 External Reset

P0[0]

I/O

16 Port 0[0] (Analog Input)

P0[2]

I/O

17 Port 0[2] (Analog Input/Output)

P0[4]

I/O

18 Port 0[4] (Analog Input/Output)

P0[6]

I/O

19 Port 0[6] (Analog Input)

Vcc

Power

20 Supply Voltage

XtalIn/SCLK/P1[1]

Vss

1
2
3
4
5
6
7
8
9
10

CY8C26233 PDIP/SOIC/SSOP

P0[7]
P0[5]
P0[3]
P0[1]
SMP
P1[7]
P1[5]
P1[3]

20
19
18
17
16
15
14
13
12
11

Vcc
P0[6]
P0[4]
P0[2]
P0[0]
XRES
P1[6]
P1[4]
P1[2]
P1[0]/XtalOut/SDATA

Figure 3: CY8C26233

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

15

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 4:

Pin-out 28 Pin

Name
P0[7]

I/O

Pin

Description

1 Port 0[7] (Analog Input)

P0[5]

I/O

Port 0[5] (Analog Input/ Out2

put)

P0[3]

I/O

P0[1]

I/O

4 Port 0[1] (Analog Input)

P2[7]

I/O

5 Port 2[7]

P2[5]

I/O

6 Port 2[5]

P2[3]

I/O

Port 2[3] (Non-Multiplexed

Analog Input)

P2[1]

I/O

Port 2[1] (Non-Multiplexed

Analog Input)

SMP

9 Switch Mode Pump

P1[7]

I/O

10 Port 1[7]

P1[5]

I/O

11 Port 1[5]

P1[3]

I/O

12 Port 1[3]

P1[1]

I/O

13 Port 1[1] / XtalIn / SCLK

Vss

Power

14 Ground

P1[0]

I/O

15 Port 1[0] / XtalOut / SDATA

P1[2]

I/O

16 Port 1[2]

P1[4]

I/O

P1[6]

P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]

Port 0[3] (Analog Input/ Output)

1
2
3
4
5
6
7
8
9
10
11
12
13
14

XtalIn/SCLK/P1[1]

Vss

26443 PDIP/SOIC/SSOP

I/O

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Vcc
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]/External V ref
P2[4]/External AGND
P2[2]
P2[0]
Xres
P1[6]
P1[4]
P1[2]
P1[0]/XtalOut/SDATA

Figure 4: 26443 PDIP/SOIC/SSOP

Pin-out 44 Pin

Table 5:
Name

I/O

Pin

Description

P2[5]

I/O

1 Port 2[5]

P2[3]

I/O

Port 2[3] (Non-Multiplexed

Analog Input)

P2[1]

I/O

Port 2[1] (Non-Multiplexed

Analog Input)

17 Port 1[4]

P3[7]

I/O

4 Port 3[7]

I/O

18 Port 1[6]

P3[5]

I/O

5 Port 3[5]

XRES

19 External Reset

P3[3]

I/O

6 Port 3[3]

P2[0]

I/O

20

Port 2[0] (Non-Multiplexed

Analog Input)

P3[1]

I/O

7 Port 3[1]

SMP

8 Switch Mode Pump

P2[2]

I/O

Port 2[2] (Non-Multiplexed

21
Analog Input)

P4[7]

I/O

9 Port 4[7]

P2[4]

I/O

22 Port 2[4] / External AGNDIn

P4[5]

I/O

10 Port 4[5]

P2[6]

I/O

23 Port 2[6] / External VREFIn

P4[3]

I/O

11 Port 4[3]

P0[0]

I/O

24 Port 0[0] (Analog Input)

P4[1]

I/O

12 Port 4[1]

I/O

13 Port 1[7]

I/O

25

Port 0[2] (Analog Input/Output)

P1[7]

P0[2]

P1[5]

I/O

14 Port 1[5]

P0[4]

I/O

26

Port 0[4] (Analog Input/Output)

P1[3]

I/O

15 Port 1[3]

P1[1]

I/O

16 Port 1[1] / XtalIn / SCLK

P0[6]

I/O

27 Port 0[6] (Analog Input)

Vss

Power

17 Ground

Vcc

Power

28 Supply Voltage

P1[0]

I/O

18 Port 1[0] / XtalOut / SDATA

P1[2]

I/O

19 Port 1[2]

P1[4]

I/O

20 Port 1[4]

P1[6]

I/O

21 Port 1[6]

P4[0]

I/O

22 Port 4[0]

P4[2]

I/O

23 Port 4[2]

P4[4]

I/O

24 Port 4[4]

16

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Functional Overview

Pin-out 44 Pin, continued

Table 5:
P4[6]

I/O

25 Port 4[6]

XRES

26 External Reset

P3[0]

I/O

27 Port 3[0]

P3[2]

I/O

28 Port 3[2]

P3[4]

I/O

29 Port 3[4]

P3[6]

I/O

30 Port 3[6]

P2[0]

I/O

31

P2[2]

Pin-out 48 Pin

Table 6:
Name

I/O

Pin

Description

1 Port 0[7] (Analog Input)

P0[5]

I/O

Port 0[5] (Analog Input/Output)

P0[3]

I/O

Port 0[3] (Analog Input/Output)

Port 2[0] (Non-Multiplexed

Analog Input)

P0[1]

I/O

4 Port 0[1] (Analog Input)

P2[7]

I/O

5 Port 2[7]

I/O

Port 2[2] (Non-Multiplexed

32
Analog Input)

P2[5]

I/O

6 Port 2[5]

P2[4]

I/O

33 Port 2[4] / External AGNDIn

P2[3]

I/O

Port 2[3] (Non-Multiplexed

Analog Input)

P2[6]

I/O

34 Port 2[6] / External VREFIn

P0[0]

I/O

35 Port 0[0] (Analog Input)

P2[1]

I/O

Port 2[1] (Non-Multiplexed

Analog Input)

P0[2]

I/O

36 Port 0[2] (Analog Input/Output)

P3[7]

I/O

9 Port 3[7]

P0[4]

I/O

37 Port 0[4] (Analog Input/Output)

P3[5]

I/O

10 Port 3[5]

P0[6]

I/O

38 Port 0[6] (Analog Input)

P3[3]

I/O

11 Port 3[3]

Vcc

Power

39 Supply Voltage

P3[1]

I/O

12 Port 3[1]

P0[7]

I/O

40 Port 0[7] (Analog Input)

SMP

13 Switch Mode Pump

P0[5]

I/O

41 Port 0[5] (Analog Input/Output)

P4[7]

I/O

14 Port 4[7]

P0[3]

I/O

42 Port 0[3] (Analog Input/Output)

P4[5]

I/O

15 Port 4[5]

P0[1]

I/O

43 Port 0[1] (Analog Input)

P4[3]

I/O

16 Port 4[3]

P2[7]

I/O

44 Port 2[7]

P4[1]

I/O

17 Port 4[1]

P5[3]

I/O

18 Port 5[3]

P5[1]

I/O

19 Port 5[1]

P1[7]

I/O

20 Port 1[7]

P1[5]

I/O

21 Port 1[5]

P1[3]

I/O

22 Port 1[3]

P1[1]

I/O

23 Port 1[1] / XtalIn / SCLK

Vss

Power

24 Ground

P1[0]

I/O

25 Port 1[0] / XtalOut / SDATA

P1[2]

I/O

26 Port 1[2]

P1[4]

I/O

27 Port 1[4]

P1[6]

I/O

28 Port 1[6]

1 44 43 42 41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
9
10
11
26643 TQFP

P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]

P2[6]/ExVrefIn

I/O

P2[7]
P0[1]
P0[3]
P0[5]
P0[7]
Vcc
P0[6]
P0[4]
P0[2]
P0[0]

P0[7]

33
32
31
30
29
28
27
26
25
24
23

P2[4]/Ex AGNDIn

P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
Xres
P4[6]
P4[4]
P4[2]

P4[1]
P1[7]
P1[5]
P1[3]
XtalIn/SCLK/P1[1]
Vss
XtalOut/SDATA/P1[0]
P1[2]
P1[4]
P1[6]
P4[0]

12 13 14 15 16 17 18 19 20 21 22

Figure 5: 26643 TQFP

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

17

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Pin-out 48 Pin, continued

Table 6:
P5[0]

I/O

29 Port 5[0]

P5[2]

I/O

30 Port 5[2]

P4[0]

I/O

31 Port 4[0]

P4[2]

I/O

32 Port 4[2]

P4[4]

I/O

33 Port 4[4]

P4[6]

I/O

34 Port 4[6]

XRES

35 External Reset

P3[0]

I/O

36 Port 3[0]

P3[2]

I/O

37 Port 3[2]

P3[4]

I/O

38 Port 3[4]

P3[6]

I/O

39 Port 3[6]

P2[0]

I/O

40

Port 2[0] (Non-Multiplexed

Analog Input)

P2[2]

I/O

41

Port 2[2] (Non-Multiplexed

Analog Input)

P2[4]

I/O

42 Port 2[4] / External AGNDIn

P2[6]

I/O

43 Port 2[6] / External VREFIn

P0[0]

I/O

44 Port 0[0] (Analog Input)

P0[2]

I/O

45

Port 0[2] (Analog Input/Output)

P0[4]

I/O

46

Port 0[4] (Analog Input/Output)

P0[6]

I/O

47 Port 0[6] (Analog Input)

Vcc

Power

48 Supply Voltage

XtalIn/SCLK/P1[1]

Vss

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

26643 PDIP/SSOP

P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

Vcc
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]/External V ref IN
P2[4] /External AGNDIN
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
Xres
P4[6]
P4[4]
P4[2]
P4[0]
P5[2]
P5[0]
P1[6]
P1[4]
P1[2]
P1[0]/XtalOut/SDATA

Figure 6: 26643 PDIP/SSOP

18

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

CPU Architecture

2.0

CPU Architecture

2.1

Introduction

This family of microcontrollers is based on a high perfor-

RET instructions, which manage the software stack. It

mance, 8-bit, Harvard architecture microprocessor. Five

can also be affected by the SWAP and ADD instructions.

registers control the primary operation of the CPU core.

These registers are affected by various instructions, but
are not directly accessible through the register space by
the user. For more details on addressing with the register
space, see section 4.0.
Table 7:

CPU Registers and Mnemonics

Register

Mnemonic

The Flag Register (CPU_F) has three status bits: Zero

Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3].
The Global Interrupt Enable bit [0] is used to globally
enable or disable interrupts. An extended I/O space
address, bit [4], is used to determine which bank of the
register space is in use. The user cannot manipulate the
Supervisory State status bit [3]. The flags are affected by

Flags

CPU_F

arithmetic, logic, and shift operations. The manner in

Program Counter

CPU_PC

which each flag is changed is dependent upon the

Accumulator

CPU_A

instruction being executed (i.e., AND, OR, XOR... See

Stack Pointer

CPU_SP

Table 23 on page 25).

Index

CPU_X

The 16 bit Program Counter Register (CPU_PC) allows

for direct addressing of the full 16 Kbytes of program
memory space available in the largest members of this
family. This forms one contiguous program space, and
no paging is required.
The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that
specify any of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is
used in the indexed addressing modes. Typically, this is
used to address a block of data within the data memory
space.
The Stack Pointer Register (CPU_SP) holds the address
of the current top-of-stack in the data memory space. It is
affected by the PUSH, POP, LCALL, CALL, RETI, and

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

19

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

2.2

CPU Registers

2.2.1

Flags Register

The Flags Register can only be set or reset with logical instruction.
Table 8:

Flags Register

Bit #

POR

Read/
Write

--

--

--

RW

RW

RW

RW

Bit Name

Reserved

Reserved

Reserved

XIO

Super

Carry

Zero

Global IE

Bit 7: Reserved
Bit 6: Reserved
Bit 5: Reserved
Bit 4: XIO Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed
directly by the user and is not displayed in the ICE debugger.)
0 = User Code
1 = Supervisor Code
Bit 2: Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation
0 = No Carry
1 = Carry
Bit 1: Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0: Global IE Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled

2.2.2

Accumulator Register

Table 9:

Accumulator Register (CPU_A)

Bit #
POR
Read/Write
Bit Name

7
0
System1
Data [7]

6
0

5
0

System1
Data [6]

System1
Data [5]

4
0
System1
Data [4]

3
0
System1
Data [3]

2
0
System1
Data [2]

1
0

0
0

System1
Data [1]

System1
Data [0]

Bit [7:0]: Data [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode
1.

20

System - not directly accessible by the user

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

CPU Architecture

2.2.3

Index Register

Table 10:

Index Register (CPU_X)

Bit #
POR
Read/
Write
Bit Name

7
0

6
0

5
0

4
0

3
0

2
0

1
0

0
0

System1

System1

System1

System1

System1

System1

System1

System1

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode
1.

System - not directly accessible by the user

2.2.4

Stack Pointer Register

Table 11:

Stack Pointer Register (CPU_SP)

Bit #
POR
Read/
Write
Bit Name

7
0

6
0

5
0

4
0

3
0

2
0

1
0

0
0

System1

System1

System1

System1

System1

System1

System1

System1

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] 8-bit data value holds a pointer to the current top-of-stack
1.

System - not directly accessible by the user

2.2.5

Program Counter Register

Table 12:
Bit #
POR
Read/
Write
Bit
Name

Program Counter Register (CPU_PC)

15
0

14
0

13
0

12
0

11
0

10
0

9
0

8
0

7
0

6
0

5
0

4
0

3
0

2
0

1
0

0
0

Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
[15] [14] [13] [12] [11] [10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]

Data
[0]

Bit [15:0]: Data [15:0] 16-bit data value is the low-order/high-order byte of the Program Counter
1.

System - not directly accessible by the user

2.3

Addressing Modes

2.3.1

Source Immediate

require two sources. Instructions using this addressing

The result of an instruction using this addressing mode is

placed in the A register, the F register, the SP register, or
the X register, which is specified as part of the instruction
opcode. Operand 1 is an immediate value that serves as

mode are two bytes in length.

Table 13:

Source Immediate

Opcode
Instruction

Operand 1
Immediate Value

a source for the instruction. Arithmetic instructions

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

21

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

added to the X register forming an address that points to

Examples:

ADD

MOV

AND

2.3.2

A,

X,

F,

;In this case, the immediate

;value of 7 is added with the
;Accumulator, and the result
;is placed in the
;Accumulator.

;In this case, the immediate

;value of 8 is moved to the X
;register.

;In this case, the immediate

;value of 9 is logically
;ANDed with the F register
;and the result is placed in
;the F register.

a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic
instructions require two sources, the second source is
the A register or X register specified in the opcode.
Instructions using this addressing mode are two bytes.

Table 15:

Source Indexed

Opcode
Instruction

Operand 1
Source Index

Examples:

[X+7]

;In this case, the

;value in the memory
;location at address
;X + 7 is added with
;the Accumulator, and
;the result is placed
;in the Accumulator.

REG[X+8]

;In this case, the

;value in the
;register space at
;address X + 8 is
;moved to the X
;register.

Source Direct

The result of an instruction using this addressing mode is

ADD

A,

placed in either the A register or the X register, which is

specified as part of the instruction opcode. Operand 1 is
an address that points to a location in either the RAM
memory space or the register space that is the source for
the instruction. Arithmetic instructions require two

MOV

X,

sources, the second source is the A register or X register

specified in the opcode. Instructions using this addressing mode are two bytes in length.

Table 14:

Destination Direct

Operand 1

The result of an instruction using this addressing mode is

Source Address

placed within either the RAM memory space or the regis-

Opcode
Instruction

2.3.4

Source Direct

ter space. Operand 1 is an address that points to the

location of the result. The source for the instruction is

Examples:

either the A register or the X register, which is specified

ADD

MOV

2.3.3

A,

X,

[7]

;In this case, the

;value in the RAM
;memory location at
;address 7 is added
;with the Accumulator,
;and the result is
;placed in the
;Accumulator.

;In this case, the

;value in the register
REG[8] ;space at address 8 is
;moved to the X
;register.

as part of the instruction opcode. Arithmetic instructions

require two sources, the second source is the location
specified by Operand 1. Instructions using this addressing mode are two bytes in length.

Table 16:

Destination Direct

Opcode
Instruction

Operand 1
Destination Address

Source Indexed

The result of an instruction using this addressing mode is

placed in either the A register or the X register, which is
specified as part of the instruction opcode. Operand 1 is

22

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

CPU Architecture

source for the instruction is Operand 2, which is an

Examples:

ADD

MOV

2.3.5

[7],

REG[8], A

;In this case, the

;value in the memory
;location at address
;7 is added with the
;Accumulator, and the
;result is placed in
;the memory location
;at address 7. The
;Accumulator is
;unchanged.
;In this case, the
;Accumulator is moved
;to the register
;space location at
;address 8. The
;Accumulator is
;unchanged.

immediate value. Arithmetic instructions require two

sources, the second source is the location specified by
Operand 1. Instructions using this addressing mode are
three bytes in length.

Table 18:

Destination Direct Immediate

Opcode
Instruction

Operand 1

Operand 2

Destination Address

Immediate Value

Examples:

ADD [7],

;In this case, value in

;the memory location at
;address 7 is added to
;the immediate value of
;5, and the result is
;placed in the memory
;location at address 7.

Destination Indexed

The result of an instruction using this addressing mode is

placed within either the RAM memory space or the regis-

;In this case, the

;immediate value of 6 is
;moved into the register
;space location at
;address 8.

MOV REG[8], 6

ter space. Operand 1 is added to the X register forming

the address that points to the location of the result. The
source for the instruction is the A register. Arithmetic
instructions require two sources, the second source is
the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are two
bytes in length.

Table 17:

Destination Indexed

Opcode
Instruction

Operand 1

2.3.7

Destination Indexed Immediate

The result of an instruction using this addressing mode is

placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form
the address of the result. The source for the instruction is
Operand 2, which is an immediate value. Arithmetic
instructions require two sources, the second source is

Destination Index

the location specified by Operand 1 added with the X

register. Instructions using this addressing mode are
three bytes in length.

Example:

ADD [X+7],

2.3.6

;In this case, the value

;in the memory location
;at address X+7 is added
;with the Accumulator,
;and the result is placed
;in the memory location
;at address x+7. The
;Accumulator is
;unchanged.

Table 19:
Opcode
Instruction

Destination Indexed Immediate

Operand 1
Destination Index

Operand 2
Immediate Value

Destination Direct Immediate

The result of an instruction using this addressing mode is

placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

23

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Language User Guide for further details on MVI instruc-

Examples:

ADD

MOV

2.3.8

[X+7],

REG[X+8], 6

;In this case, the

;value in the memory
;location at address
;X+7 is added with
;the immediate value
;of 5, and the result
;is placed in the
;memory location at
;address X+7.
;In this case, the
;immediate value of 6
;is moved into the
;location in the
;register space at
;address X+8.

tion.

Table 21:

Source Indirect Post Increment

Opcode
Instruction

Operand 1
Source Address Address

Example:

MVI

A,

[8]

Destination Direct Direct

;In this case, the value

;in the memory location at
;address 8 is an indirect
;address. The memory
;location pointed to by
;the indirect address is
;moved into the
;Accumulator. The
;indirect address is then
;incremented.

The result of an instruction using this addressing mode is

placed within the RAM memory. Operand 1 is the
address of the result. Operand 2 is an address that
points to a location in the RAM memory that is the source
for the instruction. This addressing mode is only valid on

2.3.10 Destination Indirect Post Increment

The result of an instruction using this addressing mode is
placed within the memory space. Operand 1 is an

the MOV instruction. The instruction using this address-

address pointing to a location within the memory space,

ing mode is three bytes in length.

which contains an address (the indirect address) for the

Table 20:
Opcode
Instruction

Destination Direct Direct

Operand 1

Operand 2

Destination Address Source Address

2.3.9

incremented as part of the instruction execution. The

source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction.
The instruction using this addressing mode is two bytes

Example:

MOV

destination of the instruction. The indirect address is

in length.

;In this case, the value

;in the memory location at
[7], [8] ;address 8 is moved to the
;memory location at
;address 7.

Source Indirect Post Increment

Table 22:

Destination Indirect Post Increment

Opcode
Instruction

Operand 1
Destination Address Address

Example:

The result of an instruction using this addressing mode is

placed in the Accumulator. Operand 1 is an address
pointing to a location within the memory space, which
contains an address (the indirect address) for the source
of the instruction. The indirect address is incremented as

MVI

[8], A

part of the instruction execution. This addressing mode

is only valid on the MVI instruction. The instruction using
this addressing mode is two bytes in length. See Sec-

;In this case, the

;value in the memory
;location at address 8
;is an indirect
;address. The
;Accumulator is moved
;into the memory
;location pointed to by
;the indirect address.
;The indirect address
;is then incremented.

tion 7. Instruction Set in PSoC Designer: Assembly

24

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

CPU Architecture

2.4

Instruction Set Summary

Table 23:

Instruction Set Summary (Sorted by Mnemonic)

INC [expr]
INC [X+expr]
INDEX
JACC
JC
JMP
JNC
JNZ
JZ
LCALL
LJMP
MOV X, SP
MOV A, expr
MOV A, [expr]
MOV A, [X+expr]
MOV [expr], A
MOV [X+expr], A
MOV [expr], expr
MOV [X+expr], expr
MOV X, expr
MOV X, [expr]
MOV X, [X+expr]
MOV [expr], X
MOV A, X
MOV X, A
MOV A, reg[expr]
MOV A, reg[X+expr]
MOV [expr], [expr]
MOV reg[expr], A
MOV reg[X+expr], A
MOV reg[expr], expr
MOV reg[X+expr], expr
MVI A, [ [expr]++ ]
MVI [ [expr]++ ], A
NOP
OR A, expr
OR A, [expr]
OR A, [X+expr]
OR [expr], A
OR [X+expr], A
OR [expr], expr
OR [X+expr], expr
OR reg[expr], expr
OR reg[X+expr], expr
OR F, expr

C, Z
C, Z
Z

Z
Z
Z

Z
Z
Z

Z
Z
Z
Z
Z
Z
Z
Z
Z
C, Z

20
18
10
08
7E
7F
6A
6B
6C
28
6D
6E
6F
19
1A
1B
1C
1D
1E
1F
00
11
12
13
14
15
16
17
4B
4C
4D
4E
47
48
49
4A
72
31
32
33
34
35
36
37
45
46

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

Instruction Format

Flags

Bytes
Cycles

Flags

Bytes
Cycles

09 4 2 ADC A, expr
C, Z
76 7 2
0A 6 2 ADC A, [expr]
C, Z
77 8 2
0B 7 2 ADC A, [X+expr]
C, Z
Fx 13 2
0C 7 2 ADC [expr], A
C, Z
Ex 7 2
0D 8 2 ADC [X+expr], A
C, Z
Cx 5 2
0E 9 3 ADC [expr], expr
C, Z
8x 5 2
0F 10 3 ADC [X+expr], expr
C, Z
Dx 5 2
01 4 2 ADD A, expr
C, Z
Bx 5 2
02 6 2 ADD A, [expr]
C, Z
Ax 5 2
03 7 2 ADD A, [X+expr]
C, Z
7C 13 3
04 7 2 ADD [expr], A
C, Z
7D 7 3
05 8 2 ADD [X+expr], A
C, Z
4F 4 1
06 9 3 ADD [expr], expr
C, Z
50 4 2
07 10 3 ADD [X+expr], expr
C, Z
51 5 2
38 5 2 ADD SP, expr
52 6 2
21 4 2 AND A, expr
Z
53 5 2
22 6 2 AND A, [expr]
Z
54 6 2
23 7 2 AND A, [X+expr]
Z
55 8 3
24 7 2 AND [expr], A
Z
56 9 3
25 8 2 AND [X+expr], A
Z
57 4 2
26 9 3 AND [expr], expr
Z
58 6 2
27 10 3 AND [X+expr], expr
Z
59 7 2
70 4 2 AND F, expr
C, Z
5A 5 2
41 9 3 AND reg[expr], expr
Z
5B 4 1
42 10 3 AND reg[X+expr], expr
Z
5C 4 1
64 4 1 ASL A
C, Z
5D 6 2
65 7 2 ASL [expr]
C, Z
5E 7 2
66 8 2 ASL [X+expr]
C, Z
5F 10 3
67 4 1 ASR A
C, Z
60 5 2
68 7 2 ASR [expr]
C, Z
61 6 2
69 8 2 ASR [X+expr]
C, Z
62 8 3
9x 11 2 CALL
63 9 3
39 5 2 CMP A, expr
if (A=B) Z=1 3E 10 2
3A 7 2 CMP A, [expr]
if (A<B) C=1 3F 10 2
3B 8 2 CMP A, [X+expr]
40 4 1
3C 8 3 CMP [expr], expr
29 4 2
3D 9 3 CMP [X+expr], expr
2A 6 2
73 4 1 CPL A
Z
2B 7 2
78 4 1 DEC A
C, Z
2C 7 2
79 4 1 DEC X
C, Z
2D 8 2
7A 7 2 DEC [expr]
C, Z
2E 9 3
7B 8 2 DEC [X+expr]
C, Z
2F 10 3
30 9 1 HALT
43 9 3
74 4 1 INC A
C, Z
44 10 3
75 4 1 INC X
C, Z
71 4 2
Note: Interrupt acknowledge to Interrupt Vector table = 13 cycles.

August 18, 2003

Instruction Format

Opcode Hex

Flags

Opcode Hex

Bytes
Cycles

Opcode Hex

Instruction Format

5
5
4
4
10
8
4
7
8
11
4
7
8
4
6
7
7
8
9
10
15
4
6
7
7
8
9
10
5
7
7
5
8
9
9
10
4
4
6
7
7
8
9
10
9
10

1
1
1
1
1
1
1
2
2
1
1
2
2
2
2
2
2
2
3
3
1
2
2
2
2
2
3
3
1
2
2
1
3
3
3
3
2
2
2
2
2
2
3
3
3
3

POP X
POP A
PUSH X
PUSH A
RETI
RET
RLC A
RLC [expr]
RLC [X+expr]
ROMX
RRC A
RRC [expr]
RRC [X+expr]
SBB A, expr
SBB A, [expr]
SBB A, [X+expr]
SBB [expr], A
SBB [X+expr], A
SBB [expr], expr
SBB [X+expr], expr
SSC
SUB A, expr
SUB A, [expr]
SUB A, [X+expr]
SUB [expr], A
SUB [X+expr], A
SUB [expr], expr
SUB [X+expr], expr
SWAP A, X
SWAP A, [expr]
SWAP X, [expr]
SWAP A, SP
TST [expr], expr
TST [X+expr], expr
TST reg[expr], expr
TST reg[X+expr], expr
XOR F, expr
XOR A, expr
XOR A, [expr]
XOR A, [X+expr]
XOR [expr], A
XOR [X+expr], A
XOR [expr], expr
XOR [X+expr], expr
XOR reg[expr], expr
XOR reg[X+expr], expr

C, Z
C, Z
C, Z
C, Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

25

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

3.0

Memory Organization

3.1

Flash Program Memory

Organization

Table 24:

Flash Program Memory Map

Address

Description

3.2

RAM Data Memory Organization

The stack on this device grows from low addresses to

high addresses. The Linker function within PSoC
Designer locates the bottom of the stack after the end of

0x0000

Reset Vector

Global Variables. This allows the stack to grow from just

0x0004

Supply Monitor Interrupt Vector

after the Global Variables until 0xFF. The stack will wrap

0x0008

DBA 00 PSoC Block Interrupt Vector

back to 0x00 on an overflow condition.

0x000C

DBA 01 PSoC Block Interrupt Vector

Table 25:

0x0010

DBA 02 PSoC Block Interrupt Vector

0x0014

DBA 03 PSoC Block Interrupt Vector

0x00

First General Purpose RAM Location

0x0018

DCA 04 PSoC Block Interrupt Vector

0xXX

General Purpose RAM

0x001C

DCA 05 PSoC Block Interrupt Vector

0xXY

General Purpose RAM

0x0020

DCA 06 PSoC Block Interrupt Vector

0xXZ

Last General Purpose RAM Location

0x0024

DCA 07 PSoC Block Interrupt Vector

0xYX

Bottom of Hardware Stack

0x0028

Analog Column 0 Interrupt Vector

0xYY

Stack Grows This Way

0x002C

Analog Column 1 Interrupt Vector

0xFF

Top of Hardware Stack

0x0030

Analog Column 2 Interrupt Vector

0x0034

Analog Column 3 Interrupt Vector

0x0038

GPIO Interrupt Vector

0x003C
0x0040

Address

Description

4.0

Register Organization

Sleep Timer Interrupt Vector

4.1

Introduction

On-Chip User Program Memory Starts

Here

There are two register banks implemented on these

***

devices. Each bank contains 256 addresses. The purpose of these register banks is to personalize and

***

parameterize the on-chip resources as well as read and

***
0x3FFF

RAM Data Memory Map

write data values.

16K Flash Maximum Depending on Version

The user selects between the two banks by setting the

XIO bit in the CPU_F Flag Register.
In some cases, the same register is available on either
bank, for convenience. These registers (71h to 9fh) can
be accessed from either bank.
Note: All register addresses not shown are reserved and
should never be written. In addition, unused or reserved
bits in any register should always be written to 0.

26

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Register Organization

4.2

Register Bank 0 Map

Table 26:

Bank 0

ARF_CR
CMP_CR
ASY_CR

ACA00CR0
ACA00CR1
ACA00CR2
Reserved
ACA01CR0
ACA01CR1
ACA01CR2
Reserved
ACA02CR0
ACA02CR1
ACA02CR2
Reserved
ACA03CR0
ACA03CR1
ACA03CR2

104

RW

73
101
102

RW
1
1

82
83
84

RW
RW
RW

82
83
84

RW
RW
RW

82
83
84

RW
RW
RW

82
83
84

RW
RW
RW

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

Access

Reserved

Data Sheet
Page

AMX_IN

Address

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

45
46
46
116
113
113
113

RW
RW
RW
RW
RW
R
RW

110
110
111
111
111
111
112
112

W
W
R
R
RW
RW
RW
RW

114

Reserved

54
54
54
55
54
54
54
55
54
54
54
55
54
54
54
55
54
54
54
55
54
54
54
55
54
54
54
55
54
54
54
55

C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
INT_MSK0
E0h
INT_MSK1
E1h
INT_VC
E2h
RES_WDT
E3h
DEC_DH/DEC_CL
E4h
DEC_DL
E5h
DEC_CR
E6h
Reserved
E7h
MUL_X
E8h
MUL_Y
E9h
MUL_DH
EAh
MUL_DL
EBh
ACC_DR1/MAC_X
ECh
ACC_DR0/MAC_Y
EDh
ACC_DR3/MAC_CL0 EEh
ACC_DR2/MAC_CL1 EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
CPU_SCR
FFh
Reserved

RW
W
W

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

Register
Name

31
31
32

88
90
92
93
95
97
99
100
88
90
92
93
95
97
99
100
95
97
99
100
88
90
92
93
95
97
99
100
88
90
92
93

Access

RW
W
W

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh

Data Sheet
Page

31
31
32

Address

RW
W
W

ASA10CR0
ASA10CR1
ASA10CR2
ASA10CR3
ASB11CR0
ASB11CR1
ASB11CR2
ASB11CR3
ASA12CR0
ASA12CR1
ASA12CR2
ASA12CR3
ASB13CR0
ASB13CR1
ASB13CR2
ASB13CR3
ASB20CR0
ASB20CR1
ASB20CR2
ASB20CR3
ASA21CR0
ASA21CR1
ASA21CR2
ASA21CR3
ASB22CR0
ASB22CR1
ASB22CR2
ASB22CR3
ASA23CR0
ASA23CR1
ASA23CR2
ASA23CR3

Reserved

31
31
32

Register
Name

RW
W
W

Access

31
31
32

40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh

Data Sheet
Page

RW
W
W

Address

31
31
32

Reserved

RW
W
W

Reserved

31
31
32

Register
Name

August 18, 2003

Access

DBA00DR0
DBA00DR1
DBA00DR2
DBA00CR0
DBA01DR0
DBA01DR1
DBA01DR2
DBA01CR0
DBA02DR0
DBA02DR1
DBA02DR2
DBA02CR0
DBA03DR0
DBA03DR1
DBA03DR2
DBA03CR0
DCA04DR0
DCA04DR1
DCA04DR2
DCA04CR0
DCA05DR0
DCA05DR1
DCA05DR2
DCA05CR0
DCA06DR0
DCA06DR1
DCA06DR2
DCA06CR0
DCA07DR0
DCA07DR1
DCA07DR2
DCA07CR0

Data Sheet
Page

Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh

Reserved

Register
Name
PRT0DR
PRT0IE
PRT0GS
Reserved
PRT1DR
PRT1IE
PRT1GS
Reserved
PRT2DR
PRT2IE
PRT2GS
Reserved
PRT3DR
PRT3IE
PRT3GS
Reserved
PRT4DR
PRT4IE
PRT4GS
Reserved
PRT5DR
PRT5IE
PRT5GS

27

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

4.3

Register Bank 1 Map

Table 27:

Bank 1

RW
RW
RW

CPU_SCR

40
40

Access

82
83
84

Page

RW
RW
RW

C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh

Data Sheet

82
83
84

Address

RW
RW
RW

OSC_CR0
OSC_CR1
Reserved
VLT_CR
Reserved
Reserved
Reserved
Reserved
IMO_TR
ILO_TR
BDG_TR
ECO_TR

Reserved

82
83
84

Reserved

50
51
53

RW
RW
RW

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

Register
Name

50
51
53

Reserved

50
51
53

82
83
84

88
90
92
93
95
97
99
100
88
90
92
93
95
97
99
100
95
97
99
100
88
90
92
93
95
97
99
100
88
90
92
93

Access

RW
RW ACA00CR0
RW ACA00CR1
ACA00CR2
RW Reserved
RW ACA01CR0
RW ACA01CR1
ACA01CR2
RW Reserved
RW ACA02CR0
RW ACA02CR1
ACA02CR2
RW Reserved
RW ACA03CR0
RW ACA03CR1
ACA03CR2

Page

50
51
53

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh

Data Sheet

RW
RW
RW

Address

50
51
53

ASA10CR0
ASA10CR1
ASA10CR2
ASA10CR3
ASB11CR0
ASB11CR1
ASB11CR2
ASB11CR3
ASA12CR0
ASA12CR1
ASA12CR2
ASA12CR3
ASB13CR0
ASB13CR1
ASB13CR2
ASB13CR3
ASB20CR0
ASB20CR1
ASB20CR2
ASB20CR3
ASA21CR0
ASA21CR1
ASA21CR2
ASA21CR3
ASB22CR0
ASB22CR1
ASB22CR2
ASB22CR3
ASA23CR0
ASA23CR1
ASA23CR2
ASA23CR3

Reserved

RW
RW
RW

RW
RW
W
RW

Register
Name

50
51
53

76
77
106
107

Access

50
51
53

RW CLK_CR0
RW CLK_CR1
RW ABF_CR
AMD_CR
RW
RW
RW

Page

50
51
53

40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh

Data Sheet

W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W

Reserved

32
33
33
34
32
33
33
34
32
33
33
34
32
33
33
34
32
33
33
34
32
33
33
34

Address

Register
Name

28

Access

1.

Page

DBA00FN
DBA00IN
DBA00OU
Reserved
DBA01FN
DBA01IN
DBA01OU
Reserved
DBA02FN
DBA02IN
DBA02OU
Reserved
DBA03FN
DBA03IN
DBA03OU
Reserved
DCA04FN
DCA04IN
DCA04OU
Reserved
DCA05FN
DCA05IN
DCA05OU
Reserved
DCA06FN
DCA06IN
DCA06OU
Reserved
DCA07FN
DCA07IN
DCA07OU
Reserved

Data Sheet

Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh

Reserved

Register
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1

RW
RW

118 RW

35
36
120
37

W
W
W
W

114 1

Read/Write access is bit-specific or varies by function. See register.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

I/O Ports

5.0

I/O Ports

5.1

Introduction

Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide

The circumstances are that during sleep, the reference

I/O port (P5) are implemented. The number of general

voltage on the capacitor is refreshed periodically at the

purpose I/Os implemented and connected to pins

sleep system duty cycle. Between refresh cycles, this

depends on the individual part chosen. All port bits are

voltage may leak slightly to either the positive supply or

independently programmable and have the following

ground. If pins P2[4] or P2[6] are in a high state, the leak-

capabilities:

age to the positive supply is accelerated (especially at

high temperature). Since the reference voltage is com-

General-purpose digital input readable by the CPU.

pared to the supply to detect a low voltage condition, this

General-purpose digital output writable by the CPU.

accelerated leakage to the positive supply voltage will

Independent control of data direction for each port

bit.

Independent access for each port bit to Global Input

and Global Output busses.

cause that voltage to appear lower than it actually is,

leading to the generation of a false Low Voltage Detect
interrupt.
Port 0 and Port 2 have additional analog input and/or

Interrupt programmable to assert on rising edge,

falling edge, or change from last pin state read.

analog output capability. The specific routing and multi-

Output drive strength programmable in logic 0 and 1

states as strong, resistive (pull-up or pull-down), or
high impedance.

gram:

A slew rate controlled output mode is available.

In high impedence, the digital input can be disabled

to lower power consumption.

plexing of analog signals is shown in the following dia-

Port 1, Pin 0 is used in conjunction with device Test

Mode and does not behave the same as other I/O ports
immediately after reset. A device reset with Power On
Reset (POR) will drive P1[0] high for 8 ms immediately
after POR is released because there is a CPU hold-off
time of approximately 64 ms before code execution
begins. It will then drive P1[0] low for 8 ms. This can
impact external circuits connected to Port 1, Pin 0.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is maintained on a capacitor.

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

29

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

GPIO
InterruptEnable
(INT_MSK0:5)

IM0
IM1

From
Other
GPIO
Pins

Rise

1
IM0
IM1

GPIO Int

Fall

Interrupt Mode
IM1 IM0
Output

D Q

0
0
1
1

En

IM0
IM1

GPIO Read

Change

0
1
0
1

Suppress Interrupt
Falling Edge
Rising Edge
Change from last read

To CPU Bus
DM0
DM1

Global Select

Global Input Line

Analog In (Ports 0 and 2 Only)

Bonding
Pad

Analog Out (Port 0 Only)

VDD
Drive Mode
DM1 DM0

DM0
DM1

0
0
1
1

CPU Bus
VDD
D
GPIO Write
Global Out

0
1
0
1

Output
Resistive Pulldown
Strong Drive
High Z (off)
Resistive Pullup

5.6K

Q
DM1

Global Select
DM0
5.6K
VSS

DM0
DM1

VSS

Figure 7: General Purpose I/O Pins

30

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

I/O Registers

6.0

I/O Registers

6.1

Port Data Registers

Table 28:

Port Data Registers

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] When written is the bits for output on port pins. When read is the state of the port pins
Port 0 Data Register (PRT0DR, Address = Bank 0, 00h)
Port 1 Data Register (PRT1DR, Address = Bank 0, 04h)
Port 2 Data Register (PRT2DR, Address = Bank 0, 08h)
Port 3 Data Register (PRT3DR, Address = Bank 0, 0Ch)
Port 4 Data Register (PRT4DR, Address = Bank 0, 10h)
Port 5 Data Register (PRT5DR, Address = Bank 0, 14h) Note: Port 5 is 4-bits wide, Bit [3:0]

6.2

Port Interrupt Enable Registers

Table 29:

Port Interrupt Enable Registers

Bit #

POR

Read/Write

Bit Name

Int En [7]

Int En [6]

Int En [5]

Int En [4]

Int En [3]

Int En [2]

Int En [1]

Int En [0]

Bit [7:0]: Int En [7:0] When written sets the pin interrupt state
0 = Interrupt disabled for pin
1 = Interrupt enabled for pin
Port 0 Interrupt Enable Register (PRT0IE, Address = Bank 0, 01h)
Port 1 Interrupt Enable Register (PRT1IE, Address = Bank 0, 05h)
Port 2 Interrupt Enable Register (PRT2IE, Address = Bank 0, 09h)
Port 3 Interrupt Enable Register (PRT3IE, Address = Bank 0, 0Dh)
Port 4 Interrupt Enable Register (PRT4IE, Address = Bank 0, 11h)
Port 5 Interrupt Enable Register (PRT5IE, Address = Bank 0, 15h) Note: Port 5 is 4-bits wide

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

31

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

6.3

Port Global Select Registers

Table 30:

Port Global Select Registers

Bit #

POR

Read/Write

Bit Name

GlobSel
[7]

GlobSel
[6]

GlobSel
[5]

GlobSel
[4]

GlobSel
[3]

GlobSel
[2]

GlobSel
[1]

GlobSel
[0]

Bit [7:0]: Global Select [7:0] When written determines whether a pin is connected to the Global Input Bus and Global Output Bus
0 = Not Connected
1 = Connected
Drive Mode xx = Global Select Register 0 = Standard CPU controlled port (Default)
Drive Mode 1 0 (High Z) = Global Select Register 1 = Direct Drive of associated Global Input line
Drive Mode 0 0, 0 1, 1 1 = Global Select Register 1 = Direct Receive from associated Global Output line
Port 0 Global Select Register (PRT0GS, Address = Bank 0, 02h)
Port 1 Global Select Register (PRT1GS, Address = Bank 0, 06h)
Port 2 Global Select Register (PRT2GS, Address = Bank 0, 0Ah)
Port 3 Global Select Register (PRT3GS, Address = Bank 0, 0Eh)
Port 4 Global Select Register (PRT4GS, Address = Bank 0, 12h)
Port 5 Global Select Register (PRT5GS, Address = Bank 0, 16h) Note: If implemented, Port 5 is 4-bits wide

6.3.1

Port Drive Mode 0 Registers

Table 31:

Port Drive Mode 0 Registers

Bit #

POR

Read/Write

Bit Name

DM0 [7]

DM0 [6]

DM0 [5]

DM0 [4]

DM0 [3]

DM0 [2]

DM0 [1]

DM0 [0]

Bit [7:0]: DM0 [7:0] The two Drive Mode bits that control a particular port pin are treated as a pair and are decoded
as follows:
Port Data Register Bit 0 = Drive Mode 0 0 = 0 Resistive (Default)
Port Data Register Bit 0 = Drive Mode 0 1 = 0 Strong
Port Data Register Bit 0 = Drive Mode 1 0 = High Z
Port Data Register Bit 0 = Drive Mode 1 1 = 0 Strong
Port Data Register Bit 1 = Drive Mode 0 0 = 1 Strong
Port Data Register Bit 1 = Drive Mode 0 1 = 1 Strong
Port Data Register Bit 1 = Drive Mode 1 0 = High Z
Port Data Register Bit 1 = Drive Mode 1 1 = 1 Resistive
Port 0 Drive Mode 0 Register (PRT0DM0, Address = Bank 1, 00h)
Port 1 Drive Mode 0 Register (PRT1DM0, Address = Bank 1, 04h)
Port 2 Drive Mode 0 Register (PRT2DM0, Address = Bank 1, 08h)
Port 3 Drive Mode 0 Register (PRT3DM0, Address = Bank 1, 0Ch)
Port 4 Drive Mode 0 Register (PRT4DM0, Address = Bank 1, 10h)
Port 5 Drive Mode 0 Register (PRT5DM0, Address = Bank 1, 14h) Note: Port 5 is 4-bits wide

32

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

I/O Registers

6.3.2

Port Drive Mode 1 Registers

Table 32:

Port Drive Mode 1 Registers

Bit #

POR

Read/Write

Bit Name

DM1 [7]

DM1 [6]

DM1 [5]

DM1 [4]

DM1 [3]

DM1 [2]

DM1 [1]

DM1 [0]

Bit [7:0]: DM1 [7:0] See truth table for Port Drive Mode 0 Registers, above
Port 0 Drive Mode 1 Register (PRT0DM1, Address = Bank 1, 01h)
Port 1 Drive Mode 1 Register (PRT1DM1, Address = Bank 1, 05h)
Port 2 Drive Mode 1 Register (PRT2DM1, Address = Bank 1, 09h)
Port 3 Drive Mode 1 Register (PRT3DM1, Address = Bank 1, 0Dh)
Port 4 Drive Mode 1 Register (PRT4DM1, Address = Bank 1, 11h)
Port 5 Drive Mode 1 Register (PRT5DM1, Address = Bank 1, 15h) Note: Port 5 is 4-bits wide

6.3.3

Port Interrupt Control 0 Registers

Table 33:

Port Interrupt Control 0 Registers

Bit #

POR

Read/Write

Bit Name

IC0 [7]

IC0 [6]

IC0 [5]

IC0 [4]

IC0 [3]

IC0 [2]

IC0 [1]

IC0 [0]

Bit [7:0]: IC0 [7:0] The two Interrupt Control bits that control a particular port pin are treated as a pair and are
decoded as follows:
IC1 [x], IC0 [x] = 0 0 = Disabled (Default)
IC1 [x], IC0 [x] = 0 1 = Falling Edge (-)
IC1 [x], IC0 [x] = 1 0 = Rising Edge (+)
IC1 [x], IC0 [x] = 1 1 = Change from Last Direct Read
Port 0 Interrupt Control 0 Register (PRT0IC0, Address = Bank 1, 02h)
Port 1 Interrupt Control 0 Register (PRT1IC0, Address = Bank 1, 06h)
Port 2 Interrupt Control 0 Register (PRT2IC0, Address = Bank 1, 0Ah)
Port 3 Interrupt Control 0 Register (PRT3IC0, Address = Bank 1, 0Eh)
Port 4 Interrupt Control 0 Register (PRT4IC0, Address = Bank 1, 12h)
Port 5 Interrupt Control 0 Register (PRT5IC0, Address = Bank 1, 16h) Note: Port 5 is 4-bits wide

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

33

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

6.3.4

Port Interrupt Control 1 Registers

Table 34:

Port Interrupt Control 1 Registers

Bit #

POR

Read/
Write

Bit Name

IC1 [7]

IC1 [6]

IC1 [5]

IC1 [4]

IC1 [3]

IC1 [2]

IC1 [1]

IC1 [0]

Bit [7:0]: IC1 [7:0] See truth table for Port Interrupt Control 0 Registers, above
Port 0 Interrupt Control 1 Register (PRT0IC1, Address = Bank 1, 03h)
Port 1 Interrupt Control 1 Register (PRT1IC1, Address = Bank 1, 07h)
Port 2 Interrupt Control 1 Register (PRT2IC1, Address = Bank 1, 0Bh)
Port 3 Interrupt Control 1 Register (PRT3IC1, Address = Bank 1, 0Fh)
Port 4 Interrupt Control 1 Register (PRT4IC1, Address = Bank 1, 13h)
Port 5 Interrupt Control 1 Register (PRT5IC1, Address = Bank 1, 17h) Note: Port 5 is 4-bits wide

34

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Clocking

7.0

Clocking

7.1

Oscillator Options

7.1.1

Internal Main Oscillator

The internal main oscillator outputs two frequencies, 48

for which factory calibration was set. The factory-pro-

MHz and 24 MHz. In the absence of a high-precision

grammed trim value is selected using the Table Read

input source from the external oscillator, the accuracy of

Supervisor Call, and is documented in 11.8.

this circuit is +/- 2.5% (between 0oC and +85oC). No

There is an option to phase lock this oscillator to the

external components are required to achieve this level of

External Crystal Oscillator. The choice of crystal and its

accuracy. The Internal Main Oscillator Trim Register

inherent accuracy will determine the overall accuracy of

(IMO_TR) is used to calibrate this oscillator into specified

the oscillator. The External Crystal Oscillator must be

tolerance. Factory-programmed trim values are available

stable prior to locking the frequency of the Internal Main

for 5.0V and 3.3V operation. The 5.0V value is loaded in

Oscillator to this reference source.

the IMO_TR register upon reset. This register must be

adjusted when the operating voltage is outside the range

Table 35:

Internal Main Oscillator Trim Register

Bit #

POR

FS1

FS1

FS1

FS1

FS1

FS1

FS1

FS1

Read/Write

Bit Name

IMO Trim
[7]

IMO Trim
[6]

IMO Trim
[5]

IMO Trim
[4]

IMO Trim
[3]

IMO Trim
[2]

IMO Trim
[1]

IMO Trim
[0]

Bit [7:0]: IMO Trim [7:0] Data value stored will alter the trimmed frequency of the Internal Main Oscillator. A larger
value in this register will increase the speed of the Internal Main Oscillator
1.

FS = Factory set trim value

Internal Main Oscillator Trim Register (IMO_TR, Address = Bank 1, E8h)

7.1.2

Internal Low Speed Oscillator

An internal low speed oscillator of nominally 32 kHz is

available to generate sleep wake-up interrupts and
Watchdog resets if the user does not want to attach a
32.768 kHz watch crystal. This oscillator can also be
used as a clocking source for the digital PSoC blocks.
The oscillator operates in two different modes. A trim
value is written to the Internal Low Speed Oscillator Trim
Register (ILO_TR), shown below, upon reset. See section 13.0 for accuracy information. When the IC is put
into sleep mode this oscillator drops into an ultra low current state and the accuracy is reduced.
This register sets the adjustment for the Internal Low
Speed Oscillator. The value placed in this register is
based on factory testing. It is recommended that the user
not alter this value.
August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

35

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 36:

Internal Low Speed Oscillator Trim Register

Bit #

POR

FS

FS

FS

FS

FS

FS1

Read/
Write

--

Bit Name

Reserved

Disable

ILO Trim
[5]

ILO Trim
[4]

ILO Trim
[3]

ILO Trim
[2]

ILO Trim
[1]

ILO Trim
[0]

Bit 7: Reserved
Bit 6: Disable
0 = Low Speed Oscillator is on
1 = Low Speed Oscillator is off (minimum power state)
Bit [5:0]: ILO Trim [5:0] Data value stored will alter the trimmed frequency of the Internal Low Speed Oscillator. (Not
recommended for customer alteration)
1.

FS = Factory set trim value

Internal Low Speed Oscillator Trim Register (ILO_TR, Address = Bank 1, E9h)

7.1.3

External Crystal Oscillator

The XtalIn and XtalOut pins support connection of a

ond interval, created by the Sleep Interrupt logic.

The 1-second interval gives the oscillator time to
stabilize before it becomes the active source. The
Sleep Interrupt need not be enabled for the switch
over to occur. The user may want to reset the sleep
timer (if this does not interfere with any ongoing
real-time clock operation), to guarantee the interval
length.

32.768 kHz watch crystal to drive the 32K clock. To connect to the external crystal, the XtalIn and XtalOut pins
drive modes must be set to High Z. To enable the external crystal oscillator, bit 7 of the Oscillator Control 0 Register (OSC_CR0) must be set (default is off). Note that
the Internal Low Speed Oscillator continues to run when
this external function is selected. It runs until the oscillator is automatically switched over when the sleep timer
reaches terminal count. External feedback capacitors to
Vcc are required.

5.

The user must wait the 1-second stabilization period

prior to engaging the PLL mode to lock the Internal
Main Oscillator frequency to the External Crystal
Oscillator frequency.

If the proper settings are selected in PSoC Designer, the

The firmware steps involved in switching between the

above steps are automatically done in boot.asm.

Internal Low Speed Oscillator and External Crystal OscilNote: Transitions between oscillator domains may pro-

lator are as follows:

duce glitches on the 32K clock bus. Functions that

1.

2.

3.

4.

36

At reset, the chip begins operation using the Internal

Low Speed Oscillator.

require accuracy on the 32K clock should be enabled

User immediately selects a sleep interval of 1 second in the Oscillator Control 0 Register (OSC_CR0),
as the oscillator stabilization interval.

The External Crystal Oscillator Trim Register (ECO_TR)

User selects External Crystal Oscillator by setting bit

[7] in Oscillator Control 0 Register (OSC_CR0) to 1.
The External Crystal Oscillator becomes the
selected 32.768 kHz source at the end of the 1-sec-

after the transition in oscillator domains.

sets the adjustment for the External Crystal Oscillator.

The value placed in this register at reset is based on factory testing. This register does not adjust the frequency
of the External Crystal Oscillator. It is recommended that
the user not alter this value.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Clocking

Table 37:

External Crystal Oscillator Trim Register

Bit #

POR

FS

FS

FS

FS

FS

FS1

Read/Write

--

--

Reserved

Reserved

Amp [1]

Amp [0]

Bias [1]

Bias [0]

Bit Name

PSSDC [1] PSSDC [0]

Bit [7:6]: PSSDC [1:0] Power System Sleep Duty Cycle. (Not recommended for customer alteration)
0 0 = 1/128
0 1 = 1/512
1 0 = 1/32
1 1 = 1/8
Bit 5: Reserved
Bit 4: Reserved
Bit [3:2]: Amp [1:0] Sets the amplitude of the adjustment. (Not recommended for customer alteration)
Bit [1:0]: Bias [1:0] Sets the bias of the adjustment. (Not recommended for customer alteration)
1.

FS = Factory set trim value

External Crystal Oscillator Trim Register (ECO_TR, Address = Bank 1, EBh)

7.1.4

External Crystal Oscillator Component Connections and Selections

Vc c

Vc c

C1

C2
XtalOut

XtalIn
Crys tal
Figure 8: External Crystal Oscillator Connections

Crystal 32.768 kHz watch crystal such as EPSON

C-002RX (12.5 pF load capacitance)

Table 38:

Capacitors C1, C2
Use NPO-type ceramic caps
C1 = C2 = 25 pF - (Package Cap) - (Board Parasitic
Cap)

8 PDIP

Note: Use this equation if you do not employ PLL mode.

Typical Package Capacitances

Package

Package Capacitance
0.9 pF

20 PDIP

2 pF

20 SOIC

1 pF

20 SSOP

0.5 pF

If you do employ PLL with the External Crystal Oscillator,

28 PDIP

see Application Note AN2027 under Support at http://

28 SOIC

www.cypressmicro.com for equation and details. An

28 SSOP

0.5 pF

error of 1 pF in C1 and C2 gives about 3 ppm error in fre-

44 TQFP

0.5 pF

quency.

48 PDIP
48 SSOP

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

2 pF
1 pF

5 pF
0.6 pF

37

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

7.1.5

Phase-Locked Loop (PLL) Operation

The Phase-Locked Loop (PLL) function generates the

system clock with crystal accuracy. It is designed to provide a 23.986 MHz oscillator when utilized with an external 32.768 kHz crystal. Although the PLL provides
crystal accuracy it requires time to lock onto the reference frequency when first starting. After the External
Crystal Oscillator has been selected and enabled, the
following procedure should be followed to enable the
PLL and allow for proper frequency lock:

1.

Select a CPU frequency of 3 MHz or less.

2.

Enable the PLL.

3.

Wait at least 10 ms.

4.

Set CPU to a faster frequency, if desired. To do this,

write the bits CPU[2:0] in the OSC_CR0 register.
The CPU frequency will immediately change when
these bits are set.

If the proper settings are selected in PSoC Designer, the

above steps are automatically done in boot.asm.

7.2

System Clocking Signals

There are twelve system-clocking signals that are used

based on use of 32.768 kHz crystal. The names of these

throughout the device. Referenced frequencies are

signals and their definitions are as follows:

Table 39:
Signal

System Clocking Signals and Definitions

Definition

48M

The direct 48 MHz output from the Internal Main Oscillator.

24M

The direct 24 MHz output from the Internal Main Oscillator.

24V1

The 24 MHz output from the Internal Main Oscillator that has been passed through a user-selectable 1
to 16 divider {F = 24 MHz / (1 to 16) = 24 MHz to 1.5 MHz}. The divider value is found in the Oscillator
Control 1 Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the
register bits.

24V2

The 24V1 signal that has been passed through an additional user-selectable 1 to 16 divider {F = 24
MHz / ((1 to 16) * (1 to 16)) = 24 MHz to 93.7 kHz}. The divider value is found in the Oscillator Control 1
Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the register
bits.

32K

The multiplexed output of either the Internal Low Speed Oscillator or the External Crystal Oscillator.

CPU

The output from the Internal Main Oscillator that has been passed through a divider that has 8 user
selectable ratios ranging from 1:1 to 1:256, yielding frequencies ranging from 24 MHz to 93.7 kHz.

SLP

The 32K system-clocking signal that has been passed through a divider that has 4 user selectable
ratios ranging from 1:26 to 1:215, yielding frequencies ranging from 512 Hz to 1 Hz. This signal is used
to clock the sleep timer period.

38

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Clocking

The following diagram shows the PSoC MCU Clock Tree of signals 48M through SLP:

PLL Lock Enable

OSC_CR0[6]

IMO Trim Register

IMO_TR[7:0]

48M

48 MHz

Internal
Main
Oscillator

24M

24 MHz

Phase
Lock Loop

24V1 Clock Div isor

OSC_CR1[7:4]
732
n

24V1

24V2 Clock Div isor

OSC_CR1[3:0]

ECO Trim Register

ECO_TR[7:0]

Vcc

CPU Clock Div isor

OSC_CR0[2:0]

P1[1]

External
Crystal
Oscillator

P1[0]

Vcc

24V2

ILO Trim Register

ILO_TR[7:0]

32 kHz Select
OSC_CR0[7]

1
2
4
8
16
32
128
256

CPU

32K

Internal
Low Speed
Oscillator

Sleep Clock Div isor

OSC_CR0[4:3]

26
29
212
215

SLP

Figure 9: PSoC MCU Clock Tree of Signals

7.2.1

CPU and Sleep Timer Clock Options

The CPU is clocked off the CPU system-clocking signal,

The sleep timer is clocked off the SLP system-clocking

which can be configured to run at one of eight rates. This

signal. The SLEEP[1] and SLEEP[0] bits in the Oscillator

selection is independent from all other clock selection

Control 0 Register (OSC_CR0) allow the user to select

functions. It is completely safe for the CPU to change its

from the four available periods.

clock rate without a timing hazard. The CPU clock period

is determined by setting the CPU[2:0] bits in the Oscillator Control 0 Register (OSC_CR0).

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

39

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 40:

Oscillator Control 0 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

32k Select

PLL Mode

Reserved

Sleep [1]

Sleep [0]

CPU [2]

CPU [1]

CPU [0]

Bit 7: 32k Select

0 = Internal low precision 32 kHz oscillator
1 = External Crystal Oscillator
Bit 6: PLL Mode
0 = Disabled
1 = Enabled, Internal Main Oscillator is locked to External Crystal Oscillator
Bit 5: Reserved
Bit [4:3]: Sleep [1:0]
0 0 = 512 Hz or 1.95 ms period
0 1 = 64 Hz or 15.6 ms period
1 0 = 8 Hz or 125 ms period
1 1 = 1 Hz or 1 s period
Bit [2:0]: CPU [2:0]
0 0 0 = 3 MHz
0 0 1 = 6 MHz
0 1 0 = 12 MHz
0 1 1 = 24 MHz
1 0 0 = 1.5 MHz
1 0 1 = 750 kHz
1 1 0 = 187.5 kHz
1 1 1 = 93.7 kHz
Oscillator Control 0 Register (OSC_CR0, Address = Bank 1, E0h)
Table 41:

Oscillator Control 1 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

24V1 [3]

24V1 [2]

24V1 [1]

24V1 [0]

24V2 [3]

24V2 [2]

24V2 [1]

24V2 [0]

Bit [7:4]: 24V1 [3:0] 4-bit data value determines the divider value for the 24V1 system-clocking signal. Note that the
4-bit data value equals n-1, where n is the desired divider value, as illustrated in PSoC MCU Clock Tree of Signals.
See Table 42 on page 41.
Bit [3:0]: 24V2 [3:0] 4-bit data value determines the divider value for the 24V2 system-clocking signal. Note that the
4-bit data value equals n-1, where n is the desired divider value, as illustrated in the PSoC MCU Clock Tree of Signals. See Table 42 on page 41.
Oscillator Control 1 Register (OSC_CR1, Address = Bank 1, E1h)

40

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August 18, 2003

Clocking

7.2.2

24V1/24V2 Frequency Selection

24V1 and 24V2 based on the value written to the

The following table shows the resulting frequencies for

Table 42:
Reg.
Value
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

OSC_CR1 register.

24V1/24V2 Frequency Selection

24V1
MHz
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00

August 18, 2003

24V2 kHz

24000.00
12000.00
8000.00
6000.00
4800.00
4000.00
3428.57
3000.00
2666.67
2400.00
2181.82
2000.00
1846.15
1714.29
1600.00
1500.00
12000.00
6000.00
4000.00
3000.00
2400.00
2000.00
1714.29
1500.00
1333.33
1200.00
1090.91
1000.00
923.08
857.14
800.00
750.00
8000.00
4000.00
2666.67
2000.00
1600.00
1333.33
1142.86
1000.00
888.89
800.00
727.27
666.67
615.38
571.43
533.33
500.00
6000.00
3000.00
2000.00
1500.00
1200.00
1000.00
857.14
750.00
666.67
600.00
545.45
500.00
461.54
428.57
400.00
375.00

Reg.
Value
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F

24V1
MHz
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00

24V2 kHz

4800.00
2400.00
1600.00
1200.00
960.00
800.00
685.71
600.00
533.33
480.00
436.36
400.00
369.23
342.86
320.00
300.00
4000.00
2000.00
1333.33
1000.00
800.00
666.67
571.43
500.00
444.44
400.00
363.64
333.33
307.69
285.71
266.67
250.00
3428.57
1714.29
1142.86
857.14
685.71
571.43
489.80
428.57
380.95
342.86
311.69
285.71
263.74
244.90
228.57
214.29
3000.00
1500.00
1000.00
750.00
600.00
500.00
428.57
375.00
333.33
300.00
272.73
250.00
230.77
214.29
200.00
187.5

Reg.
Value
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF

24V1
MHz
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00

24V2 kHz

2666.67
1333.33
888.89
666.67
533.33
444.44
380.95
333.33
296.30
266.67
242.42
222.22
205.13
190.48
177.78
166.67
2400.00
1200.00
800.00
600.00
480.00
400.00
342.86
300.00
266.67
240.00
218.18
200.00
184.62
171.43
160.00
150.00
2181.82
1090.91
727.27
545.45
436.36
363.64
311.69
272.73
242.42
218.18
198.35
181.82
167.83
155.84
145.45
136.36
2000.00
1000.00
666.67
500.00
400.00
333.33
285.71
250.00
222.22
200.00
181.82
166.67
153.85
142.86
133.33
125.00

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

Reg.
Value
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF

24V1
MHz
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50

24V2 kHz

1846.15
923.08
615.38
461.54
369.23
307.69
263.74
230.77
205.13
184.62
167.83
153.85
142.01
131.87
123.08
115.38
1714.29
857.14
571.43
428.57
342.86
285.71
244.90
214.29
190.48
171.43
155.84
142.86
131.87
122.45
114.29
107.14
1600.00
800.00
533.33
400.00
320.00
266.67
228.57
200.00
177.78
160.00
145.45
133.33
123.08
114.29
106.67
100.00
1500.00
750.00
500.00
375.00
300.00
250.00
214.29
187.50
166.67
150.00
136.36
125.00
115.38
107.14
100.00
93.75

41

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

7.2.3

Digital PSoC Block Clocking Options

All digital PSoC block clocks are a user-selectable

pose I/O pins. There are a total of 16 possible clock

choice of 48M, 24V1, 24V2, or 32K, as well as clocking

options for each digital PSoC block. See the Digital

signals from other digital PSoC blocks or general pur-

PSoC Block section for details.

8.0

Interrupts

8.1

Overview

Interrupts can be generated by the General Purpose I/O

lines, the Power monitor, the internal Sleep Timer, the
eight Digital PSoC blocks, and the four analog columns.
Every interrupt has a separate enable bit, which is contained

in

the

General

Interrupt

Mask

Register

(INT_MSK0) and the Digital PSoC Block Interrupt Mask

Register (INT_MSK1). When the user writes a 1 to a
particular bit position, this enables the interrupt associated with that position. There is a single Global Interrupt
Enable bit in the Flags Register (CPU_F), which can disable all interrupts, or enable those interrupts that also
have their individual interrupt bit enabled. During a reset,
the enable bits in the General Interrupt Mask Register
(INT_MASK0), the enable bits in the Digital PSoC Block
Interrupt Mask Register (INT_MSK1) and the Global
Interrupt Enable bit in the Flags Register (CPU_F) are all
cleared. The Interrupt Vector Register (INT_VC) holds
the interrupt vector for the highest priority pending interrupt when read, and when written will clear all pending
interrupts.
If there is only one interrupt pending and an instruction is
executed that would mask that pending interrupt (by
clearing the corresponding bit in either of the interrupt
mask registers at address E0h or E1h in Bank 0), the
CPU will take that interrupt. Since the pending interrupt
has been cleared and there are no others, the resulting
interrupt vector is 0000h and the CPU will jump to the
user code at the beginning of Flash. To address this
issue, use the macro defined in m8c.inc called
"M8C_DisableIntMask" in PSoC Designer. This macro
brackets the register write with a disable then an enable
of global interrupts.

42

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Interrupts

General Interrupt Mask Register

Bit
7

Bit
6

Bit
5

Bit
4

Bit
3

Bit
2

Bit
1

Bit
0

R
Q

Interrupt
Source

IRQ

IRQ
Flip Flop
1

D
IRQ

...

...

Priority
Decode
Logic

Interrupt
Vector Table

Interrupt Vector

Reset or Decoded Int Ack IRQ

or Iwrite to INT_VC Register
R
v

Interrupt
Source

IRQ

IRQ
Flip Flop
D
Bit
7

Bit
6

Bit
5

Bit
4

Bit
3

Bit
2

Bit
1

Bit
0

Digital PSoC Block Interrupt

Mask Register
Figure 10: Interrupts Overview

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

43

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

8.2

Interrupt Control Architecture

The interrupt controller contains a separate flip-flop for

each interrupt. When an interrupt is generated, it is registered as a pending interrupt. It will stay pending until it is
serviced, a reset occurs, or there is a write to the
INT_VC Register. A pending interrupt will only generate
an interrupt request when enabled by the appropriate

Each digital PSoC block has its own unique Interrupt

Vector and Interrupt Enable bit. There are also individual
interrupt vectors for each of the Analog columns, Supply
Voltage Monitor, Sleep Timer and General Purpose I/Os.

8.3

Interrupt Vectors

Table 43:

ter (INT_MSK1) or General Interrupt Mask Register

(INT_MSK0), and the Global IE bit in the CPU_F register
is set.

Address

Additionally, for GPIO Interrupts, the appropriate enable

Interrupt Priority
Number

mask bit in the Digital PSoC Block Interrupt Mask Regis-

Interrupt Vector Table

Description

and interrupt-type bits for each I/O pin must be set (see

0x0004

Supply Monitor Interrupt Vector

section 6.0, Table 29 on page 31, Table 33 on page 33,

0x0008

DBA00 PSoC Block Interrupt Vector

0x000C

DBA01 PSoC Block Interrupt Vector

0x0010

DBA02 PSoC Block Interrupt Vector

0x0014

DBA03 PSoC Block Interrupt Vector

During the servicing of any interrupt, the MSB and LSB

0x0018

DCA04 PSoC Block Interrupt Vector

of Program Counter and Flag registers (CPU_PC and

0x001C

DCA05 PSoC Block Interrupt Vector

CPU_F) are stored onto the program stack by an auto-

0x0020

DCA06 PSoC Block Interrupt Vector

matic CALL instruction (13 cycles) generated during the

0x0024

DCA07 PSoC Block Interrupt Vector

interrupt acknowledge process. The user firmware may

0x0028

10

Acolumn 0 Interrupt Vector

preserve and restore processor state during an interrupt

0x002C

11

Acolumn 1 Interrupt Vector

0x0030

12

Acolumn 2 Interrupt Vector

0x0034

13

Acolumn 3 Interrupt Vector

0x0038

14

GPIO Interrupt Vector

0x003C

15

Sleep Timer Interrupt Vector

and Table 34 on page 34). For Analog Column Interrupts, the interrupt source must be set (see section 10.10
and Table 77 on page 101).

using the PUSH and POP instructions. The memory oriented CPU architecture requires minimal state saving
during interrupts, providing very fast interrupt context
switching. The Program Counter and Flag registers
(CPU_PC and CPU_F) are restored when the RETI
instruction is executed. If two or more interrupts are
pending at the same time, the higher priority interrupt
(lower priority number) will be serviced first.

0x0040

On-Chip Program Memory Starts

The interrupt process vectors the Program Counter to

the appropriate address in the Interrupt Vector Table.

After a copy of the Flag Register is stored on the stack,

Typically, these addresses contain JMP instructions to

the Flag Register is automatically cleared. This disables

the start of the interrupt handling routine for the interrupt.

all interrupts, since the Global IE flag bit is now cleared.

Executing a RETI instruction restores the Flag register,
and re-enables the Global Interrupt bit.
Nested interrupts can be accomplished by re-enabling
interrupts inside an interrupt service routine. To do this,
set the IE bit in the Flag Register. The user must store
sufficient information to maintain machine state if this is
done.

44

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Interrupts

8.4

Interrupt Masks

Table 44:

General Interrupt Mask Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Reserved

Sleep

GPIO

Acolumn3

Acolumn2

Acolumn1

Acolumn0

Voltage Monitor

Bit 7: Reserved
Bit 6: Sleep Interrupt Enable Bit (see 11.4)
0 = Disabled
1 = Enabled
Bit 5: GPIO Interrupt Enable Bit (see 8.6)
0 = Disabled
1 = Enabled
Bit [4]: Acolumn 3 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [3]: Acolumn 2 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [2]: Acolumn 1 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [1]: Acolumn 0 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit 0: Voltage Monitor Interrupt Enable Bit (see 11.5)
0 = Disabled
1 = Enabled
General Interrupt Mask Register (INT_MSK0, Address = Bank 0, E0h)

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

45

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 45:

Digital PSoC Block Interrupt Mask Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

DCA07

DCA06

DCA05

DCA04

DBA03

DBA02

DBA01

DBA00

Bit 7: DCA07 Interrupt Enable Bit

0 = Disabled
1 = Enabled
Bit 6: DCA06 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 5: DCA05 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 4: DCA04 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 3: DBA03 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 2: DBA02 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 1: DBA01 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 0: DBA00 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Digital PSoC Block Interrupt Mask Register (INT_MSK1, Address = Bank 0, E1h)

8.5

Interrupt Vector Register

Table 46:

Interrupt Vector Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2]

Data[1]

Data[0]

Bit [7:0]: Data [7:0]

8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all
pending interrupts
Interrupt Vector Register (INT_VC, Address = Bank 0, E2h)

46

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Interrupts

8.6

GPIO Interrupt

GPIO Interrupts are polarity configurable and pin-wise

the Port x Interrupt Enable Registers (PRTxIE). There

maskable (within each Ports pin configuration registers).

are user selectable options to generate an interrupt on 1)

They all share the same interrupt priority and vector.

any change from the last read state, 2) rising edge, and

Any general purpose I/O can be used as an interrupt

3) falling edge.

source. The GPIO bit in the General Interrupt Mask Reg-

When Interrupt on Change is selected, the state of the

ister (INT_MSK0) must be set to enable pin interrupts, as

GPIO pin is stored when the port is read. Changes from

well as the enable bits for each pin, which are located in

this state will then assert the interrupt, if enabled.

R
1
GPIO Cell

All GPIO INTOUTs

D
Q

IRQ

OR

To Priority
Decode Logic

INTOUTn

PIN
Int Logic

GPIO Int Enable

BIT S, INT_MSK0

GPIO BIT IE
PORTX IE Register
(PRT0IE...PRT5IE)

Figure 11: GPIO Interrupt Enable Diagram

For a GPIO interrupt to occur, the following steps must
be taken:
1.

The pin Drive Mode must be set so the pin can be

an input.

2.

The pin must be enabled to generate an interrupt by

setting the appropriate bit in the Port interrupt
Enable Register (PRTxIE).

3.

The edge type for the interrupt must be set in the

Port Interrupt Control 0 and Control 1 Registers
(PRTxIC0 and PRTxIC1). Edge type must be set to
a value other than 00.

4.

The GPIO bit must be set in the General Interrupt

Mask Register (INT_MSK0).

5.

The Global Interrupt Enable bit must be set.

August 18, 2003

6.

Because the GPIO interrupts all share the same

interrupt vector, the source for the GPIO interrupt
must be cleared before any other GPIO interrupt will
occur (i.e., the OR gate in Figure 11: ors all of the
INTOUTn signals together). If any of the INTOUTn
signals are high, the flip-flop in Figure 11: will not
see a rising edge and no IRQ will occur.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

47

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

9.0

Digital PSoC Blocks

9.1

Introduction

PSoC blocks are user configurable system resources.

dependent on the overall block function selected by the

On-chip digital PSoC blocks reduce the need for many

user.

MCU part types and external peripheral components.

Digital PSoC blocks can be configured to provide a wide
variety of peripheral functions. PSoC Designer Software
Integrated Development Environment provides automated configuration of PSoC blocks by simply selecting
the desired functions. PSoC Designer then generates
the proper configuration information and can print a
device data sheet unique to that configuration.
Digital PSoC blocks provide up to eight, 8-bit multipurpose timers/counters supporting multiple event timers,
real-time clocks, Pulse Width Modulators (PWM), and
CRCs. In addition to all PSoC block functions, communication PSoC blocks support full-duplex UARTs and SPI

The one Control Register (DBA00CR0-DCA07CR0) is

designated Control 0. The function of this register and its
bit mapping is dependent on the overall block function
selected by the user.
If the CPU frequency is 24 MHz and a PSoC timer/
counter of 24-bits or longer is operating at 48 MHz, a
write to the block Control Register to enable it (for example, a call to Timer_1_Start) may not start the block properly. In the failure case, the first count will typically be
indeterminate as the upper bytes fail to make the first
count correctly. However, on the first terminal count, the
correct period will be loaded and counted thereafter.

master or slave functions.

As shown in Figure 12:, there are a total of eight 8-bit
digital PSoC blocks in this device family configured as a
linear array. Four of these are the Digital Basic Type A
blocks and four are the Digital Communications Type A
blocks. Each of these digital PSoC blocks can be configured independently, or used in combination.
Each digital PSoC block has a unique Interrupt Vector
and Interrupt Enable bit. Functions can be stopped or
started with a user-accessible Enable bit.
The Timer/Counter/CRC/PRS/Deadband functions are
available on the Digital Basic Type A blocks and also the
Digital Communications Type A blocks. The UART and
SPI communications functions are only available on the
Digital Communications Type A blocks.
There are three configuration registers: the Function
Register (DBA00FN-DCA07FN) to select the block function and mode, the Input Register (DBA00IN-DCA07IN)
to select data input and clock selection, and the Output
Register (DBA00OU-DCA07OU) to select and enable
function outputs.
The three data registers are designated Data 0
(DBA00DR0-DCA07DR0),

Data

(DBA00DR1-

DCA07DR1), and Data 2 (DBA00DR2-DCA07DR2). The

function of these registers and their bit mapping is

48

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

Global Outputs [3:0]

Global Inputs [3:0]

DBA0
(Basic Block)

DCA4
(Comm Block)

DBA1
(Basic Block)

DCA5
(Comm Block)

DBA2
(Basic Block)

DBA3
(Basic Block)

*Decimator/
Incremental

*Broadcast

DCA6
(Comm Block)

DCA7
(Comm Block)

*Decimator/
Incremental

Global Inputs [7:4]

Global Outputs [7:4]

Figure 12: Digital Basic and Digital Communications PSoC Blocks

*Three of the digital blocks have special functions. DBA3 is a Broadcast block, with output directly available to
all digital blocks as a clock or data input. Blocks DBA2 and DCA6 have selectable connections to support
Delta Sigma and Incremental A/D converters.

9.2

Digital PSoC Block Bank 1

Registers

9.2.1

Digital Basic Type A / Communications

Type A Block xx Function Register

The Digital Basic Type A/ Communications Type A Block

xx Function Register (DBA00FN-DCA07FN) consists of
3 bits [2:0] to select the block function, 2 bits [4:3] to
select mode of operation, and 1 bit [5] to indicate the last
block in a group of chained blocks.

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

49

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 47:

Digital Basic Type A/ Communications Type A Block xx Function Register

Bit #

POR

RW

RW

Read/Write

RW

Bit Name

Reserved

Reserved End

RW

RW

RW

RW

RW

Mode 1

Mode 0

Function [2]

Function [1]

Function [0]

Bit 7: Reserved
Bit 6: Reserved
Bit 5: End
0 = PSoC block is not the end of a chained function (End should not be set to 0 in block DCA07)
1 = PSoC block is the end of a chained function, or is an unchained PSoC block
Bit 4: Mode 1 The definition of the Mode [1] bit depends on the block function selected
Timer: The Mode [1] bit signifies the Compare Type
0 = Less Than or Equal
1 = Less Than
Counter: The Mode [1] bit signifies the Compare Type
0 = Less Than or Equal
1 = Less Than
CRC/PRS: The Mode [1] bit is unused in this function
Deadband: The Mode [1] bit is unused in this function
UART: The Mode[1] bit signifies the Interrupt Type (Transmitter only)
0 = Transmit: Interrupt on TX_Reg Empty
1 = Transmit: Interrupt on TX Complete
SPI: The Mode[1] bit signifies the Interrupt Type
0 = Master: Interrupt on TX Reg Empty, Slave: Interrupt on RX Reg Full
1 = Master: Interrupt on SPI Complete, Slave: Interrupt on SPI Complete
Bit 3: Mode 0 The definition of the Mode [0] bit depends on the block function selected
Timer: The Mode [0] bit signifies Interrupt Type
0 = Terminal Count
1 = Compare True
Counter: The Mode [0] bit signifies Interrupt Type
0 = Terminal Count
1 = Compare True
CRC/PRS: The Mode [0] bit is unused in this function
Deadband: The Mode [0] bit is unused in this function
UART: The Mode [0] bit signifies the Direction
0 = Receive
1 = Transmit
SPI: The Mode [0] bit signifies the Type
0 = Master
1 = Slave
Bit [2:0]: Function [2:0] The Function [2:0] bits select the block function which determines the basic hardware configuration
0 0 0 = Timer (chainable)
0 0 1 = Counter (chainable)
0 1 0 = CRC/PRS (Cyclical Redundancy Checker or Pseudo Random Sequencer) (chainable)
0 1 1 = Reserved
1 0 0 = Deadband for Pulse Width Modulator
1 0 1 = UART (function only available on DCA type blocks)
1 1 0 = SPI (function only available on DCA type blocks)
1 1 1 = Reserved

Digital Basic Type A Block 00 Function Register

Digital Basic Type A Block 01 Function Register
Digital Basic Type A Block 02 Function Register
Digital Basic Type A Block 03 Function Register
Digital Communications Type A Block 04 Function Register

50

(DBA00FN, Address = Bank 1, 20h)

(DBA01FN, Address = Bank 1, 24h)
(DBA02FN, Address = Bank 1, 28h)
(DBA03FN, Address = Bank 1, 2Ch)
(DCA04FN, Address = Bank 1, 30h)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

Digital Communications Type A Block 05 Function Register

Digital Communications Type A Block 06 Function Register
Digital Communications Type A Block 07 Function Register

9.2.2

(DCA05FN, Address = Bank 1, 34h)

(DCA06FN, Address = Bank 1, 38h)
(DCA07FN, Address = Bank 1, 3Ch)

Digital Basic Type A / Communications Type A Block xx Input Register

The Digital Basic Type A / Communications Type A Block

select the primary data/enable input. The actual usage of

xx Input Register (DBA00IN-DCA07IN) consists of 4 bits

the input data/enable is function dependent.

[3:0] to select the block input clock and 4 bits [7:4] to

Table 48:

Digital Basic Type A / Communications Type A Block xx Input Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [3]

Data [2]

Data [1]

Data [0]

Clock [3]

Clock [2]

Clock [1]

Clock [0]

Bit [7:4]: Data [3:0] Data Enable Source Select

0 0 0 0 = Data = 0
0 0 0 1 = Data = 1
0 0 1 0 = Digital Block 03
0 0 1 1 = Chain Function to Previous Block
0 1 0 0 = Analog Column Comparator 0
0 1 0 1 = Analog Column Comparator 1
0 1 1 0 = Analog Column Comparator 2
0 1 1 1 = Analog Column Comparator 3
1 0 0 0 = Global Output[0] (for Digital Blocks 00 to 03) or Global Output[4] (for Digital Blocks 04 to 07)
1 0 0 1 = Global Output[1] (for Digital Blocks 00 to 03) or Global Output[5] (for Digital Blocks 04 to 07)
1 0 1 0 = Global Output[2] (for Digital Blocks 00 to 03) or Global Output[6] (for Digital Blocks 04 to 07)
1 0 1 1 = Global Output[3] (for Digital Blocks 00 to 03) or Global Output[7] (for Digital Blocks 04 to 07)
1 1 0 0 = Global Input[0] (for Digital Blocks 00 to 03) or Global Input[4] (for Digital Blocks 04 to 07)
1 1 0 1 = Global Input[1] (for Digital Blocks 00 to 03) or Global Input[5] (for Digital Blocks 04 to 07)
1 1 1 0 = Global Input[2] (for Digital Blocks 00 to 03) or Global Input[6] (for Digital Blocks 04 to 07)
1 1 1 1 = Global Input[3] (for Digital Blocks 00 to 03) or Global Input[7] (for Digital Blocks 04 to 07)
Bit [3:0]: Clock [3:0] Clock Source Select
0 0 0 0 = Clock Disabled
0 0 0 1 = Global Output[4] (for Digital Blocks 00 to 03) or Global Output[0] (for Digital Blocks 04 to 07)
0 0 1 0 = Digital Block 03 (Primary Output)
0 0 1 1 = Previous Digital PSoC block (Primary Output)
0 1 0 0 = 48M
0 1 0 1 = 24V1
0 1 1 0 = 24V2
0 1 1 1 = 32k
1 0 0 0 = Global Output[0] (for Digital Blocks 00 to 03) or Global Output[4] (for Digital Blocks 04 to 07)
1 0 0 1 = Global Output[1] (for Digital Blocks 00 to 03) or Global Output[5] (for Digital Blocks 04 to 07)
1 0 1 0 = Global Output[2] (for Digital Blocks 00 to 03) or Global Output[6] (for Digital Blocks 04 to 07)
1 0 1 1 = Global Output[3] (for Digital Blocks 00 to 03) or Global Output[7] (for Digital Blocks 04 to 07)
1 1 0 0 = Global Input[0] (for Digital Blocks 00 to 03) or Global Input[4] (for Digital Blocks 04 to 07)
1 1 0 1 = Global Input[1] (for Digital Blocks 00 to 03) or Global Input[5] (for Digital Blocks 04 to 07)
1 1 1 0 = Global Input[2] (for Digital Blocks 00 to 03) or Global Input[6] (for Digital Blocks 04 to 07)
1 1 1 1 = Global Input[3] (for Digital Blocks 00 to 03) or Global Input[7] (for Digital Blocks 04 to 07)

Digital Basic Type A Block 00 Input Register

Digital Basic Type A Block 01 Input Register
Digital Basic Type A Block 02 Input Register
Digital Basic Type A Block 03 Input Register
Digital Communications Type A Block 04 Input Register
Digital Communications Type A Block 05 Input Register

August 18, 2003

(DBA00IN, Address = Bank 1, 21h)

(DBA01IN, Address = Bank 1, 25h)
(DBA02IN, Address = Bank 1, 29h)
(DBA03IN, Address = Bank 1, 2Dh)
(DCA04IN, Address = Bank 1, 31h)
(DCA05IN, Address = Bank 1, 35h)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

51

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Digital Communications Type A Block 06 Input Register

Digital Communications Type A Block 07 Input Register

(DCA06IN, Address = Bank 1, 39h)

(DCA07IN, Address = Bank 1, 3Dh)

The Data/Enable source select [3:0] bits select between

The Clock[3:0] bits select multiple sources for the clock

multiple inputs to the Digital PSoC Blocks. These inputs

for each digital PSoC block. The sources for each digital

serve as Clock Enables or Data Input depending on the

PSoC block clock are selected from the Global Input

Digital PSoC Blocks programmed function. If Chain

Bus, System Clocks, and other neighboring digital PSoC

Function to Previous data input is selected for Data/

blocks. As shown in the table, Digital PSoC Blocks 0-3

Enable then the selected Digital PSoC block receives its

can interface to Global I/Os 00-03, and Digital PSoC

Data, Enable, Zero Detect, and all chaining information

block 04-07 can interface to Global I/Os 4-7. It is impor-

from the previous digital PSoC block. The data inputs

tant to note that clock inputs selected from the GPIO pins

that are selected from the GPIO pins (through the Global

(through the Global Input Bus) are not synchronized.

Input Bus) are synchronized to the 24 MHz clock. The

This may cause indeterminate results if the CPU reads a

following table shows the function dependent meaning of

block register as it is changing in response to an external

the data input.

clock. CPU reads must be manually synchronized, either

Table 49:

through the block interrupt, or through a multiple read

Digital Function Data Input Definitions

Function

Data Input

Timer

Positive Edge Capture

Counter

Count Enable (Active High)

CRC

Data Input

PRS

N/A

Deadband

Kill Signal (Active High)

TX UART

N/A

RX UART

RX Data In

SPI Master

MISO (Master In/Slave Out)

SPI Slave

MOSI (Master Out/Slave In)

9.2.3

and voting scheme.

Digital Basic Type A / Communications Type A Block xx Output Register

The digital PSoC blocks outputs can be selected to drive

associated Global Output Bus signals via the Output
Select bits. In addition, the output drive can be selectively enabled in this register. The SPI Slave has an auxiliary input which is also controlled by selections in this
register.

52

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

Table 50:

Digital Basic Type A / Communications Type A Block xx Output Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Reserved

Reserved

AUX Out
Enable

AUX IO Sel
[1]

AUX IO Sel
[0]

Out
Enable

Out Sel
[1]

Out Sel
[0]

Bit 7: Reserved
Bit 6: Reserved
Bit 5: AUX Out Enable
0 = Disable Auxiliary Output
1 = Enable Auxiliary Output (function dependent)
Bit [4:3]: AUX IO Sel [1:0] Function-dependent selection of auxiliary input or output
0 0 = Drive Global Output[0] (for Digital Blocks 00 to 03) or
Input from Global Input[4] or Drive Global Output [4] (for Digital Blocks 04 to 07)
0 1 = Drive Global Output[1] (for Digital Blocks 00 to 03) or
Input from Global Input[5] or Drive Global Output[5] (for Digital Blocks 04 to 07)
1 0 = Drive Global Output[2] (for Digital Blocks 00 to 03) or
Input from Global Input[6] or Drive Global Output[6] (for Digital Blocks 04 to 07)
1 1 = Drive Global Output[3] (for Digital Blocks 00 to 03) or
Input from Global Input[7] or Drive Global Output[7] (for Digital Blocks 04 to 07)
Bit 2: Out Enable
0 = Disable Primary Output
1 = Enable Primary Output (function dependant)
Bit [1:0]: Out Sel [1:0] Primary Output
0 0 = Drive Global Output[0] (for Digital Blocks 00 to 03) or Drive Global Output[4] (for Digital Blocks 04 to 07)
0 1 = Drive Global Output[1] (for Digital Blocks 00 to 03) or Drive Global Output[5] (for Digital Blocks 04 to 07)
1 0 = Drive Global Output[2] (for Digital Blocks 00 to 03) or Drive Global Output[6] (for Digital Blocks 04 to 07)
1 1 = Drive Global Output[3] (for Digital Blocks 00 to 03) or Drive Global Output[7] (for Digital Blocks 04 to 07)

Digital Basic Type A Block 00 Output Register

Digital Basic Type A Block 01 Output Register
Digital Basic Type A Block 02 Output Register
Digital Basic Type A Block 03 Output Register
Digital Communications Type A Block 04 Output Register
Digital Communications Type A Block 05 Output Register
Digital Communications Type A Block 06 Output Register
Digital Communications Type A Block 07 Output Register

(DBA00OU, Address = Bank 1, 22h)

(DBA01OU, Address = Bank 1, 26h)
(DBA02OU, Address = Bank 1, 2Ah)
(DBA03OU, Address = Bank 1, 2Eh)
(DCA04OU, Address = Bank 1, 32h)
(DCA05OU, Address = Bank 1, 36h)
(DCA06OU, Address = Bank 1, 3Ah)
(DCA07OU, Address = Bank 1, 3Eh)

The Primary Output is the source for Previous Digital PSoC Block or Digital Block 03, selections for the Clock
Source Select in the Digital Basic Type A/Communications Type A Block xx Input Register (Table 48 on page 51).
A digital PSoC block may have 0, 1, or 2 outputs depending on its function, as shown in the following table:

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

53

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 51:
Function

Digital Function Outputs

Primary Output

Auxiliary Output

Auxiliary Input

Timer

Terminal Count

Compare True

N/A

Counter

Compare True

Terminal Count

N/A

CRC

N/A

Compare True

N/A

PRS

Serial Data

Compare True

N/A

Deadband

F0

F1

N/A

TX UART

TX Data Out

N/A

N/A

RX UART

N/A

N/A

N/A

SPI Master

MOSI

SCLK

N/A

SPI Slave

MISO

N/A

SS_

9.3

Digital PSoC Block Bank 0 Registers

There are four user registers within each digital PSoC

used during the operation. The status/control register

block: three data registers, and one status/control regis-

(CR0) contains an enable bit that is used for all configu-

ter. The three data registers are DR0, which is a shifter/

rations. In addition, it contains function-specific status

counter, and DR1 and DR2 registers, which contain data

and control, which is outlined below.

9.3.1

Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2

Table 52:

Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2

Bit #

POR

Read/Write

VF1

VF1

VF1

VF1

VF1

VF1

VF1

VF1

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

1.

Varies by function/User Module selection. (See Table 53 on page 55.)

Digital Basic Type A Block 00 Data Register 0

Digital Basic Type A Block 00 Data Register 1
Digital Basic Type A Block 00 Data Register 2
Digital Basic Type A Block 01 Data Register 0
Digital Basic Type A Block 01 Data Register 1
Digital Basic Type A Block 01 Data Register 2
Digital Basic Type A Block 02 Data Register 0
Digital Basic Type A Block 02 Data Register 1
Digital Basic Type A Block 02 Data Register 2
Digital Basic Type A Block 03 Data Register 0
Digital Basic Type A Block 03 Data Register 1
Digital Basic Type A Block 03 Data Register 2
Digital Communications Type A Block 04 Data Register 0
Digital Communications Type A Block 04 Data Register 1
Digital Communications Type A Block 04 Data Register 2
Digital Communications Type A Block 05 Data Register 0
Digital Communications Type A Block 05 Data Register 1
Digital Communications Type A Block 05 Data Register 2
Digital Communications Type A Block 06 Data Register 0
Digital Communications Type A Block 06 Data Register 1

54

(DBA00DR0, Address = Bank 0, 20h)

(DBA00DR1, Address = Bank 0, 21h)
(DBA00DR2, Address = Bank 0, 22h)
(DBA01DR0, Address = Bank 0, 24h)
(DBA01DR1, Address = Bank 0, 25h)
(DBA01DR2, Address = Bank 0, 26h)
(DBA02DR0, Address = Bank 0, 28h)
(DBA02DR1, Address = Bank 0, 29h)
(DBA02DR2, Address = Bank 0, 2Ah)
(DBA03DR0, Address = Bank 0, 2Ch)
(DBA03DR1, Address = Bank 0, 2Dh)
(DBA03DR2, Address = Bank 0, 2Eh)
(DCA04DR0, Address = Bank 0, 30h)
(DCA04DR1, Address = Bank 0, 31h)
(DCA04DR2, Address = Bank 0, 32h)
(DCA05DR0, Address = Bank 0, 34h)
(DCA05DR1, Address = Bank 0, 35h)
(DCA05DR2, Address = Bank 0, 36h)
(DCA06DR0, Address = Bank 0, 38h)
(DCA06DR1, Address = Bank 0, 39h)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

Digital Communications Type A Block 06 Data Register 2

Digital Communications Type A Block 07 Data Register 0
Digital Communications Type A Block 07 Data Register 1
Digital Communications Type A Block 07 Data Register 2
Table 53:

(DCA06DR2, Address = Bank 0, 3Ah)

(DCA07DR0, Address = Bank 0, 3Ch)
(DCA07DR1, Address = Bank 0, 3Dh)
(DCA07DR2, Address = Bank 0, 3Eh)

R/W Variations per User Module Selection

Function

DR0

R/W
1

DR1

R/W

DR2

R/W

Timer

Count

Period Value

Capture Value

RW

Counter

Count

R1

Period Value

Compare Value

RW

CRC

Current Value/CRC Residue

R1

Polynomial Mask Value

Seed Value

RW

PRS

Current Value

R1

Polynomial Mask Value

Seed Value

RW

Deadband

Count

R1

Period Value

Not Used

RW

RX UART

Shifter

NA

Not Used

NA

Data Register

TX UART

Shifter

NA

Data Register

Not Used

NA

SPI

Shifter

NA

TX Data Register

RX Data Register

1.

Each time the register is read, its value is written to the DR2 register.

9.3.2

Digital Basic Type A / Communications Type A Block xx Control Register 0

Table 54:

Digital Basic Type A / Communications Type A Block xx Control Register 0

Bit #

POR

Read/Write

VF1

VF1

VF1

VF1

VF1

VF1

VF1

VF1

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

1.

Varies by function.

Digital Basic Type A Block 00 Control Register 0

Digital Basic Type A Block 01 Control Register 0
Digital Basic Type A Block 02 Control Register 0
Digital Basic Type A Block 03 Control Register 0
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0

August 18, 2003

(DBA00CR0, Address = Bank 0, 23h)

(DBA01CR0, Address = Bank 0, 27h)
(DBA02CR0, Address = Bank 0, 2Bh)
(DBA03CR0, Address = Bank 0, 2Fh)
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

55

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

9.3.3

Digital Basic Type A/Communications Type A Block xx Control Register 0 When Used
as Timer, Counter, CRC, and Deadband

Note that the data in this register, as well as the following

variables selected in the associated Digital Basic Type A/

three registers, are a mapping of the functions of the

Communications Type A Block xx Control Register 0.

Table 55:

Digital Basic Type A/Communications Type A Block xx Control Register 0...

Bit #

POR

--

--

--

--

--

--

--

Read/Write

--

--

--

--

--

--

--

RW

Bit Name

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Enable

Bit 7: Reserved
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit 3: Reserved
Bit 2: Reserved
Bit 1: Reserved
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled

Digital Basic Type A Block 00 Control Register 0

Digital Basic Type A Block 01 Control Register 0
Digital Basic Type A Block 02 Control Register 0
Digital Basic Type A Block 03 Control Register 0
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0

56

(DBA00CR0, Address = Bank 0, 23h)

(DBA01CR0, Address = Bank 0, 27h)
(DBA02CR0, Address = Bank 0, 2Bh)
(DBA03CR0, Address = Bank 0, 2Fh)
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

9.3.4

Digital Communications Type A Block xx Control Register 0 When Used as UART Transmitter

Table 56:

Digital Communications Type A Block xx Control Register 0...

Bit #

POR

Read/
Write

--

--

--

RW

RW

RW

Bit Name

Reserved

Reserved

TX Complete

TX Reg
Empty

Reserved

Parity Type

Parity
Enable

Enable

Bit 7: Reserved
Bit 6: Reserved
Bit 5: TX Complete
0 = Indicates that if a transmission has been initiated, it is still in progress
1 = Indicates that the current transmission is complete (including framing bits)
Optional interrupt source for TX UART. Reset when this register is read.
Bit 4: TX Reg Empty
0 = Indicates TX Data register is not available to accept another byte (writing to register will cause data to be lost)
1 = Indicates TX Data register is available to accept another byte
Note that the interrupt does not occur until at least 1 byte has been previously written to the TX Data Register
Default interrupt source for TX UART. Reset when the TX Data Register (Data Register 1) is written.
Bit 3: Reserved
Bit 2: Parity Type
0 = Even
1 = Odd
Bit 1: Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0

August 18, 2003

(DCA04CR0, Address = Bank 0, 33h)

(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)

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57

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

9.3.5

Digital Communications Type A Block xx Control Register 0 When Used as UART

Receiver

Table 57:

Digital Communications Type A Block xx Control Register 0...

Bit #

POR

Read/Write

RW

RW

RW

Bit Name

Parity
Error

Overrun

Framing
Error

RX Active

RX Reg
Full

Parity
Type

Parity
Enable

Enable

Bit 7: Parity Error

0 = Indicates no parity error detected in the last byte received
1 = Indicates a parity error detected in the last byte received
Reset when this register is read
Bit 6: Overrun
0 = Indicates that no overrun has taken place
1 = Indicates the RX Data register was overwritten with a new byte before the previous one had been read
Reset when this register is read
Bit 5: Framing Error
0 = Indicates correct stop bit
1 = Indicates a missing STOP bit
Reset when this register is read
Bit 4: RX Active
0 = Indicates no communication currently in progress
1 = Indicates a start bit has been received and a byte is currently being received
Bit 3: RX Reg Full
0 = Indicates the RX Data register is empty
1 = Indicates a byte has been loaded into the RX Data register
Interrupt source for RXUART. Reset when the RX Data register is read (Data Register 2)
Bit 2: Parity Type
0 = Even
1 = Odd
Bit 1: Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0

58

(DCA04CR0, Address = Bank 0, 33h)

(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

9.3.6

Digital Communications Type A Block xx Control Register 0 When Used as SPI Transceiver

Table 58:

Digital Communications Type A Block xx Control Register 0...

Bit #

POR

Read/
Write

RW

RW

RW

RW

Bit Name

LSB First

Overrun

SPI Complete

TX Reg
Empty

RX Reg
Full

Clock
Phase

Clock
Polarity

Enable

Bit 7: LSB First

0 = MSB First
1 = LSB First
Bit 6: Overrun
0 = Indicates that no overrun has taken place
1 = Indicates the RX Data register was overwritten with a new byte before the previous one had been read
Reset when this register is read
Bit 5: SPI Complete
0 = Indicates the byte is in process of shifting out
1 = Indicates the byte has been shifted out (reset when register is read)
Optional interrupt source for both SPI Master and SPI Slave. Reset when this register is read
Bit 4: TX Reg Empty
0 = Indicates the TX Data register is not available to accept another byte
1 = Indicates the TX Data register is available to accept another byte
Default interrupt source for SPI Master. Reset when the TX Data Register (Data Register 1) is written.
Bit 3: RX Reg Full
0 = Indicates the RX Data register is empty
1 = Indicates a byte has been loaded into the RX Data register
Default interrupt source for SPI Slave. Reset when the RX Data Register (Data Register 2) is read
Bit 2: Clock Phase
0 = Data changes on leading edge and is latched on trailing edge
1 = Data is latched on leading edge and is changed on trailing edge
Bit 1: Clock Polarity
0 = Non-inverted (clock idle state is low)
1 = Inverted (clock idle state is high)
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0

August 18, 2003

(DCA04CR0, Address = Bank 0, 33h)

(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

59

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

9.4

Global Inputs and Outputs

This allows digital PSoC blocks to route their inputs and

Global Inputs and Outputs provide additional capability

to route clock and data signals to the digital PSoC
blocks. Digital PSoC blocks are connected to the global
input and output lines by configuring the PSoC block
Input

and

Output

registers

(DBA00IN-DCA07IN,

DBA00OU-DCA07OU). These global input and output

lines form an 8-bit global input bus and an 8-bit global
output bus. Four Digital PSoC blocks have access to the
upper half of these buses, while the other four access
the lower half, per the configuration register. These global input/output buses may be connected to the I/O pins
on a per-pin basis using the pin configuration registers.

Table 59:
Global
Input [7]

outputs to pins using the global I/O buses.

9.4.1

Input Assignments

The PSoC block Input Register defines the selection of

Global Inputs to digital PSoC blocks. Only 4 of the Global
Inputs bus lines are available as selections to a given
digital PSoC block as shown in the table below. Once the
Global Input has been selected using the PSoC block
Input Register selection bits, a GPIO pin must be configured to drive the selected Global Input. This configuration may be set in the Port Global Select Register. The
GPIO direction must also be set to input mode by configuring the Port Drive Mode Registers to select High Z.

Global Input Assignments

Global
Input [6]

Global
Input [5]

Global
Input [4]

Global
Input [3]

Global
Input [2]

Global
Input [1]

Global
Input [0]

Port x[7]

Port x[6]

Port x[5]

Port x[4]

Port x[3]

Port x[2]

Port x[1]

Port x[0]

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

9.4.2

Output Assignments

The PSoC block Output Register defines the selection of

puts may drive out to GPIO pins. In this case, once the

the Global Output bus line to be driven by the digital

Global Output has been selected using the PSoC block

PSoC blocks. Only 4 of the Global Output bus lines are

Output Register selection bits, a GPIO pin must be con-

available as selections to a given digital PSoC block as

figured to select the Global Output to drive to the pin.

shown in the table below. The Global Output bus has two

This configuration may be set in the Port Global Select

functions. Since Global Outputs are also selectable as

Register. The GPIO direction must also be set to output

inputs to digital PSoC blocks, signals can be routed

mode (which is the default) by configuring the Port Drive

between blocks using this bus. In addition, Global Out-

Mode Registers to one of the available driving strengths.

Table 60:
Global
Output [7]

Global Output Assignments

Global
Output [6]

Global
Output [5]

Global
Output [4]

Global
Output [3]

Global
Output [2]

Global
Output [1]

Global
Output [0]

Port x[7]

Port x[6]

Port x[5]

Port x[4]

Port x[3]

Port x[2]

Port x[1]

Port x[0]

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03

9.5

Available Programmed Digital Functionality

9.5.1

Timer with Optional Capture

9.5.1.1

Summary

generator. A down counter lies at the heart of the timer

The timer function continuously measures the amount of

time in ticks between two events, and provides a rate

60

functions. Rate generators divide their clock source by

an integer value. Hardware or software generated events

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Digital PSoC Blocks

trigger capture operations that permit calculation of

current count is less than (or less than or equal to) the

elapsed ticks. Timer-configured PSoC blocks may be

value in Data Register 2 (compare type controlled by

chained to arbitrary lengths in 8 bit increments.

Mode[1] in the PSoC block Function Register). The auxil-

9.5.1.2

iary output can be routed via Global Output lines. The

Registers

PSoC block Output Register (DBA00OU-DCA07OU)

Data Register 1 establishes the period or integer clock

division value. Data Register 0 holds the current state of
the down counter. If the function is disabled, writing a

controls output options.

9.5.1.5

Interrupts

period into Data Register 1, will automatically load Data

Interrupts may be generated in either of two ways. First,

Register 0. It is also automatically reloaded on the clock

the PSoC block may optionally generate an interrupt on

cycle after it reaches zero, the terminal count value.

the rising edge of Terminal Count or the rising edge of

When a capture event occurs, the current value of Data

the Compare True signal. The selection of interrupt

Register 0 is transferred to Data Register 2. The cap-

source is determined by the MODE[0] bit of the PSoC

tured value in Data Register 2 may then be read by the

block Function Register (DBA00FN-DCA07FN). The

CPU. In addition to the hardware capture input, A CPU

MODE[1] bit controls whether the comparison operation

read of Data Register 0 generates a software capture

is less than or less than or equal to. If capture events

event. This read will return 0 as data. A subsequent read

are disabled, Data Register 2 can be used to create a

of Data Register 2 will return the captured value. Control

periodic interrupt with a particular offset from the terminal

Register 0 contains one bit to enable/disable the func-

count.

tion.

9.5.1.3

9.5.1.6
Inputs

1.

There are two inputs, the Source Clock and the Hard-

Constraints
Hardware/software synchronous capture is only
available with a clocking rate of 24 MHz and below.

ware Capture signal. The down counter is decremented

on the rising-edge of the Source Clock. A hardware capture event is signaled by a rising edge of the Hardware

Usage Notes

2.

Capture signal. This is synchronized to the 24 MHz sys-

Software Capture
When a capture event occurs, all bytes in a multibyte timer transfer simultaneously from the current
count (Data Register 0) to the capture register (Data
Register 2). To generate a software capture event,
only the least significant Data Register 0 byte needs
to be read by the CPU. This causes the same simultaneous transfer as a hardware event.

tem clock and the data is synchronously transferred to

Data Register 2. The Hardware Capture Signal is ORed
with a software capture signal that is generated when
Data Register 0 is read directly by the CPU. In order to
use the software capture mechanism, the Hardware
Capture signal input selection must be low. The multiplexers selecting these input sources are controlled by
the PSoC block Input Register (DBA00IN-DCA07IN).

9.5.1.4

Outputs

The Terminal Count signal is the primary output and it

exhibits a duty cycle that is the reciprocal of the period
value contained in Data Register 1. In other words, it is
high during the source clock cycle when the value in
Data Register 0 is zero and low otherwise. The Terminal
Count can be routed to additional analog or digital PSoC
blocks or via Global Output lines. The auxiliary output is
the Compare True signal. This output is high when the

August 18, 2003

3.

Disabled State
When the Control Register Enable bit is set to 0,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Register 0 (Counter) to initialize or reset the count. All
outputs are low and the block interrupt is held low.
Disabling a timer does not affect the current count
value and it may be read by the CPU. However,
since hardware/software capture is disabled in this
state, two reads are required to read each byte of a
multi-byte register. One to transfer each Data Register 0 count value to the associated Data Register 2
capture register, then one to read the result in Data
Register 2.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

61

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

4.

Register 2.

Capture vs. Compare

A capture event will overwrite Data Register 2. This
is also the register that holds the compare value.
Therefore, using the capture function may not be
compatible with using the timer compare function.

9.5.2
9.5.2.1

Counter with Optional Compare (PulseWidth) Output

Control Register 0 contains one bit to

enable/disable the function.

9.5.2.3

Inputs

There are two primary inputs, the Source Clock and the
Enable signal. When the Enable signal is high, the down
counter is decremented on the rising-edge of the Source
Clock. The multiplexers selecting these inputs are con-

Summary

trolled by the PSoC block Input Register (DBA00IN-

Conceptually, a counter measures the number of events

between ticks, however, this distinction between
counter and timer blurs because both functions provide a

DCA07IN).

9.5.2.4

Outputs

complete range of clock selections. The counter trades

The counter function drives its primary output signal,

the timers hardware capture for a clock gate or enable

Compare True, high on the falling edge of the Source

and provides a means of adjusting the duty cycle of its

Clock when the value in Data Register 0 is less (or less

output so that it can double as a pulse-width modulator.

than or equal to) the value in Data Register 2. The duty

A down counter lies at the heart of the counter function.

cycle of the pulse-width modulator formed in this way is

Counter-configured PSoC blocks may be chained to

the ratio of Data Register 2 (or Data Register 2 minus

arbitrary lengths in 8 bit increments.

one) to Data Register 1. The choice of compare opera-

In a Counter User Module, the data input is an enable for

counting. Normally, when the enable goes low, the
counter will hold the current count. However, if the
enable happens to go low in the same clock period as
Terminal Count (count of all 0's), one additional count will
occur that will reload the counter from the Period Register. Once the counter is reloaded from the Period Register, counting will stop.

9.5.2.2

tors is determined by the MODE[1] bit. The Compare

value can be routed to additional analog or digital PSoC
blocks or via Global Output lines The auxiliary output signal is the Terminal Count signal which can be routed via
Global Output lines. The PSoC block Output Register
(DBA00OU-DCA07OU) controls output options.

9.5.2.5

Interrupts

Interrupts may be generated in either of two ways. First,

Registers

the PSoC block may optionally generate an interrupt on

Data Register 1 establishes the period of the counter.

Data Register 0 holds the current state of the down
counter. If the function is disabled, writing a period into
Data Register 1, will automatically load Data Register 0.
It is also automatically reloaded on the clock cycle after it
reaches zero, the terminal count value. The value in
Data Register 2 (compare value) is continually compared
to Data Register 0 (count value) to establish the output
pulse-width (duty cycle). Reading Data Register 0 to
obtain the current value of the down counter may occur
only when the function is disabled. When read, this
transfers the value from Data Register 0 to Data Register
2 and returns a 0 on the data bus. The value transferred
to Data Register 2 can then be directly read by the CPU.

the rising edge of Terminal Count or the rising edge of

the Compare signal. The selection of interrupt source is
determined by the MODE[0] bit of the PSoC block Function Register (DBA00FN-DCA07FN). The MODE[1] bit
controls whether the comparison operation is less than
or less than or equal to.

9.5.2.6
1.

Usage Notes

Enable Input
The enable input is synchronous and when low
forces the counter into a hold state. Outputs are
unaffected by the state of the enable input. If an
external source is selected as the enable input, it is
synchronized to the 24 MHz clock.

However, reading the count value in this manner will

overwrite any previously written compare value in Data

62

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August 18, 2003

Digital PSoC Blocks

2.

3.

4.

Disabled State

9.5.3.2

When the Control Register Enable bit is set to 0,

the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Register 0 (Counter) to initialize or reset the count. All
outputs are low and the block interrupt is held low.
Disabling a counter does not affect the current count
value and it may be read by the CPU. Two reads are
required to read each byte of a multi-byte register.
One to transfer each Data Register 0 count value to
the associated Data Register 2 capture register,
then one to read the result in Data Register 2.

Data Register 1 stores the count that controls the

Reading the Count Value

9.5.3.3

A CPU read of Data Register 0 (count value) will

overwrite Data Register 2 (compare value). Therefore, when reading the current count, a previously
written compare value will be overwritten.

The input controls the period and duty cycle of the dead-

state of the dead-time down counter. If the function is

disabled, writing a period into Data Register 1, will automatically load Data Register 0 with the deadband period.
This period is automatically re-loaded into the counter on
each edge of the input signal. Data Register 2 is unused.
Control Register 0 contains one bit to enable/disable the
function.

Inputs

band generator outputs. This input is fixed to be derived

from the primary output of the previous block. If this sigfigured as the previous block, the dead-band outputs will

In a Counter User Module, the data input is an

enable for counting. Normally, when the enable
goes low, the counter will hold the current count.
However, if the enable happens to go low in the
same clock period as Terminal Count (count of all
0's), one additional count will occur that will reload
the counter from the Period Register. Once the
counter is reloaded from the Period Register, counting will stop.

9.5.3.1

elapsed dead time. Data Register 0 holds the current

nal is pulse-width modulated, i.e., if a PWM block is con-

Extra Count

9.5.3

Registers

be similarly modulated. The F0 output corresponds to

the duty cycle of the input (less the dead time) and F1 to
the duty cycle of the inverted input (again, less the dead
time). The clock input to the dead-band generator controls the rate at which the down counter is decremented.
The primary data input is the Kill Signal. When this signal is asserted high, both F0 and F1 outputs will go low.
The multiplexers selecting these input are controlled by
the PSoC block Input Register (DBA00IN-DCA07IN).

Deadband Generator
Summary

9.5.3.4

Outputs

The Deadband function produces two output waveforms,

Both the F0 and F1 outputs can be driven onto the Glo-

F0 and F1, with the same frequency as the input, but

bal Output bus. If the next PSoC block selects Previous

under-lapped so they are never both high at the same

PSoC block for its clock input, it only sees the F0 out-

time. An 8-bit down counter controls the length of the

put of the dead-band function. The PSoC block Output

dead time during which both output signals are low.

Register (DBA00OU-DCA07OU) controls output options.

When the deadband function detects a rising edge on

the input waveform, the F1 output signal goes low and
the counter decrements from its initial value to its terminal count. When the down counter reaches zero, the F0
output signal goes high. The process reverses on the
falling edge of the input waveform so that after the same
dead time, F1 goes high until the input signal transitions
again. Dead-band generator PSoC blocks cannot be
chained to increase the width of the down counter
beyond 8 bits or 256 dead-time ticks.

August 18, 2003

9.5.3.5

Interrupts

The rising edge of the F0 signal provides the interrupt for

this block.

9.5.3.6
1.

Usage Notes

Constraints
The dead time must not exceed the minimum of the
input signals pulse-width high and pulse-width low
time, less two CPU clocks. Dead time equals the
period of the input clock times one plus the value
written to Data Register 1.

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

2.

PSoC blocks can be chained to increase the width of the

Enabling
The data input to the Dead-Band function is hardware to the primary output of the previous block,
which is typically programmed to be a PWM. The
proper order for enabling these blocks (writing the
Control Register 0) is PWM first, then Dead-Band.

3.

5.

chain of N PSoC blocks can generate numbers from 2to 8N-bits wide and sequences of up to 28N-1 distinct values.

9.5.4.2

Disabled State
When the Control Register Enable bit is set to 0,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Register 0 (Counter) to initialize or reset the dead-band
time. All outputs are low and the block interrupt is
held low.

4.

numbers and, hence, the length of the sequence. A

Registers

Data Register 0 implements a linear-feedback shift register. Data Register 2 holds the seed value and when the
block is disabled, a write to Data Register 2 is loaded
directly into Data Register 0 (The block must be disabled
when writing this value). Data Register 1 specifies the
polynomial and width of the numbers in the sequence

Asserting the Kill Signal

(see 9.5.4.6).

When the Kill signal is asserted high, both outputs

FO and F1 are held low. When the Kill signal is
selected from an external source through a Global
Input, it is synchronized to the 24 MHz clock and
therefore has up to 42 ns of latency.

9.5.4.3

Negating the Kill Signal

selecting these inputs is controlled by the PSoC block

The Kill signal may be negated at any time. However, the output may be enabled at an arbitrary time
with respect to the F0 and F1 generation. If exact
timing is required when re-enabling the F0 and F1
outputs, the following procedure is recommended:
1.Kill is asserted.

Inputs

The clock input determines the rate at which the output

sequence is produced. The data input must be set to low
for the block to function as a PRS. The multiplexer for
Input Register (DBA00IN-DCA07IN).

9.5.4.4

Outputs

The PRS function drives the output serial data stream

synchronous with the input clock. The output bits change
on the rising edge of the input clock. The output may be

2.Write to Control Register 0 to disable the

block.

driven on the Global Output bus or to the subsequent

digital PSoC block. The PSoC block Output Register
(DBA00OU-DCA07OU) controls output options.

3.Write to Data Register 1 (Deadband time) to

initialize the period.

9.5.4.5

4.Kill is eventually negated.

The PRS function provides an interrupt based on the

5.Write to Control Register 0 to enable the

block.

Interrupts

Compare signal between Data Register 0 and Data Register 2. Data Register 2 is initially loaded with the seed
value, and therefore a periodic interrupt will be gener-

9.5.4
9.5.4.1

PRS - Pseudo-Random Sequence

Generator

ated when the PRS count matches the seed value.

Summary

The PRS function generates an output waveform corresponding to a sequence of pseudo-random numbers. A
linear-feedback shift register generates the sequence
according to a user-specified polynomial. The width of
the numbers in the sequence is variable and the initial
value is determined by a user-defined seed value. PRS

64

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Digital PSoC Blocks

9.5.4.6

Determining the Polynomial

The PRS function utilizes a different modular architecture with one XOR gate between each bit of the shift reg-

A simple linear-feedback shift register, or LFSR, uses an

ister. A maximal sequence equivalent to that produced

XOR gate to add the values of one or more bits and

by the previous realization is generated by the following

feed the result back into the least-significant bit. One

modular LFSR

possible realization of a 6-bit LFSR providing a maximal

sequence of 63 six-bit values is shown here:

+
1

Figure 13: Polynomial LFSR

Figure 14: Polynomial PRS

Denote the first implementation as a (6, 1) LFSR, where
6 gives the length of the output codes and 1 indicates the
tap which feeds the XOR gate along with the final bit.
Then the modular form just shown is denoted as a [6, 5]
LFSR. In general, the equivalent modular form of a simple N bit LFSR with M taps denoted by (N, t1, t2, , tM) is
given by the notation [N, N-t1, N-t2, , N-tM]. Once the
form (and thus the notation) is determined, the value of

The current LFSR value can only be read when the

block is disabled by setting the Control Register bit 0
to low. Each byte of the current LFSR value (in the
case of a multi-byte block) must be read individually.
The Data Register 0 byte (LFSR), which returns 0,
then the Data Register 1 byte, which returns the
actual value.

9.5.5

CRC - Cyclic Redundancy Check

Data Register 1 is easily determined. The bit corre-

9.5.5.1

sponding to the length and all tap bits are turned on; the

The CRC uses a shift register and XOR gates like the

others are zero. Thus, the polynomial specification for

PRS function. However, instead of an output bit stream,

Data Register 1 to implement a [6, 5] LFSR is

the CRC function expects an input bit stream. Function-

00110000b, or 30h. A maximal sequence PRS for 8-bits

ally the CRC block is identical to the PRS with the excep-

giving 255 codes is [8, 4, 3, 2] with polynomial

tion of the selected input data. Input data must be

10001110b or 8Eh.

presented synchronously to the clock. A polynomial

9.5.4.7
1.

specification permits the length of the input sequence

Usage Notes

over which the cyclic redundancy check computes a

result to be varied. CRC-configured PSoC blocks can be

Disabled State
When the Control Register Enable bit is set to 0,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Register 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.

2.

Reading the LFSR

August 18, 2003

Summary

chained to form longer results.

9.5.5.2

Registers

Data Register 0 implements a linear-feedback shift register. Data Register 2 holds the seed value and when the
block is disabled, a write to Data Register 2 is loaded

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directly into Data Register 0 (The block must be disabled

CCIT example, two PSoC blocks must be chained

when writing this value). Data Register 1 specifies the

together. Data Register 1 in the high-order PSoC block

polynomial and width of the numbers in the sequence

would take the value 10001000b (88h) and the corre-

(see Specifying the Polynomial, below). Once the input

sponding register in the low-order PSoC block would

bit stream is complete, the result may be read by first

take 00010000b (10h).

reading Data Register 0, which returns 0, then reading

Data Register 2, which returns the actual result.

9.5.5.3

9.5.5.7
1.

Inputs

sequence is processed. The data input selects the data

stream to process. It is assumed that the data is valid on
the positive edge of the clock input. The multiplexer for
Input Register (DBA00IN-DCA07IN).

9.5.5.4

Outputs

Like the PRS, the CRC function drives the output serial
data stream with the most significant bit of CRC processing synchronous with the input clock. Normally the CRC
output is not used. The output may be driven on the Global Output bus or to the subsequent digital PSoC block.
The

PSoC

block

Output

Register

(DBA00OU-

DCA07OU) controls output options.

9.5.5.5

2.

Reading the CRC value

After the data stream has been processed by the
LFSR, the residue is the CRC value. The current
LFSR value can only be read when the block is disabled by setting the Control Register bit 0 to low.
Each byte of the current LFSR value (in the case of
a multi-byte block) must be read individually. The
Data Register 0 byte (LFSR) must be read, which
returns 0, then the Data Register 2 byte, which
returns the actual value.

9.5.6
9.5.6.1

Interrupts

The CRC function provides an interrupt based on the

Compare signal between Data Register 0 and Data Register 2.

9.5.5.6

Disabled State
When the Control Register Enable bit is set to 0,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Register 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.

The clock input determines the rate at which the input

selecting these inputs is controlled by the PSoC block

Usage Notes

Universal Asynchronous Receiver

Summary

The Universal Asynchronous Receiver implements the

input half of a basic 8-bit UART. Start and Stop bits are
recognized and stripped. Parity type and parity validation
are configurable features. This function requires a Digital

Specifying the Polynomial

Computation of an N-bit result is generally specified by a

polynomial with N+1 terms, the last of which is the X0

Communications Type PSoC block and cannot be

chained for longer data words.

9.5.6.2

Registers

term, where X0=1. For example, the widely used CRC-

The function shifts incoming data into Data Register 0.

CCIT 16-bit polynomial is X16+X12+X5+1. The PSoC

Once complete, the byte is transferred to Data Register 2

block CRC function assumes the presence of the X0

from which it may be read. Data Register 2 acts as a 1

term so that the polynomial for an N-bit result can be

expressed by an N-bit rather than N+1 bit specification.
To obtain the PSoC block register specification, write an
N+1 bit binary number corresponding to the full polynomial, with 1s for each term present. The CRC-CCIT

byte receive buffer. Data Register 1 is not used by this

function. Control Register 0 (DCA04CR0-DCA07CR0)
enables the function, provides the means to configure
parity checking, and a full set of status indications. See
the register definition for full details.

polynomial would be 10001000000100001b. Simply

drop the right-most bit (the X0 term) to obtain the register
specification for the PSoC block. To implement the CRC-

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Digital PSoC Blocks

9.5.6.3

Inputs

9.5.7.2

Registers

A baud-rate clock running at 8 times the desired input bit

When Data Register 0 is empty and a new byte has been

rate is selected by the clock-input multiplexer The serial

written to Data Register 1, the function transfers the byte

data input and clock input are controlled

to Data Register 0 and shifts it out along with a start bit,

by the Input

Register (DCA04IN-DCA07IN).

9.5.6.4

optionally a parity bit and a stop bit. Once Data Register

0 is loaded with the byte to shift out, Data Register 0 can

Outputs

be immediately loaded with the next byte to transmit, acting as a 1 byte transmit buffer. Data Register 2 is not

None.

9.5.6.5

used by this function. The PSoC blocks Control Register

Interrupts

0 (DCA04CR0-DCA07CR0) configures the parity type

The function can be configured to generate an interrupt

on RXREGFULL (Receive Register Full) status (Data

and enable. It also provides status information to enable

detection of transmission complete.

Register 2 is full)

9.5.7.3

9.5.6.6

A baud-rate clock running at 8 times the desired output

1.

Usage Notes

Inputs

bit rate is selected by the clock-input multiplexer con-

Reading the Status

trolled by the PSoC block Input Register (DCA04IN-

Reading Control Register 0, which contains the status bits, automatically resets all status bits to 0 with
the exception of RX Reg Full. Reading Data Register 2 (Receive Data Register) clears the RX Reg Full
status.

DCA07IN). The Data Input multiplexer is ignored by this

function.

9.5.7.4

Outputs

The transmitters serial data output appears at the PSoC

2.

Using Interrupts

block output and may be driven onto one of the Global

RX Reg Full status generates an interrupt but the

Receive Data Register (Data Register 2) must be
read to clear the RX Reg Full status. If this registers
is not read in the interrupt routine, the status will not
be cleared and further interrupts will be suppressed.
If the stop bit in a transmitted byte is missing, the
receiver will declare a framing error. Once this
occurs, this missing stop bit can be interpreted as
the start bit of the next byte, which will produce
another framing error.

9.5.7
9.5.7.1

Universal Asynchronous Transmitter

Output bus lines. The PSoC block Output Register

(DCA04OU-DCA07OU) controls output options.

9.5.7.5

If enabled, the function will generate an interrupt when

the TX Reg Empty status is set (Data Register 1 is
empty). Optionally, the interrupt can be set to TX Complete status, which indicates all bits of a given byte have
been sent, including framing bits. This option is selected
based on the Mode[1] bit in the Function Register.

9.5.7.6

Summary

The Universal Asynchronous Transmitter implements the

1.

output half of a basic 8-bit UART. Start and Stop bits are

Usage Notes

TX Reg Empty Interrupt

An initial byte must be written to the TX Data Register (Data Register 1) to enable subsequent TX Reg
Empty status interrupts. This does not apply if the
TX Complete interrupt source is selected.

generated. Parity bit generation and type are configurable features. This function requires a Digital Communications Type PSoC block. It cannot be chained for
longer data words.

Interrupts

2.

Reading the Status

Reading Control Register 0, which contains the status bits, automatically resets the status bits to 0,

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

9.5.8

except for TX Reg Empty. TX Reg Empty is automatically cleared when a byte is written to the TX
Data Register (Data Register 1).
3.

SPI Master - Serial Peripheral Interface

(SPIM)

9.5.8.1

Using CPU Interrupts

Summary

The SPI Master function provides a full-duplex synchroTX Reg Empty status or optionally TX Complete status generates the block interrupt. Executing the
interrupt routine does not automatically clear status.
If TX Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the interrupt routine to clear the status. If TX Reg Empty is
selected, a byte must be written to the TX Data Register (Data Register 1) to clear the status. If the status is not cleared, further interrupts will be
suppressed.

nous data transceiver that also generates a bit clock for

the data. This function requires a Digital Communications Type PSoC block. It cannot be chained for longer
data words. This Digital Communications Type PSoC
block supports SPI modes for 0, 1, 2, and 3. See Figure
15: for waveforms of the Clock Phase modes.

Clock Phase 0 (Mode 0, 1)

Data registered on the leading edge of the clock
Data output on the trailing edge of the clock
SS_ (required f or slav e)

SCLK

Polarity=0, Mode 0
Polarity=1, Mode 1

MOSI/MISO

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Clock Phase 1 (Mode 2, 3)

Data output on the leading edge of the clock
Data registered on the trailing edge of the clock
SS_ (optional f or slav e)
Polarity=0, Mode 2
SCLK

Polarity=1, Mode 3

MOSI/MISO

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Figure 15: SPI Waveforms

9.5.8.2

Registers

0, the received byte is transferred into Data Register 2

Data Register 0 provides a shift register for both incoming and outgoing data. Output data is written to Data
Register 1 (TX Data Register). When this block is idle, a
write to the TX Data Register will initiate a transmission.
Input data is read from Data Register 2 (RX Data Register). When Data Register 0 is empty, its value is updated
from Data Register 1, if new data is available. As data

from where it can be read. Simultaneously, the next byte

to transmit, if available, is transferred from Data Register
1 into Data Register 0. Control Register 0 (DCA04CR0DCA07CR0) provides status information and configures
the function for one of the four standard modes, which
configure the interface based on clock polarity and
phase with respect to data.

bits are shifted in, the transmit bits are shifted out. After
the 8 bits are transmitted and received by Data Register

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Digital PSoC Blocks

If the SPI Master block is being used to receive data,

dummy bytes must be written to the TX Data Register
in order to initiate transmission/reception of each byte.

9.5.8.3

Inputs

MISO (master-in, slave-out) is selected by the input mul-

interrupt routine does not automatically clear status.

If SPI Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the interrupt routine to clear the status. If TX Reg Empty status is selected, a byte must be written to the TX
Data Register (Data Register 1) to clear the status. If
the interrupting status is not cleared further interrupts will be suppressed.

tiplexer. The clock input multiplexer selects a clock that

runs at twice the desired data rate. The SPIM function

9.5.9

divides the input clock by 2 to obtain the 50% duty-cycle

required for proper timing. The input multiplexer is con-

9.5.9.1

SPI Slave - Serial Peripheral Interface

(SPIS)
Summary

trolled by the PSoC block Input Register (DCA04INThe SPI Slave function provides a full-duplex bi-direc-

DCA07IN).

tional synchronous data transceiver that requires an

9.5.8.4

Outputs

externally provided bit clock for the data. This function

There are two outputs, both of which can be enabled

onto the Global Output bus. The MOSI (master-out,
slave-in) data line provides the output serial data. The
second output is the bit-clock derived by dividing the
input clock by 2 to ensure a 50% duty-cycle. The PSoC
block Output Register (DCA04OU-DCA07OU) controls

requires a Digital Communications Type PSoC block. It

cannot be chained for longer data words. This Digital
Communications Type PSoC block supports SPI modes
for 0, 1, 2, and 3. See Figure 15: for waveforms of the
supported modes.

9.5.9.2

Registers

output options.
Data Register 0 provides a shift register for both incomNote: The SPIM function does not provide the SS_ sig-

ing and outgoing data. Output data is written to Data

nal that may be used by a corresponding SPI Slave.

Register 1 (TX Data Register). Input data is read from

However, this can be implemented with a GPIO pin and

Data Register 2 (RX Data Register). When Data Register

supporting firmware if desired.

0 is empty, its value is updated from Data Register 1. As

9.5.8.5

new data bits are shifted in, the transmit bits are shifted

Interrupts

out. After the 8 bits are transmitted and received by Data

When enabled, the function generates an interrupt on TX

Register 0, the received byte is transferred into Data

Reg Empty status (Data Register 1 empty). If Mode[1] in

Register 2 from which it can be read. Simultaneously, the

the Function Register is set, the SPI Master will generate

next byte to transmit, if available, is transferred from

an interrupt on SPI Complete.

Data Register 1 into Data Register 0. Control Register 0

(DCA04CR0-DCA07CR0) provides status information

9.5.8.6
1.

Usage Notes

and configures the function for one of the four standard

modes, which configure the interface based on clock

Reading the Status

polarity and phase with respect to data.

Reading Control Register 0, which contains the status bits, automatically resets the status bits to 0 with
the exception of TX Reg Empty, which is cleared
when a byte is written to the TX Data Register (Data
Register 1), and the RX Reg Full, which is cleared
when a byte is read from the RX Data Register
(Data Register 2).
2.

9.5.9.3

Inputs

The SPIS function has three inputs. The Input Register

(DCA04IN-DCA07IN) controls the input multiplexer,
which selects the MOSI data stream. It also controls the
clock selection multiplexer from which the function
obtains the masters bit clock. The AUX-IO bits of the

Using Interrupts

Output Register (DCA04OU-DCA07OU) select a Global

TX Reg Empty status or optionally SPI Complete
status generates the block interrupt. Executing the

August 18, 2003

Input signal from which the SS_ (Slave Select) signal is

obtained. It is important to note that the SS_ signal can

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

only be input from GPIO input pins (Global Input Bus).

Register 2) to clear the status. If the interrupting status is not cleared further interrupts will be suppressed.

There is no way to enable the SS_internally. In SPI

modes 2 & 3, where SS is not required between each
byte, the external pin may be grounded.
Important: The AUX Out Enable bit (bit 5) of the Output
Register (DCA04OU-DCA07OU) must be set to 0 to disable it.

9.5.9.4

Outputs

The function output is the MISO (master-in, slave-out)

signal, which may be driven on the Global Output bus
and is selected by Output Register (DCA04OUDCA07OU).

9.5.9.5

4.

Synchronization of CPU Interaction

Because the SPI Slave is clocked asynchronously
by the master SCLK, transfer of data between the
TX Register to shifter and shifter to RX Register
occurs asynchronously.
Either polling or interrupts can be used to detect that
a byte has been received and is ready to read. However, on the TX side, the user is responsible for
implementing a protocol that ensures there is
enough set-up time from the TX Data Register write
to the first clock (mode 2, 3) or SS_ (mode 0, 1) from
the master.

Interrupts

When enabled, the function generates an interrupt on

RX Reg Full status (Data Register 2 full). If Mode[1] of
the Function Register is set, the interrupt will be generated on SPI Complete status.

9.5.9.6
1.

Usage Notes

Reading the Status

Reading Control Register 0, which contains the status bits, automatically resets the status bits to 0 with
the exception of TX Reg Empty, which is cleared
when a byte is written to the TX Data Register (Data
Register 1), and the RX Reg Full, which is cleared
when a byte is read from the RX Data Register
(Data Register 2).

2.

Multi-Slave Environment
The SS_ signal does not have any affect on the output from the slave. The output of the slave at the
end of a reception/transmission is always the first bit
sent (the MSB, unless LSBF option is selected, then
its the LSB). To implement a multi-slave environment, a GPIO interrupt may be configured on the
SS_ input, and the Slave output strength may be
toggled between driving and High Z in firmware.

3.

Using Interrupts
RX Reg Full status or SPI Complete status generates an interrupt. Executing the interrupt routine
does not automatically clear status. If SPI Complete
is selected as the interrupt source, Control Register
0 (status) must be read in the interrupt routine to
clear the status. If RX Reg Full status is selected, a
byte must be read from the RX Data Register (Data

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Analog PSoC Blocks

10.0

Analog PSoC Blocks

10.1

Introduction

PSoC blocks are user configurable system resources.

bit Incremental and 11-bit Delta-Sigma ADC, successive

On-chip analog PSoC blocks reduce the need for many

approximation ADCs up to 6 bits, DACs up to 8 bits, pro-

MCU part types and external peripheral components.

grammable gain stages, sample and hold circuits, pro-

Analog PSoC blocks can be configured to provide a wide

grammable filters, comparators, and a temperature

variety of peripheral functions. PSoC Designer Software

sensor.

Integrated Development Environment provides automated configuration of PSoC blocks by simply selecting
the desired functions. PSoC Designer then generates
the proper configuration information and can print a
device data sheet unique to that configuration.

The analog functionality provided is as follows:

A/D and D/A converters, programmable gain blocks,

comparators, and switched capacitor filters.

Single ended configuration is cost effective for reasonable speed / accuracy, and provides simple
interface to most real-world analog inputs and outputs.

Support is provided for sensor interfaces, audio

codes, embedded modems, and general-purpose
op amp circuits.

Flexible, System on-a-Chip programmability, providing variations in functions.

For a given function, easily selected trade-offs of

accuracy and resolution with speed, resources
(number of analog blocks), and power dissipated for
that application.

The analog section is an Analog Computation Unit,

providing programmed steering of signal flow and
selecting functionality through register-based control
of analog switches. It also sets coefficients in
Switched Capacitor Filters and noise shaping
(Delta-Sigma) modulators, as well as programs gain
or attenuation settings in amplifier configurations.

The architecture provides continuous time blocks

and discrete time (Switched Capacitor) blocks. The
continuous time blocks allow selection of precision
amplifier or comparator circuitry using programmable resistors as passive configuration and parameter
setting elements. The Switched Capacitor (SC)
blocks allow configuration of DACs, Delta Sigma,
incremental or Successive Approximation ADCs, or
Switched Capacitor filters with programmable coefficients.

Each of the analog blocks has many potential inputs and

several outputs. The inputs to these blocks include analog signals from external sources, intrinsic analog signals driven from neighboring analog blocks or various
voltage reference sources.
There are three discrete outputs from each analog block
(there are an additional two discrete outputs in the Continuous Time blocks), 1) the analog output bus (ABUS),
which is an analog bus resource that is shared by all of
the analog blocks in a column, 2) the comparator bus
(CBUS), which is a digital bus resource that is shared by
all of the analog blocks in a column, and 3) the output
bus (OUT, (plus GOUT and LOUT in the Continuous
Time blocks)), which is an analog bus resource that is
shared by all of the analog blocks in a column and connects to one of the analog output buffers, to send a signal externally to the device. There are also intrinsic
outputs that connect to neighboring analog blocks.
Twelve analog PSoC blocks are available separately or
combined with the digital PSoC blocks. A precision internal voltage reference provides accurate analog comparisons. A temperature sensor input is provided to the
analog PSoC block array supporting applications like
battery chargers and data acquisition without requiring
external components.
There are three analog PSoC block types: Continuous
Time (CT) blocks, and Type A and Type B Switch Capacitor (SC) blocks. CT blocks provide continuous time analog functions. SC blocks provide ADC and DAC analog
functions. Currently, supported analog functions are 12-

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10.2

Analog System Clocking Signals

Table 61:

Analog System Clocking Signals

Signal

Definition

ACLK0

A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK0[2:0] bits in the Analog Clock Select Register (CLK_CR1).

ACLK1

A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK1[2:0] bits in the Analog Clock Select Register (CLK_CR1).

A system-clocking signal that can drive all analog PSoC blocks in Analog Column 0. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
Acolumn0
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn0[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 1. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
Acolumn1
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4.The
Acolumn1[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 2. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
Acolumn2
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn2[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 3. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
Acolumn3
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn3[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.

10.3

Array of Analog PSoC Blocks

Analog
Column 0

Analog
Column 1

Analog
Column 2

Analog
Column 3

ACA00

ACA01

ACA02

ACA03

ASA10

ASB11

ASA12

ASB13

ASB20

ASA21

ASB22

ASA23

Figure 16: Array of Analog PSoC Blocks

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Analog PSoC Blocks

10.4

Analog Reference Control

The reference generator establishes a set of three inter-

age between buffered analog grounds, as indicated in

nally fixed reference voltages for the whole chip, AGND,

the AC/DC Characteristics section. RefHi and RefLo sig-

RefHi and RefLo. The 8C26xxx is a single supply part,

nals are generated, buffered and routed to the analog

with no negative voltage available or applicable. Analog

blocks. RefHi is used to set the conversion range (i.e.,

ground (AGND) is constructed near mid-supply. This

span) of analog to digital (ADC) and digital to analog

ground is routed to all analog blocks and separately buff-

(DAC) converters. RefHi and RefLo can be used to set

ered within each block. There may be a small offset volt-

thresholds in comparators.

Vcc

Vbandgap

RefHI to
Analog
Blocks

Port 2.6

Distributed
Gound

2*Vbandgap
Port 2.4
Vcc/2

x12
AGND
Ground Buffer in
Each Analog
Block
RefLO to
Analog
Blocks

Vss

Figure 17: Analog Reference Control Schematic

10.4.1 Bandgap Test
BGT

Alternatively, the power supply can be scaled to provide

Bandgap Test is used for factory testing of the

internal reference voltage testing.

analog ground and references; this is particularly useful

for signals, which are ratiometric to the power supply
voltage.

10.4.2 Bias Level

User supplied external precision references can be con-

HBE

Controls the bias level for all analog functions. It

nected to Port 2 inputs (available on 28 pin and larger

operates with the power setting in each block to set the

parts). This is useful in setting reference for specific cus-

parameters of that block. Most applications will benefit

tomer applications such as a +/-1.000 V (from AGND)

most from the low bias level. At high bias, the analog

ADC scale. References derived from Port 2 inputs are

block op-amps have faster slew rate but slightly less volt-

limited to the same output voltage range as the op-amps

age swing and higher noise.

in the analog blocks.

10.4.3 AGND, RefHI, RefLO

REF

Sets Analog Array Reference Control, selecting

specific combinations of voltage for analog ground and

references. Many of these reference voltages are based
on the precision internal reference, a Silicon band gap
operating at 1.300 Volts. This reference has good thermal stability and power supply rejection.

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Table 62:

AGND, RefHI, RefLO Operating Parameters

AGND
Source
Voltage

RefHI
Source
Voltage

RefLO
Source
Voltage

Notes

000

Vcc/2

2.5 V
1.65 V

Vcc+Vbg

3.8 V
2.95 V

Vcc-Vbg

1.2 V
0.35 V

5.0 V System
3.3 V System

001

P2[4]

2.2 V1

P2[4]+P2[6]

3.2 V1

P2[4]-P2[6]

1.2 V1

User Adjustable

010

Vcc/2

2.5 V
1.65 V

Vcc

5.0 V
3.3 V

Vss

0.0 V
0.0 V

5.0 V System
3.3 V System

011

2*Vbg

2.6 V

2*Vbg+Vbg

3.9 V

2*Vbg-Vbg

1.3 V

100

2*Vbg

2.6 V

2*Vbg+P2[6]

3.6 V

101

P2[4]

2.2 V1

P2[4]+Vbg

3.5 V1

110

Reserved

111

Reserved

1.

Not for 3.3 V Systems

1

2*Vbg-P2[6]

1.6 V

P2[4]-Vbg

0.9 V1

Not for 3.3 V Systems

User Adjustable

Example shown for AGND P2[4] = 2.2 V and Ref P2[6] = 1.0 V

10.4.4 Analog Array Power Control

PWR

Sets Analog Array Power Control. Analog array

power is controlled through the bias circuits in the Continuous Time blocks and separate bias circuits in the
Switched Capacitor blocks. Continuous Time blocks
(ACAxx) can be operated to make low power comparators independent of Switched Capacitor (ASAxx and
ASBxx) blocks, without their power consumption.
The reference array supplies voltage to all blocks and
current to the Switched Capacitor blocks. At higher block
clock rates, there is increased reference current
demand; the reference power should be set equal to the
highest power level of the analog blocks used.

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Analog PSoC Blocks

Table 63:

Analog Reference Control Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

BGT

HBE

REF[2]

REF[1]

REF[0]

PWR[2]

PWR[1]

PWR[0]

Bit 7: BGT Bandgap Test used for internal reference voltage testing (customer should not alter; must be written as 0)
Bit 6: HBE Bias level control for op-amps
0 = Low bias mode for analog array
1 = High bias mode for analog array
Bit [5:3]: REF [2:0] Analog Array Reference Control
AGND
High/Low
0 0 0 = Vcc/2
Bandgap
0 0 1 = P2[4]
P2[6]
0 1 0 = Vcc/2
Vcc/2
0 1 1 = 2 Bandgap Bandgap
1 0 0 = 2 Bandgap P2[6]
1 0 1 = P2[4]
Bandgap
1 1 0 = Reserved
1 1 1 = Reserved
Bit [2:0]: PWR [2:0] Analog Array Power Control
0 0 0 = All Analog Off
0 0 1 = SC Off, REFPWR Low
0 1 0 = SC Off, REFPWR Med
0 1 1 = SC Off, REFPWR High
1 0 0 = All Analog Off
1 0 1 = SC On, REFPWR Low
1 1 0 = SC On, REFPWR Med
1 1 1 = SC On, REFPWR High
Analog Reference Control Register (ARF_CR, Address = Bank 0, 63h)

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.5

Analog PSoC Block Clocking Options

All analog PSoC blocks in a particular Analog Column

2.

share the same clock signal. Choosing the clocking for

an analog PSoC block is a two-step process.
1.

First, if the user wants to use the ACLK0 and

ACLK1 system-clocking signals, the digital PSoC
blocks that serve as the source for these signals
must be selected. This selection is made in the Analog Clock Select Register (CLK_CR1).

Next, the user must select the source for the

Acolumn0, Acolumn1, Acolumn2, and Acolumn3
system-clocking signals. The user will choose the
clock for Acolumnx[1:0] bits in the Analog Column
Clock Select Register (CLK_CR0). Each analog
PSoC block in a particular Analog Column is
clocked from the Acolumn[x] system-clocking signal for that column. (Note that the Acolumn[x] signals have a 1:4 divider on them.)

10.5.1 Analog Column Clock Select Register

Table 64:

Analog Column Clock Select Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Acolumn3
[1]

Acolumn3
[0]

Acolumn2
[1]

Acolumn2
[0]

Acolumn1
[1]

Acolumn1
[0]

Acolumn0
[1]

Acolumn0
[0]

Bit [7:6]: Acolumn3 [1:0]

0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [5:4]: Acolumn2 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [3:2]: Acolumn1 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [1:0]: Acolumn0 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Analog Column Clock Select Register (CLK_CR0, Address = Bank 1, 60h)

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Analog PSoC Blocks

10.6

Analog Clock Select Register

Table 65:

Analog Clock Select Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Reserved

SHDIS

ACLK1 [2]

ACLK1 [1]

ACLK1 [0]

ACLK0 [2]

ACLK0 [1]

ACLK0 [0]

Bit 7: Reserved
Bit 6: SHDIS During normal operation of an SC block for the amplifier of a column enabled to drive the output bus,
the connection is only made for the last half of PHI2 (during PHI1 and for the first half of PHI2, the output bus floats
at the last voltage to which it was driven). This forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the output bus from being perturbed by the intermediate states of the SC
operation (often a reset state for PHI1 and settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the output is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Sample and hold function enabled
1 = Sample and hold function disabled
Bit [5:3]: ACLK1 [2:0]
0 0 0 = Digital Basic Type A Block 00
0 0 1 = Digital Basic Type A Block 01
0 1 0 = Digital Basic Type A Block 02
0 1 1 = Digital Basic Type A Block 03
1 0 0 = Digital Communications Type A Block 04
1 0 1 = Digital Communications Type A Block 05
1 1 0 = Digital Communications Type A Block 06
1 1 1 = Digital Communications Type A Block 07
Bit [2:0]: ACLK0 [2:0] Same configurations as ACLK1 [2:0]
0 0 0 = Digital Basic Type A Block 00
0 0 1 = Digital Basic Type A Block 01
0 1 0 = Digital Basic Type A Block 02
0 1 1 = Digital Basic Type A Block 03
1 0 0 = Digital Communications Type A Block 04
1 0 1 = Digital Communications Type A Block 05
1 1 0 = Digital Communications Type A Block 06
1 1 1 = Digital Communications Type A Block 07
Analog Clock Select Register (CLK_CR1, Address = Bank 1, 61h)
There are a total of twelve analog PSoC blocks imple-

There are two primary types of analog PSoC blocks.

mented for each of the following types; Analog Continu-

Both types contain one op-amp but their principles of

ous Time Type A (ACAxx), Analog Switch Cap Type A

operation are quite different. Continuous-time PSoC

(ASAxx), and Analog Switch Cap Type B (ASBxx).

blocks employ three configuration registers and use

These blocks are arranged in an array of three rows by

resistors to condition amplifier response. Switched

four columns. Each column has one of each type of

capacitor blocks have one comparator and four configu-

PSoC block, and the individual PSoC blocks are identi-

ration registers and operate as discrete-time sampling

fied by the row and column in which they reside.

operators. In both types, the configuration registers are

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

divided into distinct bit fields. Some bit fields set the

neighbors by means of three multiplexers. (Note that

PSoC block's resistor ratios or capacitor values. Others

unlike the switched capacitor blocks, the continuous time

configure switches and multiplexers that form connec-

blocks in the current family of parts only have one sub-

tions between internal block nodes. Additionally, a block

type.) The three are the non-inverting input multiplexer,

may be connected via local interconnection resources to

"PMux," the inverting input multiplexer, "NMux," and the

neighboring analog PSoC blocks, reference voltage

"RBotMux" which controls the node at the bottom of the

sources, input multiplexers and output busses. Specific

resistor string. The bit fields, which control these multi-

advantages and applications of each type are treated

plexers, are named PMux, NMux, and RBotMux, respec-

separately below.

tively.

10.6.1 Local Interconnect

following

diagrams

show

how

each

bors. Each arrow points from an input source, either a

Analog continuous-time PSoC blocks occupy the top

row, (row 0) of the analog array. Designated ACA for
analog continuous-time subtype "A," each connects to its

10.6.1.1

The

multiplexer connects its ACA block connect to its neighPSoC block, bus or reference voltage to the block where
it is used. Each arrow is labeled with the value to which
the bit-field must be set to select that input source.

NMux
N (Inverting) Input Multiplexer Connections
REFLO
(2)

(4)
(3)

ACA
00
(3)
(1)

AGND

REFHI
(3)
(0)

(6)
(5)

(3)
(0)

(4)
(3)

REFLO
(2)

(2)

ACA
01

ACA
02
(1)

(6)
(5)

(4)
(3)

(1)

AGND

REFHI
(3)
(0)

(6)

(3)
(0)

(4)
(3)

ACA
03
(3)
(1)

(6)

(5)

REFLO
(2)

(5)

ASA
10

ASB
11

ASA
12

ASB
13

ASB
20

ASA
21

ASB
22

ASA
23

AGND

Figure 18: NMux Connections

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Analog PSoC Blocks

10.6.1.2

PMux

P (Non-inverting) Input Multiplexer Connections

Port
Inputs

Port
Inputs

Port
Inputs

ABUS 0
(1)

REFLO

(0)

ACA
00

(3)

(5)

AGND

ABUS 1
(1)

(6)
(2)

(2)

Port
Inputs

ACA
01

(0)
(3)

(5)

(4)

(4)

ABUS 2
(1)

(6)
(0)

ACA
02

(3)

ABUS 3
(1)

(6)
(2)

(2)

(5)

(0)

ACA
03

REFLO

(3)

(5)

(4)

AGND

(6)

AGND

(4)

ASA
10

ASB
11

ASA
12

ASB
13

ASB
20

ASA
21

ASB
22

ASA
23

Figure 19: PMux Connections

10.6.1.3

RBotMux

RB Input Multiplexer Connections

VSS

VSS
(2)

(2)

ACA
00
(3)
(1)

AGND

VSS

(0)

(0)

(2)

ACA
01

AGND

(3)

ACA
02

(0)

(3)

AGND

(0)

ACA
03

(1)
(3)

(1)

(1)
(3)

VSS

(3)

AGND

(3)

ASA
10

ASB
11

ASA
12

ASB
13

ASB
20

ASA
21

ASB
22

ASA
23

Figure 20: RBotMux Connections

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.7

Analog Continuous Time PSoC Blocks

10.7.1 Introduction
The Analog Continuous Time PSoC blocks are built
around an operational amplifier. There are several analog muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There is also a precision resistor matrix
that is located in the feedback path for the op-amp, and
is controlled by register-bit setting. There is also an analog comparator connected to the output OUT, which converts analog comparisons into digital signals.
There are five discrete outputs from this block. These
outputs are:
1.

The analog output bus (ABUS), which is an analog

bus resource that is shared by all of the analog
blocks in the analog column for that block.

2.

The comparator bus (CBUS), which is a digital bus

that is a resource that is shared by all of the analog
blocks in a column for that block.

3.

The output bus (OUT, GOUT and LOUT), which is

an analog bus resource that is shared by all of the
analog blocks in a column and connects to one of
the analog output buffers, to send a signal externally
to the device.

This block supports Programmable Gain or attenuation

Op-Amp Circuits, (Differential Gain) Instrumentation
Amplifiers (using two CT Blocks), Continuous time high
frequency anti-aliasing filters, and modest response-time
analog comparators.

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Analog PSoC Blocks

TestMux
REFHI
REFLO
AGND
Gain

ABUS
AnalogBus

PMuxOut

CompCap

OUT

Power
CBUS
CompBus

Block Inputs
Port Input

CLatch

ABUS

CPhase
GOUT

AGND

VCC

PMux
NMux

RTopMux

Block Inputs
AGND

LOUT

REFHI, LO

Gain

RESISTOR
MATRIX

FB

RTapMux
RBotMux

GIN
LIN

SCBLK
AGND

VSS

Figure 21: Analog Continuous Time PSoC Blocks

10.7.2 Registers
10.7.2.1

Analog Continuous Time Block xx Control 0 Register

The RTopMux and RBotMux bits control the connection

The RTapMux bits control the center tap of the resistor

of the two ends of the resistor string. The RTopMux bit

string. Note that only relative weighting of units is given

controls the top end of the resistor string, which can

in the table.

either be connected to Vcc or to the op-amp output. The

RBotMux bits control the connection of the bottom end of
the resistor string.

The Gain and Loss columns correspond to the gain or

loss obtained if the RTopMux and Gain bits are set so
that the overall amplifier provides gain or loss.
The Gain bit controls whether the resistor string is connected around the op-amp as for gain (center tap to

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

inverting op-amp input) or for loss (center tap to output of

Note that connections between GIN and GOUT, and LIN

the block). Note that setting Gain alone does not guaran-

and LOUT are automatically resolved by PSoC Designer

tee a gain or loss block. Routing of the other ends of the

when they are set in a differential configuration with an

resistor determine this.

adjacent CT block.

Table 66:

Analog Continuous Time Block xx Control 0 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

RTapMux[3]

RTapMux[2]

RTapMux[1]

RTapMux[0]

Gain

RTopMux

RBotMux[1]

RBotMux[0]

Bit [7:4]: RTapMux [3:0] Encoding for selecting 1 of 16 resistor taps

0 0 0 0 = Rf 15 = Ri 01 = Loss .0625 / Gain 16.00
0 0 0 1 = Rf 14 = Ri 02 = Loss .1250 / Gain 8.000
0 0 1 0 = Rf 13 = Ri 03 = Loss .1875 / Gain 5.333
0 0 1 1 = Rf 12 = Ri 04 = Loss .2500 / Gain 4.000
0 1 0 0 = Rf 11 = Ri 05 = Loss .3125 / Gain 3.200
0 1 0 1 = Rf 10 = Ri 06 = Loss .3750 / Gain 2.667
0 1 1 0 = Rf 09 = Ri 07 = Loss .4375 / Gain 2.286
0 1 1 1 = Rf 08 = Ri 08 = Loss .5000 / Gain 2.000
1 0 0 0 = Rf 07 = Ri 09 = Loss .5625 / Gain 1.778
1 0 0 1 = Rf 06 = Ri 10 = Loss .6250 / Gain 1.600
1 0 1 0 = Rf 05 = Ri 11 = Loss .6875 / Gain 1.455
1 0 1 1 = Rf 04 = Ri 12 = Loss .7500 / Gain 1.333
1 1 0 0 = Rf 03 = Ri 13 = Loss .8125 / Gain 1.231
1 1 0 1 = Rf 02 = Ri 14 = Loss .8750 / Gain 1.143
1 1 1 0 = Rf 01 = Ri 15 = Loss .9375 / Gain 1.067
1 1 1 1 = Rf 00 = Ri 16 = Loss 1.000 / Gain 1.000
Bit 3: Gain Select gain or loss configuration for output tap
0 = Loss
1 = Gain
Bit 2: RTopMux Encoding for feedback resistor select
0 = Rtop to Vcc
1 = Rtop to op-amps output
Bit [1:0]: RBotMux [1:0] Encoding for feedback resistor select

00=
01=
10=
11=

ACA00
ACA01
AGND
Vss
ASA10

ACA01
ACA00
AGND
Vss
ASB11

ACA02
ACA03
AGND
Vss
ASA12

ACA03
ACA02
AGND
Vss
ASB13

Analog Continuous Time Block 00 Control 0 Register (ACA00CR0, Address = Bank 0/1, 71h)
Analog Continuous Time Block 01 Control 0 Register (ACA01CR0, Address = Bank 0/1, 75h)
Analog Continuous Time Block 02 Control 0 Register (ACA02CR0, Address = Bank 0/1, 79h)
Analog Continuous Time Block 03 Control 0 Register (ACA03CR0, Address = Bank 0/1, 7Dh)

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Analog PSoC Blocks

10.7.2.2

Analog Continuous Time Block xx Control 1 Register

The PMux bits control the multiplexing of inputs to the

CompBus controls a tri-state buffer that drives the com-

non-inverting input of the op-amp. There are physically

parator logic. If no PSoC block in the analog column is

only 7 inputs.

driving the comparator bus, it will be driven low externally

to the blocks.

The 8th code (111) will leave the input floating. This is not

AnalogBus controls the analog output bus. A CMOS

desirable, and should be avoided.

switch connects the op-amp output to the analog bus.

The NMux bits control the multiplexing of inputs to the
inverting input of the op-amp. There are physically only 7
inputs.

Table 67:

Analog Continuous Time Block xx Control 1 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

AnalogBus

CompBus

NMux2

NMux1

NMux0

PMux2

PMux1

PMux0

Bit Name

Bit 7: AnalogBus Enable output to the analog bus

0 = Disable analog bus driven by this block
1 = Enable analog bus driven by this block
Bit 6: CompBus Enable output to the comparator bus
0 = Disable comparator bus driven by this block
1 = Enable comparator bus driven by this block
Bit [5:3]: NMux [2:0] Encoding for negative input select
000=
001=
010=
011=
100=
101=
110=
111=

ACA00
ACA01
AGND
REFLO
REFHI
ACA00
ASA10
ASB11
Reserved

ACA01
ACA00
AGND
REFLO
REFHI
ACA01
ASB11
ASA10
Reserved

ACA02
ACA03
AGND
REFLO
REFHI
ACA02
ASA12
ASB13
Reserved

ACA03
ACA02
AGND
REFLO
REFHI
ACA03
ASB13
ASA12
Reserved

Bit [2:0]: PMux [2:0] Encoding for positive input select

000=
001=
010=
011=
100=
101=
110=
111=

ACA00
REFLO
Port Inputs
ACA01
AGND
ASA10
ASB11
ABUS0
Reserved

ACA01
ACA02
Port Inputs
ACA00
AGND
ASB11
ASA10
ABUS1
Reserved

ACA02
ACA01
Port Inputs
ACA03
AGND
ASA12
ASB13
ABUS2
Reserved

ACA03
REFLO
Port Inputs
ACA02
AGND
ASB13
ASA12
ABUS3
Reserved

Analog Continuous Time Block 00 Control 1 Register (ACA00CR1, Address = Bank 0/1, 72h)
Analog Continuous Time Block 01 Control 1 Register (ACA01CR1, Address = Bank 0/1, 76h)
Analog Continuous Time Block 02 Control 1 Register (ACA02CR1, Address = Bank 0/1, 7Ah)
Analog Continuous Time Block 03 Control 1 Register (ACA03CR1, Address = Bank 0/1, 7Eh)

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.7.2.3

Analog Continuous Time Type A Block xx Control 2 Register

CPhase controls which internal clock phase the compar-

can be obtained if the amplifier is being used as a com-

ator data is latched on.

parator.

CLatch controls whether the latch is active or if it is

TestMux selects block bypass mode for testing and

always transparent.

characterization purposes.

CompCap controls whether the compensation capacitor

Power encoding for selecting 1 of 4 power levels. The

is switched in or not in the op-amp. By not switching in

blocks always power up in the off state.

the compensation capacitance, a much faster response

Table 68:

Analog Continuous Time Type A Block xx Control 2 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

CPhase

CLatch

CompCap

Power[1]

Power[0]

TestMux[2] TestMux[1] TestMux[0]

Bit 7: CPhase
0 = Comparator Control latch transparent on PHI1
1 = Comparator Control latch transparent on PHI2
Bit 6: CLatch
0 = Comparator Control latch is always transparent
1 = Comparator Control latch is active
Bit 5: CompCap
0 = Comparator Mode
1 = Op-amp Mode
Bit [4:2]: TestMux [2:0] Select block bypass mode for testing and characterization purposes
ACA02 ACA03
ACA00 ACA01
1 0 0 = Positive Input to ABUS0 ABUS1
ABUS2 ABUS3
1 0 1 = AGND to
ABUS0 ABUS1
ABUS2 ABUS3
1 1 0 = REFLO to
ABUS0 ABUS1
ABUS2 ABUS3
1 1 1 = REFHI to
ABUS0 ABUS1
ABUS2 ABUS3
0 x x = All Paths Off
Bit [1:0]: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = Low (60 A)
1 0 = Med (150 A)
1 1 = High (500 A)
Analog Continuous Time Block 00 Control 2 Register (ACA00CR2, Address = Bank 0/1, 73h)
Analog Continuous Time Block 01 Control 2 Register (ACA01CR2, Address = Bank 0/1, 77h)
Analog Continuous Time Block 02 Control 2 Register (ACA02CR2, Address = Bank 0/1, 7Bh)
Analog Continuous Time Block 03 Control 2 Register (ACA03CR2, Address = Bank 0/1, 7Fh)

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Analog PSoC Blocks

10.8

Analog Switch Cap Type A PSoC Blocks

10.8.1

Introduction

The Analog Switch Cap Type A PSoC blocks are built

around an operational amplifier. There are several analog muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There are also four arrays of unit value
capacitors that are located in the feedback path for the
op-amp, and are switched by two phase clocks, PHI1
and PHI2. These four capacitor arrays are labeled A Cap
Array, B Cap Array, C Cap Array, and F Cap Array. There
is also an analog comparator connected to the output
OUT, which converts analog comparisons into digital signals.
There are three discrete outputs from this block. These
outputs are:
1.

The analog output bus (ABUS), which is an analog

bus resource that is shared by all of the analog
blocks in the analog column for that block.

2.

The comparator bus (CBUS), which is a digital bus

that is a resource that is shared by all of the analog
blocks in a column for that block.

3.

The output bus (OUT), which is an analog bus

resource that is shared by all of the analog blocks in
a column and connects to one of the analog output
buffers, to send a signal externally to the device.

SC Integrator Block A supports Delta-Sigma, Successive

Approximation and Incremental A/D Conversion, Capacitor DACs, and SC filters. It has three input arrays of binarily-weighted

switched

capacitors,

allowing

user

programmability of the capacitor weights. This provides

summing capability of two (CDAC) scaled inputs, and a
non-switched capacitor input. Since the input of SC
Block A has this additional switched capacitor, it is configured for the input stage of such a switched capacitor
biquad filter. When followed by an SC Block B Integrator,
this combination of blocks can be used to provide a full
Switched Capacitor Biquad.

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

1*AutoZero

BQTAP
CCap
0..31 C

FCap
16,32 C

C Inputs

(2+!AutoZero)
* FSW1
1* FSW0

ACMux
1

A Inputs
REFHI
REFLO
AGND

2+AutoZero
1 *
!AutoZero

ARefMux
ASign

B Inputs

ACap
0..31 C

OUT

AnalogBus*2B

ABUS

BCap
0..31 C
Power
CompBus

CBUS
BMuxSCA

Figure 22: Analog Switch Cap Type A PSoC Blocks

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Analog PSoC Blocks

10.8.2 Local Interconnect

10.8.2.1

AMux

A Input Multiplexer
Connections
ACA
00

ACA
01

ACA
02

ACA
03

(1)

ABUS0

VTemp

(0)

(4
-

P2.2

(3)
(0)

(3)

(1)

RefHi

(2
)

(5
)

ASA
23

(2)

(3)

(2
)

(0)
ASB
22

(3)

(3)

(1)

(3)

(0)

(5
)

(0)

(3)

(3)

(2
)

ASA
21

(1)

ASB
13

(2)

)
-7
(4

(2)

RefHi

)
(4

(1)

ASB
20

(1)

)
(4

)
(4

)
(4
(1)
P2.1

)
-7
(4

RefHi

ASA
12

(2
)

ASB
11

(2)

7)

(0)

(0)

(4
-7
)

(0)

)
(5

)
(5
(1)

ASA
10

ABUS2

ABUS3

Figure 23: AMux Connections

10.8.2.2

CMux

C Input Multiplexer
Connections

ASA
21

ACA
03

ASB
13
(0-3)

ASA
12

)
-7
(4

)
-7
(4

ASB
20

(0-3)
ASB
11
(0-3)

ASA
10

ACA
02
(4
-7
)

ACA
01
(4
-7
)

(0-3)

ACA
00

ASB
22

ASA
23

Figure 24: CMux Connections

August 18, 2003

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.8.2.3

ACMux

However, when the bit is high, it also overrides the two

low order bits, forcing the A and C branches to the same
source. The resulting condition is used to construct low
pass biquad filters. See the individual AMux and CMux
diagrams.

The ACMux, as shown in Analog Switch Cap Type A

Block xx Control 1 Register, controls the input muxing for
both the A and C capacitor branches. The high order bit,
ACMux[2], selects one of two inputs for the C branch.

10.8.2.4

BMuxSCA/SCB

B Input Multiplexer Connections

ASB
11

(1)

ASA
12

(1)

ASA
21

(1
)

(1)

ASB
22

ASA
23

(2)
P2.0

(3)

(2)

ASB
13

(3)

ASB
20

(0)

(0)

(1
)

(0)

(3)

(3)

(2)

(0)

(0)

(0)

(1)

ASA
10

ACA
03

)
(1

)
(1

(2)
P2.3

ACA
02

(0)

ACA
01

(0)

ACA
00

ABUS3

TRefGND

Figure 25: BMuxSCA/SCB Connections

10.8.3 Registers
10.8.3.1

AnalogBus bit in Control 2 Register (ASA10CR2,

ASA12CR2, ASA21CR2, ASA23CR2).

Analog Switch Cap Type A Block xx

Control 0 Register

ASign controls the switch phasing of the switches on the

bottom plate of the ACap capacitor. The bottom plate

FCap controls the size of the switched feedback capaci-

samples the input or the reference.

tor in the integrator.

The ACap bits set the value of the capacitor in the A

ClockPhase controls the internal clock phasing relative

path.

to the input clock phasing. ClockPhase affects the output

of the analog column bus which is controlled by the
Table 69:

Analog Switch Cap Type A Block xx Control 0 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

FCap

ClockPhase

ASign

ACap[4]

ACap[3]

ACap[2]

ACap[1]

ACap[0]

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Analog PSoC Blocks

Table 69:

Analog Switch Cap Type A Block xx Control 0 Register, continued

Bit 7: FCap F Capacitor value selection bit

0 = 16 capacitor units
1 = 32 capacitor units
Bit 6: ClockPhase Clock phase select, will invert clocks internal to the blocks. During normal operation of an SC
block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of
PHI2 (during PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven). This
forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the
output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the output is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Internal PHI1 = External PHI1
1 = Internal PHI1 = External PHI2
This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved in
the output latching mechanism. The capture of the next value to be output from the latch (capture point event) happens during the falling edge of one clock phase, and the rising edge of the other clock phase will cause the value to
come out (output point event). This bit determines which clock phase triggers the capture point event, and the other
clock will trigger the output point event. The value output to the comparator bus will remain stable between output
point events.
0 = Capture Point Event triggered by Falling PHI2, Output Point Event triggered by Rising PHI1
1 = Capture Point Event triggered by Falling PHI1, Output Point Event triggered by Rising PHI2
Bit 5: ASign
0 = Input sampled on Internal PHI1, Reference Input sampled on internal PHI2
1 = Input sampled on Internal PHI2, Reference Input sampled on internal PHI1
Bit [4:0]: ACap [4:0] Binary encoding for 32 possible capacitor sizes for A Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array

1 0 0 0 0 = 16 Capacitor units in array

1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array

Analog Switch Cap Type A Block 10 Control 0 Register (ASA10CR0, Address = Bank 0/1, 80h)
Analog Switch Cap Type A Block 12 Control 0 Register (ASA12CR0, Address = Bank 0/1, 88h)
Analog Switch Cap Type A Block 21 Control 0 Register (ASA21CR0, Address = Bank 0/1, 94h)
Analog Switch Cap Type A Block 23 Control 0 Register (ASA23CR0, Address = Bank 0/1, 9Ch)

August 18, 2003

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89

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.8.3.2

Analog Switch Cap Type A Block xx Control 1 Register

ACMux controls the input muxing for both the A and C

The resulting condition is used to construct low pass

capacitor branches. The high order bit, ACMux[2],

biquad filters.

selects one of two inputs for the C branch. However,

The BCap bits set the value of the capacitor in the B

when the bit is high, it also overrides the two low order

path.

bits, forcing the A and C branches to the same source.

Table 70:

Analog Switch Cap Type A Block xx Control 1 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

ACMux[2]

ACMux[1]

ACMux[0]

BCap[4]

BCap[3]

BCap[2]

BCap[1]

BCap[0]

Bit [7:5] ACMux [2:0] Encoding for selecting A and C inputs. (Note that available mux inputs vary by individual
PSoC block.)
ASA10
A Inputs C Inputs
0 0 0 = ACA00 ACA00
0 0 1 = ASB11 ACA00
0 1 0 = REFHI ACA00
0 1 1 = ASB20 ACA00
1 0 0 = ACA01Reserved
1 0 1 = Reserved Reserved
1 1 0 = Reserved Reserved
1 1 1 = Reserved Reserved

ASA21
A Inputs C Inputs
ASB11
ASB11
ASB20
ASB11
REFHI
ASB11
Vtemp
ASB11
ASA10
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved

ASA12
A Inputs C Inputs
ACA02 ACA02
ASB13 ACA02
REFHI
ACA02
ASB22 ACA02
ACA03 Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved

ASA23
A Inputs C Inputs
ASB13
ASB13
ASB22
ASB13
REFHI
ASB13
ABUS3 ASB13
ASA12
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved

Bit [4:0]: BCap [4:0] Binary encoding for 32 possible capacitor sizes for B Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array

1 0 0 0 0 = 16 Capacitor units in array

1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array

Analog Switch Cap Type A Block 10 Control 1 Register (ASA10CR1, Address = Bank 0/1, 81h)
Analog Switch Cap Type A Block 12 Control 1 Register (ASA12CR1, Address = Bank 0/1, 89h)
Analog Switch Cap Type A Block 21 Control 1 Register (ASA21CR1, Address = Bank 0/1, 95h)
Analog Switch Cap Type A Block 23 Control 1 Register (ASA23CR1, Address = Bank 0/1, 9Dh)

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Analog PSoC Blocks

10.8.3.3

Analog Switch Cap Type A Block xx Control 2 Register

AnalogBus gates the output to the analog column bus.

The output on the analog column bus is affected by the
state of the ClockPhase bit in Control 0 Register
(ASA10CR0, ASA12CR0, ASA21CR0, ASA23CR0). If
AnalogBus is set to 0, the output to the analog column
bus is tri-stated. If AnalogBus is set to 1, the signal that is
output to the analog column bus is selected by the
ClockPhase bit. If the ClockPhase bit is 0, the block output is gated by sampling clock on last part of PHI2. If the
ClockPhase bit is 1, the block output continuously drives
the analog column bus.
CompBus controls the output to the column comparator
bus. Note that if the comparator bus is not driven by anything in the column, it is pulled low. The comparator output is evaluated on the rising edge of internal PHI1 and
is latched so it is available during internal PHI2.
AutoZero controls the shorting of the output to the inverting input of the op-amp. When shorted, the op-amp is
basically a follower. The output is the op-amp offset. By
using the feedback capacitor of the integrator, the block
can memorize the offset and create an offset cancellation scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the op-amp. If AutoZero is enabled, then the pair of
switches is active. AutoZero also affects the function of
the FSW1 bit in Control 3 Register.
The CCap bits set the value of the capacitor in the C
path.

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

91

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 71:

Analog Switch Cap Type A Block xx Control 2 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

AnalogBus

CompBus

AutoZero

CCap[4]

CCap[3]

CCap[2]

CCap[1]

CCap[0]

Bit 7: AnalogBus Enable output to the analog bus

0 = Disable output to analog column bus
1 = Enable output to analog column bus
(The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register
(ASA10CR0, ASA12CR0, ASA21CR0, ASA23CR0). If AnalogBus is set to 0, the output to the analog column bus is
tri-stated. If AnalogBus is set to 1, the signal that is output to the analog column bus is selected by the ClockPhase
bit. If the ClockPhase bit is 0, the block output is gated by sampling clock on last part of PHI2. If the ClockPhase bit
is 1, the block output continuously drives the analog column bus.)
Bit 6: CompBus Enable output to the comparator bus
0 = Disable output to comparator bus
1 = Enable output to comparator bus
Bit 5: AutoZero Bit for controlling gated switches
0 = Shorting switch is not active. Input cap branches shorted to op-amp input
1 = Shorting switch is enabled during internal PHI1. Input cap branches shorted to analog ground during internal
PHI1 and to op-amp input during internal PHI2.
Bit [4:0]: CCap [4:0] Binary encoding for 32 possible capacitor sizes for C Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array

1 0 0 0 0 = 16 Capacitor units in array

1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array

Analog Switch Cap Type A Block 10 Control 2 Register (ASA10CR2, Address = Bank 0/1, 82h)
Analog Switch Cap Type A Block 12 Control 2 Register (ASA12CR2, Address = Bank 0/1, 8Ah)
Analog Switch Cap Type A Block 21 Control 2 Register (ASA21CR2, Address = Bank 0/1, 96h)
Analog Switch Cap Type A Block 23 Control 2 Register (ASA23CR2, Address = Bank 0/1, 9Eh)

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Analog PSoC Blocks

10.8.3.4

Analog Switch Cap Type A Block xx Control 3 Register

ARefMux selects the reference input of the A capacitor

branch.

enabled at all times. If the AutoZero bit is 1, the switch is

enabled only when the internal PHI2 is high.

FSW1 is used to control a switch in the integrator capacitor path. It connects the output of the op-amp to the integrating cap. The state of the switch is affected by the
state of the AutoZero bit in Control 2 Register
(ASA10CR2, ASA12CR2, ASA21CR2, ASA23CR2). If
the FSW1 bit is set to 0, the switch is always disabled. If
the FSW1 bit is set to 1, the AutoZero bit determines the
state of the switch. If the AutoZero bit is 0, the switch is

FSW0 is used to control a switch in the integrator capacitor path. It connects the output of the op-amp to analog
ground.

Table 72:

BMuxSCA controls the muxing to the input of the B

capacitor branch.
Power encoding for selecting 1 of 4 power levels. The
block always powers up in the off state.

Analog Switch Cap Type A Block xx Control 3 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

FSW[1]

FSW[0]

BMuxSCA[1]

BMuxSCA[0]

Power[1]

Power[0]

Bit Name

ARefMux[1] ARefMux[0]

Bit [7:6]: ARefMux [1:0] Encoding for selecting reference input

0 0 = Analog ground is selected
0 1 = REFHI input selected (This is usually the high reference)
1 0 = REFLO input selected (This is usually the low reference)
1 1 = Reference selection is driven by the comparator (When output comparator node is set high, the input is set to
REFHI. When set low, the input is set to REFLO)
Bit 5: FSW1 Bit for controlling gated switches
0 = Switch is disabled
1 = If the FSW1 bit is set to 1, the state of the switch is determined by the AutoZero bit. If the AutoZero bit is 0, the
switch is enabled at all times. If the AutoZero bit is 1, the switch is enabled only when the internal PHI2 is high
Bit 4: FSW0 Bits for controlling gated switches
0 = Switch is disabled
1 = Switch is enabled when PHI1 is high
Bit [3:2] BMuxSCA [1:0] Encoding for selecting B inputs. (Note that the available mux inputs vary by individual
PSoC block.)
ASA21 ASA12 ASA23
ASA10
0 0 = ACA00 ASB11
ACA02 ASB13
0 1 = ASB11 ASB20
ASB13 ASB22
1 0 = P2.3
ASB22
ASB11 P2.0
1 1 = ASB20 TrefGND ASB22 ABUS3
Bit [1:0]: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = 10 A, typical
1 0 = 50 A, typical
1 1 = 200 A, typical
Analog Switch Cap Type A Block 10 Control 3 Register (ASA10CR3, Address = Bank 0/1, 83h)
Analog Switch Cap Type A Block 12 Control 3 Register (ASA12CR3, Address = Bank 0/1, 8Bh)
Analog Switch Cap Type A Block 21 Control 3 Register (ASA21CR3, Address = Bank 0/1, 97h)
Analog Switch Cap Type A Block 23 Control 3 Register (ASA23CR3, Address = Bank 0/1, 9Fh)

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

93

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.9

Analog Switch Cap Type B PSoC Blocks

10.9.1

Introduction

The Analog Switch Cap Type B PSoC blocks are built

around an operational amplifier. There are several analog muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There are also four arrays of unit value
capacitors that are located in the feedback path for the
op-amp, and are switched by two phase clocks, PHI1
and PHI2. These four capacitor arrays are labeled A Cap
Array, B Cap Array, C Cap Array, and F Cap Array. There
is also an analog comparator connected to the output
OUT, which converts analog comparisons into digital signals.
There are three discrete outputs from this block. These
outputs are:
1.

The analog output bus (ABUS), which is an analog

bus resource that is shared by all of the analog
blocks in the analog column for that block.

2.

The comparator bus (CBUS), which is a digital bus

that is a resource that is shared by all of the analog
blocks in a column for that block.

3.

The output bus (OUT), which is an analog bus

resource that is shared by all of the analog blocks in
a column and connects to one of the analog output
buffers, to send a signal externally to the device.

The SCB block also supports Delta-Sigma, Successive

Approximation and Incremental A/D Conversion, Capacitor DACs, and SC filters. It has two input arrays of
switched capacitors, and a Non-Switched capacitor feedback array from the output. When preceded by an SC
Block A Integrator, the combination can be used to provide a full Switched Capacitor Biquad.

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Analog PSoC Blocks

1*AutoZero

FCap
16,32 C

CCap
0..31 C

(2+!AutoZero)
* FSW1

BQTAP

1* FSW0
A Mux

ACap
0..31 C

A Inputs
REFHI
REFLO
AGND

2+AutoZero
1 *
!AutoZero

ARefMux
ASign

OUT

AnalogBus*2B

2 +!BSW

B Inputs

ABUS

BCap
0..31 C

2+!BSW

Power
CompBus
CBUS

1*BSW

BMuxSCB

1*BSW

Figure 26: Analog Switch Cap Type B PSoC Blocks

10.9.2

Registers

10.9.2.1

Analog Switch Cap Type B Block xx Control 0 Register

FCap controls the size of the switched feedback capaci-

ASign controls the switch phasing of the switches on the

tor in the integrator.

bottom plate of the A capacitor. The bottom plate sam-

ClockPhase controls the internal clock phasing relative

ples the input or the reference.

to the input clock phasing. ClockPhase affects the output

The ACap bits set the value of the capacitor in the A

of the analog column bus which is controlled by the

path.

AnalogBus bit in Control 2 Register (ASB11CR2,

ASB13CR2, ASB20CR2, ASB22CR2).
Table 73:

Analog Switch Cap Type B Block xx Control 0 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

FCap

ClockPhase

ASign

ACap[4]

ACap[3]

ACap[2]

ACap[1]

ACap[0]

Bit Name

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

95

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 73:

Analog Switch Cap Type B Block xx Control 0 Register, continued

Bit 7: FCap F Capacitor value selection bit

0 = 16 capacitor units
1 = 32 capacitor units
Bit 6: ClockPhase Clock phase select, will invert clocks internal to the blocks. During normal operation of an SC
block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of
PHI2 (during PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven). This
forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the
output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and
settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the output is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Internal PHI1 = External PHI1
1 = Internal PHI1 = External PHI2
This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved
in the output latching mechanism. The capture of the next value to be output from the latch (capture point event)
happens during the falling edge of one clock phase, and the rising edge of the other clock phase will cause the
value to come out (output point event). This bit determines which clock phase triggers the capture point event, and
the other clock will trigger the output point event. The value output to the comparator bus will remain stable
between output point events.
0 = Capture Point Event triggered by Falling PHI2, Output Point Event triggered by Rising PHI1
1 = Capture Point Event triggered by Falling PHI1, Output Point Event triggered by Rising PHI2
Bit 5: ASign
0 = Input sampled on Internal PHI1, Reference Input sampled on internal PHI2
1 = Input sampled on Internal PHI2, Reference Input sampled on internal PHI1
Bit [4:0]: ACap [4:0] Binary encoding for 32 possible capacitor sizes for A Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array

1 0 0 0 0 = 16 Capacitor units in array

1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array

Analog Switch Cap Type B Block 11 Control 0 Register (ASB11CR0, Address = Bank 0/1, 84h)
Analog Switch Cap Type B Block 13 Control 0 Register (ASB13CR0, Address = Bank 0/1, 8Ch)
Analog Switch Cap Type B Block 20 Control 0 Register (ASB20CR0, Address = Bank 0/1, 90h)
Analog Switch Cap Type B Block 22 Control 0 Register (ASB22CR0, Address = Bank 0/1, 98h)

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Analog PSoC Blocks

10.9.2.2

Analog Switch Cap Type B Block xx Control 1 Register

AMux controls the input muxing for the A capacitor

The BCap bits set the value of the capacitor in the B

branch.

path.

Table 74:

Analog Switch Cap Type B Block xx Control 1 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

AMux[2]

AMux[1]

AMux[0]

BCap[4]

BCap[3]

BCap[2]

BCap[1]

BCap[0]

Bit [7:5]: AMux [2:0] Input muxing select for A capacitor branch. (Note that available mux inputs vary by individual
PSoC block.)
ASB11
0 0 0 = ACA01
0 0 1 = ASA12
0 1 0 = ASA10
0 1 1 = ASA21
1 0 0 = REFHI
1 0 1 = ACA00
1 1 0 = Reserved
1 1 1 = Reserved

ASB13
ACA03
P2.2
ASA12
ASA23
REFHI
ACA02
Reserved
Reserved

ASB20
ASA10
P2.1
ASA21
ABUS0
REFHI
ASB11
Reserved
Reserved

ASB22
ASA12
ASA21
ASA23
ABUS2
REFHI
ASB13
Reserved
Reserved

Bit [4:0]: BCap [4:0] Binary encoding for 32 possible capacitor sizes for B Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array

1 0 0 0 0 = 16 Capacitor units in array

1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array

Analog Switch Cap Type B Block 11 Control 1 Register (ASB11CR1, Address = Bank 0/1, 85h)
Analog Switch Cap Type B Block 13 Control 1 Register (ASB13CR1, Address = Bank 0/1, 8Dh)
Analog Switch Cap Type B Block 20 Control 1 Register (ASB20CR1, Address = Bank 0/1, 91h)
Analog Switch Cap Type B Block 22 Control 1 Register (ASB22CR1, Address = Bank 0/1, 99h)

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

10.9.2.3

Analog Switch Cap Type B Block xx Control 2 Register

AnalogBus gates the output to the analog column bus.

The output on the analog column bus is affected by the
state of the ClockPhase bit in Control 0 Register
(ASB11CR0, ASB13CR0, ASB20CR0, ASB22CR0). If
AnalogBus is set to 0, the output to the analog column
bus is tri-stated. If AnalogBus is set to 1, the ClockPhase
bit selects the signal that is output to the analog-column
bus. If the ClockPhase bit is 0, the block output is gated
by sampling clock on last part of PHI2. If the ClockPhase
bit is 1, the block ClockPhase continuously drives the
analog column bus.
CompBus controls the output to the column comparator
bus. Note that if the comparator bus is not driven by anything in the column, it is pulled low. The comparator output is evaluated on the rising edge of internal PHI1 and
is latched so it is available during internal PHI2.
AutoZero controls the shorting of the output to the inverting input of the op-amp. When shorted, the op-amp is
basically a follower. The output is the op-amp offset. By
using the feedback capacitor of the integrator, the block
can memorize the offset and create an offset cancellation scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the op-amp. If AutoZero is enabled, then the pair of
switches is active. AutoZero also affects the function of
the FSW1 bit in Control 3 Register.
The CCap bits set the value of the capacitor in the C
path.

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Table 75:

Analog Switch Cap Type B Block xx Control 2 Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

AnalogBus

CompBus

AutoZero

CCap[4]

CCap[3]

CCap[2]

CCap[1]

CCap[0]

Bit 7: AnalogBus Enable output to the analog bus

0 = Disable output to analog column bus
1 = Enable output to analog column bus
(The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register
(ASB11CR0, ASB13CR0, ASB20CR0, ASB22CR0). If AnalogBus is set to 0, the output to the analog column bus is
tri-stated. If AnalogBus is set to 1, the ClockPhase bit selects the signal that is output to the analog column bus. If the
ClockPhase bit is 0, the block output is gated by sampling clock on last part of PHI2. If the ClockPhase bit is 1, the
block output continuously drives the analog column bus)
Bit 6: CompBus Enable output to the comparator bus
0 = Disable output to comparator bus
1 = Enable output to comparator bus
Bit 5: AutoZero Bit for controlling gated switches
0 = Shorting switch is not active. Input cap branches shorted to op-amp input
1 = Shorting switch is enabled during internal PHI1. Input cap branches shorted to analog ground during internal
PHI1 and to op-amp input during internal PHI2.
Bit [4:0]: CCap [4:0] Binary encoding for 32 possible capacitor sizes for C Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array

1 0 0 0 0 = 16 Capacitor units in array

1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array

Analog Switch Cap Type B Block 11 Control 2 Register (ASB11CR2, Address = Bank 0/1, 86h)
Analog Switch Cap Type B Block 13 Control 2 Register (ASB13CR2, Address = Bank 0/1, 8Eh)
Analog Switch Cap Type B Block 20 Control 2 Register (ASB20CR2, Address = Bank 0/1, 92h)
Analog Switch Cap Type B Block 22 Control 2 Register (ASB22CR2, Address = Bank 0/1, 9Ah)

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10.9.2.4

Analog Switch Cap Type B Block xx Control 3 Register

FSW0 is used to control a switch in the integrator capacitor path. It connects the output of the op-amp to analog
ground.

ARefMux selects the reference input of the A capacitor

branch.
FSW1 is used to control a switch in the integrator capacitor path. It connects the output of the op-amp to the integrating cap. The state of the switch is affected by the
state of the AutoZero bit in Control 2 Register
(ASB11CR2, ASB13CR2, ASB20CR2, ASB22CR2). If
the FSW1 bit is set to 0, the switch is always disabled. If
the FSW1 bit is set to 1, the AutoZero bit determines the
state of the switch. If the AutoZero bit is 0, the switch is
enabled at all times. If the AutoZero bit is 1, the switch is
enabled only when the internal PHI2 is high.
Table 76:
Bit #
POR
Read/
Write
Bit Name

BSW is used to control switching in the B branch. If disabled, the B capacitor branch is a continuous time
branch like the C branch of the SC A Block. If enabled,
then on internal PHI1, both ends of the cap are switched
to analog ground. On internal PHI2, one end is switched
to the B input and the other end is switched to the summing node.
BMuxSCB controls muxing to the input of the B capacitor
branch. The B branch can be switched or unswitched.

Analog Switch Cap Type B Block xx Control 3 Register

7
0

6
0

5
0

4
0

3
0

2
0

1
0

0
0

RW

RW

RW

RW

RW

RW

RW

RW

FSW[1]

FSW[0]

BSW

BMuxSCB

Power[1]

Power[0]

ARefMux[1] ARefMux[0]

Bit [7:6]: ARefMux [1:0] Encoding for selecting reference input

0 0 = Analog ground is selected
0 1 = REFHI input selected (This is usually the high reference)
1 0 = REFLO input selected (This is usually the low reference)
1 1 = Reference selection is driven by the comparator (When output comparator node is set high, the input is set to
REFHI. When set low, the input is set to REFLO)
Bit 5: FSW1 Bit for controlling gated switches
0 = Switch is disabled
FSW1 bit is set to 1; the state of the switch is determined by the AutoZero bit. If the AutoZero bit is 0, the switch is
enabled at all times. If the AutoZero bit is 1, the switch is enabled only when the internal PHI2 is high
Bit 4: FSW0 Bits for controlling gated switches
0 = Switch is disabled
1 = Switch is enabled when PHI1 is high
Bit 3: BSW Enable switching in branch
0 = B branch is a continuous time path
1 = B branch is switched with internal PHI2 sampling
Bit 2: BMuxSCB Encoding for selecting B inputs. (Note that the available mux inputs vary by individual PSoC block)
ASB11 ASB13 ASB20 ASB22
0 = ACA00 ACA02 ASA11 ASA13
1 = ACA01 ACA03 ASB10 ASB12
Bit [1:0]: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = 10 A, typical
1 0 = 50 A, typical
1 1 = 200 A, typical
Analog Switch Cap Type B Block 11 Control 3 Register (ASB11CR3, Address = Bank 0/1, 87h)
Analog Switch Cap Type B Block 13 Control 3 Register (ASB13CR3, Address = Bank 0/1, 8Fh)
Analog Switch Cap Type B Block 20 Control 3 Register (ASB20CR3, Address = Bank 0/1, 93h)
Analog Switch Cap Type B Block 22 Control 3 Register (ASB22CR3, Address = Bank 0/1, 9Bh)

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Analog PSoC Blocks

10.10 Analog Comparator Bus

Each analog column has a dedicated comparator bus

The output from the analog block that is actively driving

associated with it. Every analog PSoC block has a com-

the bus may also be latched internal to the analog block

parator output that can drive out on this bus, but the

itself.

comparator output from only one analog block in a col-

In the Continuous Time analog blocks, the CPhase and

umn can be actively driving the comparator bus for that

CLatch bits inside the Analog Continuous Time Type A

column at any one time. The output on the comparator

Block xx Control Register 2 determine whether the out-

bus can drive into the digital blocks, and is also available

put signal on the comparator bus is latched inside the

to be read in the Analog Comparator Control Register

block, and if it is, which clock phase it is latched on.

(CMP_CR, Address = Bank 0,64H).

In the Switched Capacitor analog blocks, the output on

The comparator bus is latched before it is available to

the comparator bus is always latched. The ClockPhase

either drive the digital blocks, or be read in the Analog

bit in the Analog SwitchCap Type A Block xx Control

Comparator Control Register. The latch for each compar-

Register 0 or the Analog SwitchCap Type B Block xx

ator bus is transparent (the output tracks the input) dur-

Control Register 0 determines the phase on which this

ing the high period of PHI2. During the low period of

data is latched and available.

PHI2 the latch retains the value on the comparator bus

during the high to low transition of PHI2.
Table 77:

Analog Comparator Control Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

Bit Name

COMP 3

COMP 2

COMP 1

COMP 0

AINT 3

AINT 2

AINT 1

AINT 0

Bit 7: COMP 3 COMP 3 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 6: COMP 2 COMP 2 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 5: COMP 1 COMP 1 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 4: COMP 0 COMP 0 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 3: AINT 3 AINT 3 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 2: AINT 2 AINT 2 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 1: AINT 1 AINT 1 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 0: AINT 0 AINT 0 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
0 = Comparator bus
1 = PHI2 (Falling edge of PHI2 causes an interrupt)
Analog Comparator Control Register (CMP_CR, Address = Bank 0, 64h)

10.11 Analog Synchronization

For high precision analog operation, it may be necessary

(CMP_CR) are another way to address it with interrupts.)

to precisely time when updated register values are avail-

When the SYNCEN bit is set, a subsequent write instruc-

able to the analog PSOC blocks. The optimum time to

tion to any register in a Switch Cap block will cause the

update values in Switch Cap registers is at the beginning

CPU to stall until the rising edge of PHI1. This mode is in

of the PHI1 active period. The SYNCEN bit in the Analog

effect until the SYNCEN bit is cleared.

Synchronization Control Register is designed to address

this. (The AINT bits of the Analog Comparator Register

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

The SAR hardware accelerator is a block of specialized

ware accelerator. The DAC and SAR User Modules

hardware designed to sequence the SAR algorithm for

operate in this mode. The analog column clock fre-

efficient A/D conversion. A SAR ADC is implemented

quency must not be a power of two multiple (2, 4, 8...)

conceptually with a DAC of the desired precision, and a

higher than the CPU clock frequency. Under this condi-

comparator. This functionality can be configured from

tion, the CPU will never recover from a stall.

one or more PSoC blocks. For each conversion, the firm-

See the list of relationships (in MHz) that will fail:

ware should initialize the ASY_CR register as defined

Table 78:

below, and set the sign bit of the DAC as the first guess
in the algorithm. A sequence of OR instructions (Read,

Analog Frequency Relationships

Analog Column Clock

CPU Clock

Modify, Write) to the DAC (CR0) register is then exe-

3.

1.5, 0.75, .018, 0.093

cuted. Each of these OR instructions causes the SAR

1.5

0.75, 0.18, 0.093

0.75

0.18, 0.093

0.37

0.18, 0.093

0.18

0.093

hardware to read the current state of the comparator,

checking the validity of the previous guess. It either
clears it or leaves it set, accordingly. The next LSB in the
DAC register is also set as the next guess. Six OR
instructions will complete the conversion of a 6-bit DAC.

You can still run the CPU clock slower than the column

The resulting DAC code, which matches the input volt-

clock if the relationship is not a power of two multiple.

age to within 1 LSB, is then read back from the DAC

For example, you can run at 0.6 MHz, which is not a

CR0 register.

power of two multiple of any CPU frequency and therefore any CPU frequency can be selected. If the CPU fre-

10.11.1 Analog Stall and Analog Stall Lockup

quency is greater than or equal to the analog column

Stall lockup affects the operation of stalled IO writes,

clock, there is not a problem.

such as DAC writes and the stalled IOR of the SAR hardTable 79:

Analog Synchronization Control Register

Bit #

POR

Read/
Write

--

RW

RW

RW

RW

Bit Name

Reserved

SARCOUNT
[2]

SARCOUNT
[1]

SARCOUNT
[0]

SARSIGN

SARCOL
[1]

SARCOL
[0]

SYNCEN

Bit 7: Reserved
Bit [6:4]: SARCOUNT [2:0] Initial SAR count. Load this field with the number of bits to process. In a typical 6-bit
SAR, the value would be 6
Bit 3: SARSIGN Adjust the SAR comparator based on the type of block addressed. In a DAC configuration with
more than one PSoC block (more than 6-bits), this bit would be 0 when processing the most significant block and 1
when processing the least significant block. This is because the least significant block of a DAC is an inverting input
to the most significant block
Bit [2:1]: SARCOL [1:0] Column select for SAR comparator input. The DAC portion of the SAR can reside in any of
the appropriate positions in the analog PSOC block array. However, once the comparator block is positioned (and it
is possible to have the DAC and comparator in the same block), this should be the column selected
Bit 0: SYNCEN Set to 1, will stall the CPU until the rising edge of PHI1, if a write to a register within an analog Switch
Cap block takes place
Analog Synchronization Control Register (ASY_CR, Address = Bank 0, 65h)

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Analog PSoC Blocks

10.12 Analog I/O

10.12.1

Analog Input Muxing

MUX

ACM1

AC0

BUF

AC1

MUX

ACI2

ACM2

ACol1Mux

P0[6]

MUX

ACI1

P0[4]

MUX
ACM0

P0[2]

P0[0]

P0[7]

P0[5]

P0[3]

P0[1]
ACI0

ACI3

ACM3

ACol2Mux

BUF

AC2

BUF

AC3

ACA00

ACA01

ACA02

ACA03

P2[3]

ASA10

ASB11

ASA12

ASB13

P2[1]

ASB20

ASA21

ASB22

ASA23

BUF

P2[2]

P2[0]

Figure 27: Analog Input Muxing

10.12.2 Analog Input Select Register
This register controls the analog muxes that feed signals
in from port pins into each Analog Column. Each of the
Analog Columns can have up to four port bits connected
to its muxed input. Analog Columns 01 and 02 (ACI1 and
ACI2) have additional muxes that allow selection
between separate column multiplexers (see Analog Input
Muxing diagram above). The AC1Mux and AC2Mux bit
fields control the bits for those muxes and are located in
the Analog Output Buffer Control Register (ABF_CR).
There are four additional analog inputs that go directly
into the Switch Capacitor PSoC blocks.

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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 80:

Analog Input Select Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

ACI3 [1]

ACI3 [0]

ACI2 [1]

ACI2 [0]

ACI1 [1]

ACI1 [0]

ACI0 [1]

ACI0 [0]

Bit [7:6]: ACI3 [1:0]

0 0 = ACM3 P0[0]
0 1 = ACM3 P0[2]
1 0 = ACM3 P0[4]
1 1 = ACM3 P0[6]
Bit [5:4]: ACI2 [1:0]
0 0 = ACM2 P0[1]
0 1 = ACM2 P0[3]
1 0 = ACM2 P0[5]
1 1 = ACM2 P0[7]
ACol2Mux (ABF_CR, Address = Bank1, 62h)
0 = AC2 = ACM2
1 = AC2 = ACM3
Bit [3:2]: ACI1 [1:0]
0 0 = ACM1 P0[0]
0 1 = ACM1 P0[2]
1 0 = ACM1 P0[4]
1 1 = ACM1 P0[6]
ACol1Mux (ABF_CR, Address = Bank1, 62h)
0 = AC1 = ACM1
1 = AC1 = ACM0
Bit [1:0]: ACI0 [1:0]
0 0 = ACM0 P0[1]
0 1 = ACM0 P0[3]
1 0 = ACM0 P0[5]
1 1 = ACM0 P0[7]
Analog Input Select Register (AMX_IN, Address = Bank 0, 60h)

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Analog PSoC Blocks

10.12.3

Analog Output Buffers

The user has the option to output up to four analog sig-

Column. The enable bits for the analog output buffers

nals on the pins of the device. This is done by enabling

are contained in the Analog Output Buffer Control Regis-

the analog output buffers associated with each Analog

ter (ABF_CR).

P0[3]
P0[5]
P0[4]
P0[2]

ACA 00

ACA 01

ACA 02

ACA 03

ASA 10

ASB 11

ASA 12

ASB 13

ASB 20

ASA 21

ASB 22

ASA 23

Figure 28: Analog Output Buffers

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10.12.4 Analog Output Buffer Control Register

Table 81:

Analog Output Buffer Control Register

Bit #

POR

Read/
Write

--

Bit Name

ACol1Mux

ACol2Mux

ABUF1EN

ABUF2EN

ABUF0EN

ABUF3EN

Reserved

PWR

Bit 7: ACol1Mux
0 = Set column 1 input to column 1 input mux output
1 = Set column 1 input to column 0 input mux output
Bit 6: ACol2Mux
0 = Set column 2 input to column 2 input mux output
1 = Set column 2 input to column 3 input mux output
Bit 5: ABUF1EN Enables the analog output buffer for Analog Column 1 (Pin P0[5])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 4: ABUF2EN Enables the analog output buffer for Analog Column 2 (Pin P0[4])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 3: ABUF0EN Enables the analog output buffer for Analog Column 0 (Pin P0[3])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 2: ABUF3EN Enables the analog output buffer for Analog Column 3 (Pin P0[2])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit [1]: Reserved Must be left as 0
Bit [0]: PWR Determines power level of all output buffers
0 = Low output power
1 = High output power
Analog Output Buffer Control Register (ABF_CR, Address = Bank 1, 62h)

10.13 Analog Modulator

The user has the capability to use the Analog Switch
Cap Type A PSoC Blocks in Columns 0 and 2 as amplitude modulators. The Analog Modulator Control Register
(AMD_CR) allows the user to select the appropriate
modulating signal. When the modulating signal is low,
the polarity follows the setting of the ASign bit set in the
Analog Switch Cap Type A Control 0 Register
(ASAxxCR0). When this signal is high, the normal gain
polarity of the PSoC block is inverted.

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Analog PSoC Blocks

Table 82:

Analog Modulator Control Register

Bit #

POR

Read/
Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Reserved

Reserved

Reserved

Reserved

AMOD2[1]

AMOD2[0]

AMOD0[1]

AMOD0[0]

Bit 7: Reserved
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit [3:2]: AMOD2[1], AMOD2[0] Selects the modulation signal for Analog Column 2
0 0 = No Modulation
0 1 = Global Output [0]
1 0 = Global Output [4]
1 1 = Digital Basic Type A Block 03
Bit [1:0]: AMOD0[1], AMOD0[0] Selects the modulation signal for Analog Column 0
0 0 = No Modulation
0 1 = Global Output [0]
1 0 = Global Output [4]
1 1 = Digital Basic Type A Block 03
Analog Modulator Control Register (AMD_CR, Address = Bank 1, 63h)

10.14 Analog PSoC Block Functionality

Amplitude Modulators

The analog PSoC blocks can be used to implement a

Amplitude Demodulators

wide range of functions, limited only by the designers

Sine-Wave Generators

capability of the analog PSoC blocks using one analog

Sine-Wave Detectors

PSoC block, multiple analog blocks, a combination of

Sideband Detection

more than one type of analog block, or a combination of

Sideband Stripping

are currently available as User Modules in PSoC

Audio Output Drive

Designer. Others will be added in the future.

DTMF Generator

FSK Modulator

imagination. The following functions operate within the

analog and digital PSoC blocks. Most of these functions

Delta-Sigma A/D Converters

Successive Approximation A/D Converters

Incremental A/D Converters

Programmable Gain/Loss Stage

Analog Comparators

Zero-Crossing Detectors

Low-Pass Filter

Band-Pass Filter

Notch Filter

August 18, 2003

By modifying registers, as described in this Data Sheet,

users can configure PSoC blocks to perform these functions and more.

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10.15 Temperature Sensing Capability

A temperature-sensitive voltage derived from the Band
Gap sensing on the die is buffered and available as an
analog input into the Analog Switch Cap Type A Block
ASA21. Temperature sensing allows protection of device
operating ranges for fail-safe applications. Temperature
sensing combined with a long sleep timer interval (to
allow the die to approximate ambient temperature) can
give an approximate ambient temperature for data acquisition and battery charging applications. The user may
also calibrate the internal temperature rise based on a
known current consumption.
The temperature sensor input to the ASA21 block is
labeled VTemp, and its associated ground reference is
labeled TRefGND (see Figure 22:, Figure 24:).

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Special Features of the CPU

11.0

Special Features of the CPU

11.1

Multiplier/Accumulator

A fast, on-chip signed 2s complement MAC (Multiply/

An extra instruction must be inserted between the follow-

Accumulate) function is provided to assist the main CPU

ing sequences of MAC operations to provide extra delay.

with digital signal processing applications. Multiply

If this is not done, the Accumulator results will be inaccu-

results, as well as the lower 2 bytes of the Accumulator,

rate.

are available immediately after the input registers are

written. The upper 2 bytes require a single instruction
delay before reading. The MAC function is tied directly
on the internal data bus, and is mapped into the register
space. The following MAC block diagram provides data

a.

Two MAC instructions in succession:

mov reg[MAC_X],a
nop //add nop or any other instruction
mov reg[MAC_X],a

flow information. The user has the choice to either cause

a multiply/accumulate function to take place, or a multiply only function. The user selects which operation is
performed by the choice of input register. The multiply
function occurs immediately whenever the MUL_X or the
MUL_Y multiplier input registers are written, and the
result is available in the MUL_DH and MUL_DL multiplier
result registers. The Multiply/Accumulate function is executed whenever there is a write to the MAC_X or the

For sequence a., there is no workaround, the nop or

other instruction must be inserted.
b.

A MAC instruction followed by a read of the

most significant Accumulator bytes:

mov reg[MAC_X],a
nop //add nop or any other instruction
mov a,[ACC_DR2] // or ACC_DR3

MAC_Y Multiply/Accumulate input registers, and the

result is available in the ACC_DR3, ACC_DR2,
ACC_DR1, and ACC_DR0 accumulator result registers.
A write to MUL_X or MAC_X is input as the X value to
both the multiply and Multiply/Accumulate functions. A
write to MUL_Y or MAC_Y is input as the Y value to both
the multiply and Multiply/Accumulate functions. A write to
the MAC_CL0 or MAC_CL1 registers will clear the value
in the four accumulate registers.

For sequence b., the least significant Accumulator bytes

(ACC_DR0, ACC_DR1) may be reliably read directly
after the MAC instruction.
Writing to the multiplier registers (MUL_X, MUL_Y), and
reading the result back from the multiplier product registers (MUL_DH, MUL_DL), is not affected by this problem
and does not have any restrictions.

Operation of the Multiply/Accumulate function relies on

proper multiplicand input. The first value of each multiplicand must be placed into MUL_X (or MUL_Y) register to
avoid causing a Multiply/Accumulate to occur. The second multiplicand must be placed into MAC_Y (or
MAC_X) thereby triggering the Multiply/Accumulate
function.
MUL_X, MUL_Y, MAC_X, and MAC_Y are 8-bit signed
input registers. MUL_DL and MUL_DH form a 16-bit
signed output. ACC_DR0, ACC_DR1, ACC_DR2 and
ACC_DR3 form a 32-bit signed output.

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MUL_DH
MUL_DL
MUL_X or MAC_X
A CC_DR3
MULTIPLIER

Z out, 16 BIT
16 BIT

A CC_DR2

32-BIT
ACCUMULATOR

MUL_Y or MAC_Y

To
Internal
System
Bus

A CC_DR1
A CC_DR0

32-BIT ACC

MAC_CL1
MAC_CL0

Figure 29: Multiply/Accumulate Block Diagram

Table 83:

Multiply Input X Register

Bit #

POR

Read/Write

Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] 8-bit data is the input value for X multiplier
Multiply Input X Register (MUL_X, Address = Bank 0, E8h)
Table 84:

Multiply Input Y Register

Bit #

POR

Read/Write

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] 8-bit data is the input value for Y multiplier
Multiply Input Y Register (MUL_Y, Address = Bank 0, E9h)

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Special Features of the CPU

Table 85:

Multiply Result High Register

Bit #

POR

Read/Write

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] 8-bit data value is the high order result of the multiply function
Multiply Result High Register (MUL_DH, Address = Bank 0, EAh)
Table 86:

Multiply Result Low Register

Bit #

POR

Read/Write

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] 8-bit data value is the low order result of the multiply function
Multiply Result Low Register (MUL_DL, Address = Bank 0, EBh)
Table 87:

Accumulator Result 1 / Multiply/Accumulator Input X Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

8-bit data value when read is the next to lowest order result of the multiply/accumulate function
8-bit data value when written is the X multiplier input to the multiply/accumulate function
Accumulator Result 1 / Multiply/Accumulator Input X Register (ACC_DR1 / MAC_X, Address = Bank 0, ECh)
Table 88:

Accumulator Result 0 / Multiply/Accumulator Input Y Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

8-bit data value when read is the lowest order result of the multiply/accumulate function
8-bit data value when written is the Y multiplier input to the multiply/accumulate function
Accumulator Result 0 / Multiply/Accumulator Input Y Register (ACC_DR0 / MAC_Y, Address = Bank 0, EDh)

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Table 89:

Accumulator Result 3 / Multiply/Accumulator Clear 0 Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

8-bit data value when read is the highest order result of the multiply/accumulate function
Any 8-bit data value when written will cause all four Accumulator result registers to clear
Accumulator Result 3 / Multiply/Accumulator Clear 0 Register (ACC_DR3 / MAC_CL0, Address = Bank 0, EEh)
Table 90:

Accumulator Result 2 / Multiply/Accumulator Clear 1 Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

8-bit data value when read is next to highest order result of the multiply/accumulate function
Any 8-bit data value when written will cause all four Accumulator result registers to clear
Accumulator Result 2 / Multiply/Accumulator Clear 1 Register (ACC_DR2 / MAC_CL1, Address = Bank 0, EFh)

11.2

Decimator

The output of a modulator is a high-speed, single bit

A divide by n decimator is a digital filter that takes the

A/D converter. A single bit A/D converter is of little use to

single bit data at a fast rate and outputs multiple bits at

anyone and must be converted to a lower speed multiple

one nth the speed. For a single stage converter, the

bit output. Converting this high-speed single bit data

optimal filter has a sinc2 response. This filter can be

stream to a lower speed multiple bit data stream requires

implemented as a finite impulse response (FIR) filter and

a data decimator.

for a divide by n implementation should have the following coefficients:

Coeff
n

0
0

n-1

2n-1

Figure 30: Decimator Coefficients

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Special Features of the CPU

This filter is implemented using a combination of hard-

is used to process the lower speed, enhanced resolution

ware and software resources. Hardware is used to accu-

data for output.

mulate the high-speed in-coming data while the software

Table 91:

Decimator/Incremental Control Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

IGEN [3]

IGEN [2]

IGEN [1]

IGEN [0]

ICCKSEL

DCol [1]

DCol [0]

DCLKSEL

Bit [7:4]: IGEN [3:0] Individual enables for each analog column that gates the Analog Comparator based on the
ICCKSEL input (Bit 3)
Bit 3: ICCKSEL Clock select for Incremental gate function
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Bit [2:1]: DCol [1:0] Selects Analog Column Comparator source
0 0 = Analog Column Comparator 0
0 1 = Analog Column Comparator 1
1 0 = Analog Column Comparator 2
1 1 = Analog Column Comparator 3
Bit 0: DCLKSEL Clock select for Decimator latch
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Decimator Incremental Register (DEC_CR, Address = Bank 0, E6h)
Table 92:

Decimator Data High Register

Bit #

POR

Read/Write

RW

RW

RW

RW

RW

RW

RW

RW

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

8-bit data value when read is the high order byte within the 16-bit decimator data registers
Any 8-bit data value when written will cause both the Decimator Data High (DEC_DH) and Decimator Data Low
(DEC_DL) registers to be cleared
Decimator High Register (DEC_DH / DEC_CL, Address = Bank 0, E4h)
Table 93:

Decimator Data Low Register

Bit #

POR

Read/Write

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0]

8-bit data value when read is the low order byte within the 16 bit decimator data registers
Decimator Data Low Register (DEC_DL, Address = Bank 0, E5h)

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11.3

Reset

11.3.1 Overview

tively. The firmware can interrogate these bits to determine the cause of a reset.

The microcontroller supports two types of resets. When

reset is initiated, all registers are restored to their default

The microcontroller resumes execution from ROM

states and all interrupts are disabled.

address 0x0000 after a reset. The internal clocking mode

is active after a reset, until changed by user firmware. In

Reset Types: Power On Reset (POR), External Reset

addition, the Sleep / Watchdog Timer is reset to its mini-

(Xres), and Watchdog Reset (WDR).

mum interval count.

The occurrence of a reset is recorded in the Status and

Important: The CPU clock defaults to divide by 8 mode

Control Register (CPU_SCR). Bits within this register

at POR to guarantee operation at the low Vcc that might

record the occurrence of POR and WDR Reset respec-

Table 94:

be present during the supply ramp.

Processor Status and Control Register

Bit #

POR

Read/
Write

--

R/C1

R/C1

RW

--

--

RW

Bit Name

IES

Reserved

WDRS

PORS

Sleep

Reserved

Reserved

Stop

Bit 7: IES Global interrupt enable status from CPU Flag register
0 = Global interrupts disabled
1 = Global interrupts enabled
Bit 6: Reserved
Bit 5: WDRS
WDRS is set by the CPU to indicate that a Watchdog Reset event has occurred. The user can read this bit to determine the type of reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
Bit 4: PORS
PORS is set by the CPU to indicate that a Power On Reset event has occurred. The user can read this bit to determine the type of reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared)
Bit 3: Sleep Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending
0 = Normal operation
1 = Sleep
Bit 2: Reserved
Bit 1: Reserved
Bit 0: Stop Set by the user to halt the CPU. The CPU will remain halted until a reset (WDR or POR) has taken place
0 = Normal CPU operation
1 = CPU is halted (not recommended)
1.

C = Clear

Status and Control Register (CPU_SCR, Address = Bank 0/1, FFh)

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Special Features of the CPU

11.3.2

Power On Reset (POR)

Power On Reset (POR) occurs every time the power to

trip, before CPU operation begins. If the Vcc voltage

the device is switched on. POR is released when the

drops below the POR downward supply trip point (2.1V

supply is typically 2.2V +/-12% for the upward supply

+/-12%, once the internal reference is established), POR

transition, with typically 120mV of hysterisis during the

is reasserted.

power on transient. Bit 4 of the Status and Control Register (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR,
the microprocessor is suspended for 64 ms. This pro-

Important: The PORS status bit is set at POR and can

only be cleared by the user, and cannot be set by firmware.

vides time for the Vcc supply to stabilize after the POR

11.3.3

Execution Reset

The following diagram illustrates the sequence of events

the time between beginning boot calibration and reset

(in time) for execution reset, from voltage stabilization on

vector. At reset vector, the boot.asm must execute

through execution of users code. Once voltage trips

before user code begins running. (boot.asm contains

POR and after 64 ms, the CPU starts boot calibration.

device configurations from PSoC Designer. The time it

Boot calibration takes 2,502 cycles, with the CPU run-

takes boot.asm to execute varies depending on device

ning at 3 MHz. This results in approximately 800 s for

configuration settings such as CPU speed.)

TrVdd

3.0V (Good)
Vcc Power
3.0 - 5.5

POR 2.2V 12%

64 ms
2502 ~
Boot
Calibration

Reset
Vector

Start CPU
3 MHz

boot.asm
User Code

Figure 31: Execution Reset

11.3.4 External Reset (Xres)

The only exception to this is if a POR event takes place,

Pulling the Xres pin high for a minimum of 10 S forces

which will disable the WDT.

the microcontroller to perform a Power On Reset (POR).

The sleep timer is used to generate the sleep time period

The Xres pin does not require a pull-down resistor for

and the watchdog time period. The sleep timer divides

operation and can be tied directly to ground, or left open.

down the 32K system clock, and thereby produces the

11.3.5 Watchdog Timer Reset (WDR)

period to be one of 4 multiples of the period of the 32K

The user has the option to enable the WDT. The WDT is
enabled by clearing the PORS bit. Once the PORS bit is
cleared, the Watchdog Timer (WDT) cannot be disabled.

August 18, 2003

sleep time period. The user can program the sleep time
clock. When the sleep time elapses (sleep timer overflows), an interrupt to the Sleep Timer Interrupt Vector
will be generated.

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The Watchdog Timer period is automatically set to be 3

This timer chain is also used to time the startup for the

counts of the Sleep Timer overflows. This represents

external 32 kHz crystal oscillator. When selecting the

between two and three sleep intervals depending on the

external 32 kHz oscillator, a value of 1 second must be

count in the Sleep Timer at the previous WDT clear.

selected as the sleep interval. When the sleep interrupt

When this timer reaches 3, a WDR is generated.

occurs, the 32 kHz oscillator source will switch from

internal to the crystal. The device does not have to be

The user can either clear the WDT, or the WDT and the

put into sleep for this event to occur. Note that if too short

Sleep Timer. Whenever the user writes to the Reset

of a sleep interval is given, the crystal oscillator will not

WDT Register (RES_WDT), the WDT will be cleared. If

be stable prior to switch over and the results will be

the data that is written is the hex value 38H, the Sleep

unpredictable.

Timer will also be cleared at the same time.

Table 95:

Reset WDT Register

Bit #

POR

Read/Write

Bit Name

Data [7]

Data [6]

Data [5]

Data [4]

Data [3]

Data [2]

Data [1]

Data [0]

Bit [7:0]: Data [7:0] Any write to this register will clear Watchdog Timer, a write of 38h will also clear the Sleep Timer

Reset WDT Register (RES_WDT, Address = Bank 0, E3h)

11.4

Sleep States

There are three sleep states that can be used to lower

enable bits within each analog PSoC block. Setting the

the overall power consumption on the device. The three

Analog Array Power Control bits will restore the function

states are CPU Sleep, Analog Sleep, and Full Sleep.

to those analog PSoC blocks that were previously in use.

The CPU can only be put to sleep by the firmware. This

is accomplished by setting the Sleep Bit in the Status
and Control Register (CPU_SCR). This stops the CPU

The user should take into account the required settling

time after an analog PSoC block is enabled before it will
provide the maximum precision.

from executing instructions, and the CPU will remain

For greatest power savings, the user should put the

asleep until an interrupt comes pending, or there is a

device in the Full Sleep state. This is accomplished by

reset event (either a Power On Reset, or a Watchdog

first transitioning to the Analog Sleep state, and then set-

Timer Reset). While in the CPU Sleep state, all clocking

ting the Sleep Bit in the CPU_SCR Register to the Full

signals derived from the Internal Main Oscillator are

Sleep state. The CPU will be stopped at this point, and

inactivated, including the 48M, 24M, 24V1, and 24V2

either an interrupt or reset event is required to transition

system clocking signals. The Internal Low Speed Oscilla-

back to the Analog Sleep state.

tor will continue to operate during the CPU Sleep state.

The function of any analog or digital PSoC block that is
clocked from these system-clocking signals will stop during the CPU Sleep state.

The Voltage Reference and Supply Voltage Monitor drop

into (fully functional) power-reduced states. All interrupts
remain active. The Internal Low Speed Oscillator
remains running (it will however drop into a less accu-

The user can also put all the analog PSoC block circuits

rate, low-power state). If enabled, the External Crystal

to sleep. This is accomplished by resetting the Analog

Oscillator will continue running throughout sleep (the

Array Power Control bits in the Analog Reference Con-

Internal Low Speed Oscillator is disabled if the External

trol Register (ARF_CR), which overrides the individual

Crystal Oscillator is selected). Only the occurrence of an

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Special Features of the CPU

interrupt will wake the part from sleep. The Stop bit in the
Status and Control Register (CPU_SCR) must be
cleared for a part to resume out of sleep.

CPU Running

Any digital PSoC block that is clocked by a System Clock

other than the 32K system-clocking signal or external
pins will be stopped, as these clocks do not run in sleep

Run

Analog
Sleep

CPU Sleep

Full Sleep

mode.
The Internal Main Oscillator restarts immediately on exiting either the Full Sleep or CPU Sleep modes. Analog
functions must be re-enabled by firmware. If the External
Crystal Oscillator is used and the internal PLL is
enabled, the PLL will take many cycles to change from
its initial 2.5% accuracy to track that of the External Crystal Oscillator. If the PLL is enabled, there will be a 30s
(one full 32K cycle) delay hold-off time for the CPU to let
the VCO and PLL stabilize. If the PLL is not enabled, the
hold-off time is one half of the 32K cycle. For further

CPU not Running

Figure 32: Three Sleep States

details on PLL, see 7.0.

The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintaining very low average power consumption. The sleep
interrupt may also be used to provide periodic interrupts
during non-sleep modes.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is maintained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leakage to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is compared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.

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11.5

Supply Voltage Monitor

The Supply Voltage Monitor detector generates an inter-

Control Register (VLT_CR). These bits also select the

rupt whenever Vcc drops below a pre-programmed

Switch Mode Pump trip points. The Supply Voltage Mon-

value. There are eight voltage trip points that are select-

itor will remain active when the device enters sleep

able by setting the VM [2:0] bit in the Voltage Monitor

mode.

Table 96:

Voltage Monitor Control Register

Bit #

POR

Read/
Write

--

--

--

--

Bit Name

SMP

Reserved

Reserved

Reserved

Reserved

VM [2]

VM [1]

VM [0]

Bit 7: SMP Disables SMP function

0 = Switch Mode Pump enabled, default
1 = Switch Mode Pump disabled
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit 3: Reserved
Bit [2:0]: VM [2:0]
Low Voltage Detection
0 0 0 = 2.95 Trip Voltage1
0 0 1 = 3.02 Trip Voltage
0 1 0 = 3.17 Trip Voltage
0 1 1 = 3.71 Trip Voltage
1 0 0 = 4.00 Trip Voltage
1 0 1 = 4.48 Trip Voltage
1 1 0 = 4.56 Trip Voltage
1 1 1 = 4.64 Trip Voltage
1.

Switch Mode Pump

0 0 0 = 3.17 Trip Voltage
0 0 1 = 3.25 Trip Voltage
0 1 0 = 3.42 Trip Voltage
0 1 1 = 3.94 Trip Voltage
1 0 0 = 4.19 Trip Voltage
1 0 1 = 4.64 Trip Voltage
1 1 0 = 4.82 Trip Voltage
1 1 1 = 5.00 Trip Voltage

Voltages are ideal typical values. Tolerances are in Table 104 on page 129.

Voltage Monitor Control Register (VLT_CR, Address = Bank 1, E3h)

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Special Features of the CPU

11.6

Switch Mode Pump

This feature is available on the CY8C26xxx versions

up and boot sequence, firmware can disable the SMP

within this family. During the time Vcc is ramping from 0

function by writing Voltage Monitor Control Register

Volts to POR Vtrip (2.2V +/- 12%), IC operation is held off

(VLT_CR) bit 7 to a 1.

by the POR circuit and the Switch Mode Pump is

enabled. The pump is realized by connecting an external
inductor between the battery voltage and SMP, with an
external diode pointing from SMP to the Vcc pin (which
must have a bypass capacitance of at least 0.1uF connected to Vcc). This circuitry will pump Vcc to the Switch
Mode Pump value specified in the Voltage Monitor Control Register (VLT_CR), shown above. Battery voltage
values down to 0.9 V during operation are supported, but
this circuitry is not guaranteed to start for battery volt-

Battery Voltage

ages below 1.2 V. Once the IC is enabled after its power

VCC

When the IC is put into sleep mode, the power supply

pump will remain running to maintain voltage. This may
result in higher than specification sleep current depending upon application. If the user desires, the pump may
be disabled during precision measurements (such as A/
D conversions) and then re-enabled (writing B7 to 1 and
then back to 0 again). The user, however, is responsible
for making the operation happen quickly enough to guarantee supply holdup (by the bypass capacitor) sufficient
for continued operation.

Power For All Circuitry

SMP
SMP
Control
Logic

SMP Reset
X

RST

Reset

To Rest Of
Circuitry

Figure 33: Switch Mode Pump

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11.7

Internal Voltage Reference

An internal bandgap voltage reference source is pro-

operation. The 5.0V value is loaded in the BDG_TR reg-

vided on-chip. This reference is used for the Supply Volt-

ister upon reset. This register must be adjusted when

age Monitor, and can also be accessed by the user as a

operating voltage outside the range for which factory cal-

reference voltage for analog operations. There is a

ibration was set. Changing the factory-programmed trim

Bandgap Oscillator Trim Register (BDG_TR) used to cal-

value is done using the Table Read Supervisor Call rou-

ibrate this reference into specified tolerance. Factory-

tine, and is documented in 11.8.

programmed trim values are available for 5.0V and 3.3V

Table 97:

Bandgap Trim Register

Bit #

POR

FS1

FS1

FS1

FS1

FS1

FS1

FS1

FS1

Read/Write

Bit Name

FMRD

BGT[2]

BGT[1]

BGT[0]

BGO[3]

BGO[2]

BGO[1]

BGO[0]

Bit 7: FMRD
0 = Enable voltage divider between BG and Flash (User must not use other than this setting)
1 = Disable voltage divider between BG and Flash (Test purposes only)
Bit [6:4]: BGT [2:0] Provides Temperature Curve compensation
Bit [3:0]: BGO [3:0] Provides +/- 5% Offset Trim to center Vbg to 1.30V
1.

FS = Factory set trim value

Bandgap Trim Register (BDG_TR, Address = Bank 1, EAh)

11.8

Supervisor ROM/System Supervisor Call Instruction

The parts in this family have a Supervisor ROM to man-

eters when utilizing these functions. The parameters are

age the programming, erasure, and protection of the on-

written to 5 bytes of an 8-byte block near the top of RAM

chip Flash user program space. The Supervisor ROM

memory space.

also gives the user the capability to read the internal

product ID, access factory trim values, as well as calculate checksums on blocks of the Flash memory space.
The System Supervisor Call instruction (SSC, opcode/
byte 00h) provides the method for the user to access the
pre-existing routines in the Supervisor ROM to imple-

Access to these functions must be through the Flash

APIs provided in PSoC Designer and described in Application Note AN2015.
The following table documents each function, as well as
the required parameter values:

ment these functions. This instruction sets the Flags

Register (CPU_F) bit 3 to 1 and performs an interrupt to
address 0000 into the Supervisory ROM. The flag and
old PC are pushed onto the Stack. The fact that the flag
pushed has F[3] = 1 is irrelevant as the RETI instruction
always clears F[3]. The Supervisory code at 0000 does a
JACC table lookup based on the Accumulator value,
which is effectively another level of instruction encoding.
This service table implements the vectors to the various
supervisory functions. The user must set several param-

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Special Features of the CPU

Table 98:

CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM)

Operation

Function

Accumulator

1
Reset

Calibrates
then sets
PC and SP
values to 0

Input SRAM Data

Output SRAM Data

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

00

NA

NA

NA

NA

NA

NA

NA

NA

Read Block

Move block
of 64 bytes
of FLASH
data into
SRAM

01

3Ah

SP
+3

Blk
ID

Pointer

NA

Write Block2

Program
block of
FLASH with
data from
SRAM

02

3Ah

SP
+3

Blk
ID

Pointer

Clock

Erase Block

Erase block
of FLASH

03

3Ah

SP
+3

Blk
ID

NA

Clock

Protect Block3

Set memory
protection
bits4

04

3Ah

SP
+3

NA

NA

Clock

Erase All3

Erase all
FLASH data

05

3Ah

SP
+3

NA

NA

Clock

Table Read

Read device
type code

06

3Ah

SP
+3

Tbl
ID

NA

NA

NA

NA

NA

TV
(0)

TV
(1)

TV
(2)

TV
(3)

TV
(4)

TV
(5)

TV
(6)

TV
(7)

Checksum

Calculate
FLASH
checksum
for data
range specified

07

3Ah

SP
+3

Blk
Cou
nter

NA

NA

CS
H

CSL

Calibrate5

Sets userwritable registers to

default

08

3Ah

SP
+3

NA

NA

NA

1.
2.
3.
4.
5.

This is a software-only reset.

This operation should only be invoked by calling a function in the FlashBlock library. Device specifications are no
longer guaranteed if this function is directly called by the users code.
This function can only be invoked by the device programmer, not by users code.
The address is hard coded by algorithm.
User-writeable registers include Main Oscillator Trim (IMO_TR), Internal Low Speed Oscillator Trim (ILO_TR), and
Bandgap Trim (BDG_TR).

Notes:
NA: Not applicable
*: Indeterminate
Blk ID: Number of 64-byte block within FLASH memory space
Clock: CPU system clocking signal value
Pointer: Address of first byte of 64-byte block within SRAM memory space
TV: Table value

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11.8.1 Additional Function for Table Read

Supervisory Call
The Table Read supervisory operation will return the Version ID in the Accumulator. The value in the Accumulator
is divided into a high and low nibble, indicating major and
minor revisions, respectively. Note: The value in the X
Table 99:

Call, and must be saved and restored if needed after the

call completes.

A[7:4]: Major silicon revisions.

A[3:0]: Minor silicon revisions.

Table Read for Supervisory Call Functions

Table
ID

Function

001

01

1.

register is modified during the Table Read Supervisory

TV(0)

TV(1)

Production Silicon ID

Silicon ID
1

Silicon ID
0

Provides
trim value
for Internal Main
Oscillator
and Internal Voltage
Reference

Internal
Voltage
Reference trim
value for
3.3V

Internal
Main
Oscillator
trim value
for 3.3V

TV(2)

TV(3)

TV(4)

TV(5)

TV(6)

TV(7)

Reserved Reserved Reserved Reserved

Reserved

Reserved

Internal
Voltage
ReferReserved Reserved
ence trim
value for
5.0V

Reserved

Reserved

Internal
Main
Oscillator trim
value for
5.0V

Determines silicon revision values in Accumulator and X registers.

11.9

Flash Program Memory Protection

The user has the option to define the access to the Flash
memory. A flexible system allows the user to select one
of four protection modes for each 64-byte block within
the Flash, based on the particular application. The protection mechanism is implemented by a device program-

11.10 Programming Requirements and

Step Descriptions
The pins in the following table are critical for the programmer:

mer using the System Supervisor Call. When this

Table 101:

Programmer Requirements

command is executed, two bits within the data programmed into the Flash will select the protection mode.

Pin
Name

It is not intended that the protection byte will be modified

SDATA

Serial Data In/Out

Drive TTL Levels,

Read TTL, High Z

SCLK

Serial Clock

Drive TTL levEl Clock

Signal

Vss

Power Supply
Ground Connection

Low Resistance
Ground Connection

Vcc

Power Supply
Positive Voltage

0V, 3.0V, 5V, & 5.4V.

0.1V Accuracy. 20mA
Current Capability

Function

by the users code. The following table lists the available

protection options:
Table 100:
Mode
Bits

Flash Program Memory Protection

Mode Name

External
Read

External
Write

Internal
Write

00

Unprotected

Enabled

Enabled

Enabled

01

Factory
Upgrade

Disabled

Enabled

Enabled

10

Field Upgrade

Disabled

Disabled

Enabled

11

Full Protection

Disabled

Disabled

Disabled

Programmer HW Pin
Requirements

Note: Mode 10 is the default.

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Special Features of the CPU

11.10.1 Data File Read

The users data file should be read into the programmer.
The checksum should be calculated by the programmer
for each record and compared to the record checksum
stored in the file for each record. If there is an error, a
message should be sent to the user explaining that the
file has a checksum error and the programming should
not be allowed to continue.

11.10.2 Programmer Flow

The following sequence (with descriptions) is the main
flow used to program the devices: (Note that failure at
any step will result in termination of the flow and an error
message to the device programmers operator.)

11.10.2.1

Verify Silicon ID

value. If it is not the expected value, then the device is

failed and an error message is sent to the device programmers operator.
This test will detect a bad connection to the programmer
or an incorrect device selection on the programmer.
The silicon ID test is required to be first in the flow and
cannot be bypassed. The sequence is as follows:

Set Vcc=0V
Set SDATA=HighZ
Set SCLK=VILP
Set Vcc=Vccp
Start the programmers SCLK driver
free running
WAIT-AND-POLL
ID-SETUP
WAIT-AND-POLL
READ-ID-WORD
Notes: See DC Specifications table in section 13 for
value of Vccp and VILP. See AC Specifications table in
section 13 for value of frequency for the SCLK driver
(Fsclk).

Erase

The Flash memory is erased. This is accomplished by

the following sequence:

SET-CLK-FREQ(num_MHz_times_5)

August 18, 2003

11.10.2.3

Program

The Flash is programmed with the contents of the users

programming file. This is accomplished by the following
sequence:

For num_block = 0 to max_data_block

For address =0 to 63
WRITE-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SET-BLOCK-NUM(num_block)
PROGRAM-BLOCK
WAIT-AND-POLL
End for num_block loop
11.10.2.4

The silicon ID is read and verified against the expected

11.10.2.2

Erase All
WAIT-AND-POLL

Verify (at Low Vcc and High Vcc)

The device data is read out to compare to the data in the

users programming file. This is accomplished by the following sequence:

For num_block = 0 to max_data_block

SET-BLOCK-NUM (num_block)
VERIFY-SETUP
Wait & POLL the SDATA for a high to
low transition
For address =0 to max_byte_per_block
READ-BYTE(address,data)
End for address loop
End for num_block loop
Note: This should be done 2 times; once at Vcc=Vcclv
and once at Vcc=Vcchv.

11.10.2.5

Set Security

The security operation protects certain blocks from being

read or changed. This is done at the end of the flow so
that the security does not interfere with the verify step.
Security is set with the following sequence:

For address =0 to 63
WRITE-SECURITY-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SECURE
WAIT-AND-POLL
Note: This sequence is done at Vcc=Vccp.

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11.10.2.6

Device Checksum (at Low Vcc and High Vcc)

The device checksum is retrieved from the device and

Note: This should be done 2 times; once at Vcc=Vcchv

compared to the Device Checksum from the users file

and once at Vcc=Vcclv.

(Note that this is NOT the same thing as the Record

Checksum.) The checksum is retrieved from the device

11.10.2.7

Power Down

with the following sequence:

The last step is to power down the device. This is

accomplished by the following sequence:

CHECKSUM-SETUP(max_data_block)
WAIT-AND-POLL
READ-CHECKSUM(data)

Set SDATA=HighZ (float pin P1[0])

Set SCLK=0V (Vin on pin P1[1]=Vilp)
Set Vcc = 0V

11.11 Programming Wave Forms

Vcc

SDATA

OUT

OUT

IN
Tssclk

IN
Thsclk

SCLK
Figure 34: Programming Wave Forms
Notes:
1

Vcc is only turned off (0V) at the very beginning and the very end of the flow - not within the programming flow.

When the programmer puts the driver on SDATA in a High Z (floating) state, the SDATA pin will float to a low
due to an internal device pull down circuit.

SCLK is set to VILP during the power up and power down; at other times the SCLK is free running. The frequency of the hardwares SCLK signal must be known by the software because the value (entered in the number of MegaHertz multiplied by the number 5) must be passed into the device with the SET-CLK-FREQ()
mnemonic.

11.12 Programming File Format

The programming file is created by PSoC Designer, the
Cypress MicroSystems development tool. This tool generates the programming file in an Intel Hex format.
The programmer should assume the data is 30h/HALT if
it is not specified in the users data file.

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Development Tools

12.0

Development Tools
Graphical
Designer
Interface

Commands

Context
Sensitive Help

Results

Device
Database

PSoC
Configuration
Sheet

Application
Database

PSoC
Designer
Manufacturing
Info File

Project
Database

Emulation
Pod

In-Circuit
Emulator

Device
Programmer

Figure 35: PSoC Designer Functional Flow

12.1

Overview

The Cypress MicroSystems PSoC Designer is a

Microsoft

Windows-based, integrated development

environment for the Programmable System-on-Chip

(PSoC) devices. The PSoC Designer runs on Windows
98, Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP.

Emulator, in-system programming support, and the

CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language
compiler developed specifically for the devices in the
family.

PSoC Designer helps the customer to select an operating configuration for the microcontroller, write application
code that uses the microcontroller, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit

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12.2

Integrated Development Environment Subsystems

12.2.1 Online Help System

code to be merged seamlessly with C code. The link

The online help system displays online, context-sensitive

help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-

libraries automatically use absolute addressing or can be

compiled in relative mode, and linked with other software
modules to get absolute addressing.

sensitive help. This system also provides tutorials and

The compiler comes complete with embedded libraries

links to FAQs and an Online Support Forum to aid the

providing port and bus operations, standard keypad and

designer in getting started.

display support, and extended math functionality.

12.2.2 Device Editor

12.2.5 Debugger

PSoC Designer has several main functions. The Device

The PSoC Designer Debugger subsystem provides

Editor subsystem lets the user select different onboard

hardware in-circuit emulation, allowing the designer to

analog and digital component configurations for the

test the program in a physical system while providing an

PSoC blocks. PSoC Designer sets up power-on initial-

internal view of the PSoC device. Debugger commands

ization tables for selected PSoC block configurations and

allow the designer to read and write program and data

creates source code for an application framework. The

memory, read and write I/O registers, read and write

framework contains software to operate the selected

CPU registers, set and clear breakpoints, and provide

components and, if the project uses more than one oper-

program run, halt, and step control. The debugger also

ating configuration, contains routines to switch between

allows the designer to create a trace buffer of registers

different sets of PSoC block configurations at runtime.

and memory locations of interest.

PSoC Designer can print out a configuration sheet for

given project configuration for use during application programming in conjunction with the Device Data Sheet.
Once the framework is generated, the user can add

12.3

Hardware Tools

12.3.1 In-Circuit Emulator

application-specific code to flesh out the framework. Its

A low cost, high functionality ICE is available for devel-

also possible to change the selected components and

opment support. This hardware has the capability to pro-

regenerate the framework.

gram single devices.

12.2.3 Assembler
The included CYASM macro assembler supports the
M8C microcontroller instruction set and generates a load
file ready for device programming or system debugging
using the ICE hardware.

12.2.4 C Language Software Development

A C language compiler supports Cypress MicroSystems
PSoC family devices. Even if you have never worked in
the C language before, the product quickly allows you to
create complete C programs for the PSoC family
devices.
The embedded, optimizing C compiler provides all the
features of C tailored to the PSoC architecture. It
includes a built-in macro assembler allowing assembly

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DC and AC Characteristics

13.0

DC and AC Characteristics

Specifications are valid for -40 oC </= TA </= 85 oC and TJ </= 100 oC as specified, except where noted. Specifications
for devices running at 24 MHz are valid at -40 oC </= TA </= 70oC and TJ </= 82 oC.

5.25

4.75
Voltage
3.00

93 kHz

CPU Frequency

12 MHz

24 MHz

Figure 36: CY8C25xxx/CY8C26xxx Voltage Frequency Graph

13.1

Absolute Maximum Ratings

Table 102:

Absolute Maximum Ratings

Symbol

1.

Absolute Maximum Ratings

Minimum

Typical

Maximum
1

Unit
oC

Storage Temperature

-65

+100

Ambient Temperature with Power Applied

-40

+85

oC

Supply Voltage on Vcc Relative to Vss

-0.5

+6.0

DC Input Voltage

-0.5

Vcc+0.5

DC Voltage Applied to Tri-state

Vss-0.5

Vcc+0.5

Maximum Current into any Port Pin

-25

+50

mA

Maximum Current into any Port Pin Configured as Analog Driver

-50

+50

mA

Junction Temperature up to 12 MHz

1002

oC

Junction Temperature at 24 MHz

82

Static Discharge Voltage

2000

Latch-up Current

200

mA

Higher storage temperatures will reduce data retention time.

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2.

The temperature rise from junction to ambient is package specific. (See Table 122 on page 148 for thermal impedances of available packages.) User must limit power consumption to comply with this requirement.

Table 103:
Symbol
TA
TJ

128

Temperature Specifications
Temperature Specifications
Ambient Temperature
Junction Temperature

Minimum
-40

Typical
24

-40

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Maximum

Unit

+85

100

oC

August 18, 2003

DC and AC Characteristics

13.2

DC Characteristics

Table 104:

DC Operating Specifications

Symbol

DC Operating Specifications

Minimum

Typical

Maximum

Unit

Vcc

Supply Voltage

3.00

5.25

Icc

Supply Current

81

mA

Isb

Sleep (Mode) Current

52

Isbxtl

Sleep (Mode) Current with Crystal Oscillator

Vref

Reference Voltage (Bandgap)

1.275

1.3

1.3254

Vil

Input Low Voltage

0.8

Vih

Input High Voltage

2.2

Vh

Hysterisis Voltage

60

mV

Vol

Output Low Voltage

Vss+0.755

-1.06

Voh

Output High Voltage

Vcc

Rpu

Pull Up Resistor Value

4000

5600

8000

Rpd

Pull Down Resistor Value

4000

5600

8000

Iil

Input Leakage (Absolute Value)

0.1

Cin

Capacitive Load on Pins as Input

0.5

1.7

107

pF

1.7

107

pF

1.05 x Ideal8

Cout

Capacitive Load on Pins as Output

0.5

VLVD

LVD and SMP Tolerance8

0.95 x Ideal8 Ideal

1.
2.

Conditions are 5.0V, 25 oC, 3 MHz.

Without Crystal Oscillator, Vcc = 3.3 V, TA <= 85 oC.

3.

Conditions are 3.0V <= Vcc <= 3.6V, -40 oC <= TA <= 85 oC. Correct operation assumes a properly loaded, 1 uW
maximum drive level, 32.768 kHz crystal.
Trimmed for appropriate Vcc.
Isink = 25 mA, Vcc = 4.5 V (maximum of 8 IO sinking, 4 on each side of the IC).
Isource =10 mA, Vcc = 4.5 V (maximum of 8 IO sourcing, 4 on each side of the IC).
Package dependent.
Ideal values are +/- 5% absolute tolerance and +/- 1% tolerance relative to each other (for adjacent levels).

4.
5.
6.
7.
8.

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13.2.1

DC Operational Amplifier Specifications

13.2.1.1

5V Specifications

The following table lists guaranteed maximum and mini-

PSoC blocks. The guaranteed specifications are mea-

mum specifications for the voltage and temperature

sured in the Analog Continuous Time PSoC block. Typi-

ranges, 5V +/- 5% and -40C <= TA <= 85C. The Opera-

cal parameters apply to 5V at 25C and are for design

tional Amplifier is a component of both the Analog Con-

guidance only. For 3.3V operation, see Table 106 on

tinuous Time PSoC blocks and the Analog Switch Cap

page 131.

Table 105:
Symbol

1.
2.
3.

130

5V DC Operational Amplifier Specifications

5V DC Operational Amplifier Specifications

Minimum

Typical

Maximum

Unit

Input Offset Voltage (Absolute Value)

30

mV

Average Input Offset Voltage Drift

+24

V/C

Input Leakage Current1

1000

nA

Input Capacitance2

.30

.34

.40

pF

Common Mode Voltage Range3

.5

Vcc - 1.0

VDC

Common Mode Rejection Ratio

80

dB

Open Loop Gain

80

dB

High Output Voltage Swing (Worst Case Internal Load)

Bias = Low
Bias = Medium
Bias = High

Vcc - .4
Vcc - .4
Vcc - .4

V
V
V

Low Output Voltage Swing (Worst Case Internal Load)

Bias = Low
Bias = Medium
Bias = High

0.1
0.1
0.1

V
V
V

Supply Current (Including Associated AGND Buffer)

Bias = Low
Bias = Medium
Bias = High

125
280
760

300
600
1500

A
A
A

Supply Voltage Rejection Ratio

60

dB

The leakage current includes the Analog Continuous Time PSoC block mux and the analog input mux. The leakage related to the General Purpose I/O pins is not included here.
The Input Capacitance includes the Analog Continuous Time PSoC block mux and the analog input mux. The
capacitance of the General Purpose I/O pins is not included here.
The common-mode input voltage range is measured through an analog output buffer. The specification includes
the limitations imposed by the characteristics of the analog output buffer.

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DC and AC Characteristics

13.2.1.2

3.3V Specifications

The following table lists guaranteed maximum and mini-

Cap PSoC blocks. The guaranteed specifications are

mum specifications for the voltage and temperature

measured in the Analog Continuous Time PSoC block.

ranges, 3.3V +/- 10% and -40C <= TA <= 85C. The

Typical parameters apply to 5V at 25C and are for

Operational Amplifier is a component of both the Analog

design guidance only. For 5V operation, see Table 105

Continuous Time PSoC blocks and the Analog Switch

on page 130.

Table 106:

3.3V DC Operational Amplifier Specifications

Symbol

3.3V DC Operational Amplifier Specifications

2.
3.

Typical

Maximum

Unit

Input Offset Voltage (Absolute Value)

30

mV

Average Input Offset Voltage Drift

+24

V/C

700

nA

Input Capacitance2

.32

.36

.42

pF

Common Mode Voltage Range3

.5

Vcc - 1.0

VDC

Common Mode Rejection Ratio

80

dB

Open Loop Gain

80

dB

High Output Voltage Swing (Worst Case Internal Load)

Bias = Low
Bias = Medium
Bias = High

Vcc - .4
Vcc - .4
Vcc - .4

V
V
V

Low Output Voltage Swing (Worst Case Internal Load)

Bias = Low
Bias = Medium
Bias = High

0.1
0.1
0.1

V
V
V

Supply Current (Including Associated AGND Buffer)

Bias = Low
Bias = Medium
Bias = High

80
112
320

200
300
800

A
A
A

Supply Voltage Rejection Ratio

60

dB

Input Leakage

1.

Minimum

Current1

The leakage current includes the Analog Continuous Time PSoC block mux and the analog input mux. The leakage related to the General Purpose I/O pins is not included here.
The Input Capacitance includes the Analog Continuous Time PSoC block mux and the analog input mux. The
capacitance of the General Purpose I/O pins is not included here.
The common-mode input voltage range is measured through an analog output buffer. The specification includes
the limitations imposed by the characteristics of the analog output buffer

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13.2.2

Analog Input Pin with Multiplexer Specifications

Table 107:

DC Analog Input Pin with Multiplexer Specifications

Symbol

DC Analog Input Pin with Multiplexer Specifications

Minimum

Unit

0.1

Input Capacitance

0.5

1.7

pF

Bandwidth

10

MHz

Input Voltage Range

Vcc

Analog Input Pin to Switch Cap Block Specifications

Table 108:

DC Analog Input Pin to SC Block Specifications

1.
2.

Maximum

Input Leakage (Absolute Value)

13.2.3

Symbol

Typical

DC Analog Input Pin to SC Block Specifications

Minimum

Typical

Maximum

Unit

Effective input resistance = 1/(f x c)

51

Input Capacitance

0.5

10

pF

Bandwidth

1002

kHz

Input Voltage Range

Vcc

Assumes 2 pF cap selected and 100 kHz sample frequency.

This is a sampled input. Recommendation is Fs/Fin > 10 and for Fs = 1 MHz Fin < 100 kHz.

13.2.4

DC Analog Output Buffer Specifications

The following table lists guaranteed maximum and mini-

parameters apply to 5V at 25C and are for design guid-

mum specifications for the voltage and temperature

ance only. For 3.3V operation, see Table 110 on

ranges, 5V +/- 5% and -40C <= TA <= 85C. Typical

page 133.

Table 109:
Symbol

132

5V DC Analog Output Buffer Specifications

5V DC Analog Output Buffer Specifications

Minimum

Typical

Maximum

Unit

Input Offset Voltage (Absolute Value)

12

mV

Average Input Offset Voltage Drift

+6

V/C

Common-Mode Input Voltage Range

.5

Vcc - 1.0

Output Resistance
Bias = Low
Bias = High

1
1

High Output Voltage Swing (Load = 32 ohms to Vcc/2)

.5 x Vcc + 1.3
Bias = Low
.5 x Vcc + 1.3
Bias = High

V
V

Low Output Voltage Swing (Load = 32 ohms to Vcc/2)

Bias = Low
Bias = High

.5 x Vcc - 1.3 V
.5 x Vcc - 1.3 V

Supply Current Including Bias Cell (No Load)

Bias = Low
Bias = High

1.1
2.6

5.1
8.8

mA
mA

Supply Voltage Rejection Ratio

80

dB

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

DC and AC Characteristics

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature
ranges, 3.3V +/- 10% and -40C <= TA <= 85C. Typical
parameters apply to 5V at 25C and are for design guidance only. For 5V operation, see Table 109 on page 132.

Table 110:

3.3V DC Analog Output Buffer Specifications

Symbol

3.3V DC Analog Output Buffer Specifications

Minimum

Typical

Maximum

Unit

Input Offset Voltage (Absolute Value)

12

mV

Average Input Offset Voltage Drift

+6

V/C

Common-Mode Input Voltage Range

.5

Vcc - 1.0

Output Resistance
Bias = Low
Bias = High

1
1

High Output Voltage Swing (Load = 32 ohms to Vcc/2)

Bias = Low
Bias = High

.5 x Vcc + 1.3
.5 x Vcc + 1.3

V
V

Low Output Voltage Swing (Load = 32 ohms to Vcc/2)

Bias = Low
Bias = High

.5 x Vcc - 1.3
.5 x Vcc - 1.3

V
V

Supply Current Including Bias Cell (No Load)

Bias = Low
Bias = High

0.8
2.0

2.0
4.3

mA
mA

Supply Voltage Rejection Ratio

80

dB

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

133

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

13.2.5

Switch Mode Pump Specifications

Table 111:

DC Switch Mode Pump Specifications

Symbol

1.
2.

3.
4.

134

DC Switch Mode Pump Specifications

Minimum

Typical

Maximum

Unit

Output Voltage1

3.07

5.15

Available Output Current

Vi = 1.5 V, Vo = 3.25 V
Vi = 1.5 V, Vo = 5.0 V

82
5

mA
mA

Short Circuit Current (Vi = 3.3 V)

12

mA

Input Voltage Range (During sustained operation)

1.0

3.3

Minimum Input Voltage to Start Pump

1.1

1.2

Output Voltage Tolerance (Over Vi Range)

%Vo

Line Regulation (Over Vi Range)

%Vo

Load Regulation

%Vo

Output Voltage Ripple (Depends on capacitor and load)

253

mVpp

Transient Response
50% Load Change to 5% error envelope
Vo Over/Undershoot for 50% Load Change

1
1

s
%Vo

Efficiency

354

50

Switching Frequency

1.3

MHz

Switching Duty Cycle

50

Average, neglecting ripple.

For implementation, which includes 2 H inductor, 1 F capacitor, and Schottkey diode. Performance is significantly a function of external components. Specifications guaranteed for inductors with series resistance less than
0.1 W, with a current rating of > 250 mA, a capacitor with less than 1A leakage at 5V, and Schottkey diode with
less than 0.6V of drop at 50 mA.
Configuration of note 2. Load is 5 mA.
Configuration of note 2. Load is 5 mA. Vout is 3.25V.

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

DC and AC Characteristics

13.2.6

DC Analog Reference Specifications

The following table lists guaranteed maximum and mini-

the Analog Reference Control Register. The limits stated

mum specifications for the voltage and temperature

for AGND include the offset error of the AGND buffer

ranges, 5V +/- 5% and -40C <= TA <= 85C. The guar-

local to the Analog Continuous Time PSoC block. Typical

anteed specifications are measured through the Analog

parameters apply to 5V at 25C and are for design guid-

Continuous Time PSoC blocks. The bias levels for

ance only. (3.3V replaces 5V for the 3.3V DC Analog

AGND refer to the bias of the Analog Continuous Time

Reference Specifications.)

PSoC block. The bias levels for RefHi and RefLo refer to
Table 112:

5V DC Analog Reference Specifications

Symbol

5V DC Analog Reference Specifications

Minimum

Typical

Maximum

Unit

AGND = Vcc/21
CT Block Bias = High

Vcc/2 - 0.010

Vcc/2 - 0.004

Vcc/2 + 0.003

AGND = 2*BandGap1
CT Block Bias = High

2*BG - 0.043

2*BG - 0.010

2*BG + 0.024

AGND = P2[4] (P2[4] = Vcc/2)1

CT Block Bias = High

P24 - 0.013

P24 0.001

P24 + 0.014

-0.034

0.000

0.034

mV

REFHI = Vcc/2 + BandGap

Ref Control Bias = High

Vcc/2+BG - 0.140

Vcc/2+BG - 0.018

Vcc/2+BG +

REFHI = 3*BandGap
Ref Control Bias = High

3*BG - 0.112

3*BG - 0.018

3*BG + 0.076

2*BG+P2[6] 0.113

2*BG+P2[6] 0.018

2*BG+P2[6]+
0.077

P2[4]+BG 0.130

P2[4]+BG 0.016

P2[4]+BG +
0.098

REFHI = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] =

1.3V)
Ref Control Bias = High

P2[4]+P2[6] 0.133

P2[4]+P2[6] 0.016

P2[4]+P2[6]+
0.100

REFLO = Vcc/2 BandGap

Ref Control Bias = High

Vcc/2-BG - 0.051

Vcc/2-BG + 0.024

Vcc/2-BG + 0.098

REFLO = BandGap
Ref Control Bias = High

BG - 0.082

BG + 0.023

BG + 0.129

2*BG-P2[6] 0.084

2*BG-P2[6] +
0.025

2*BG-P2[6] +
0.134

P2[4]-BG 0.056

P2[4]-BG +
0.026

P2[4]-BG +
0.107

P2[4]-P2[6] 0.057

P24-P26 +
0.026

P2[4]-P2[6] +
0.110

AGND Column to Column Variation (AGND=Vcc/

2)1
CT Block Bias = High

REFHI = 2*BandGap + P2[6] (P2[6] = 1.3V)

Ref Control Bias = High
REFHI = P2[4] + BandGap (P2[4] = Vcc/2)
Ref Control Bias = High

REFLO = 2*BandGap - P2[6] (P2[6] = 1.3V)

Ref Control Bias = High
REFLO = P2[4] BandGap (P2[4] = Vcc/2)
Ref Control Bias = High
REFLO = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] =
1.3V)
Ref Control Bias = High

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

0.103

135

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 113:

3.3V DC Analog Reference Specifications

Symbol

3.3V DC Analog Reference Specifications

Minimum

Typical

Maximum

Unit

Vcc/2 - 0.007

Vcc/2 - 0.003

Vcc/2 + 0.002

AGND = Vcc/2
CT Block Bias = High
1

AGND = 2*BandGap
CT Block Bias = High

Not Allowed

AGND = P2[4] (P2[4] = Vcc/2)

CT Block Bias = High
AGND Column to Column Variation (AGND=Vcc/
2)1
CT Block Bias = High

P24 - 0.008

P24 + 0.001

P24 + 0.009

-0.034

0.000

0.034

mV

REFHI = Vcc/2 + BandGap

Ref Control Bias = High

Not Allowed

REFHI = 3*BandGap
Ref Control Bias = High

Not Allowed

REFHI = 2*BandGap + P2[6] (P2[6] = 0.5V)

Ref Control Bias = High

Not Allowed

REFHI = P2[4] + BandGap (P2[4] = Vcc/2)

Ref Control Bias = High

Not Allowed

REFHI = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] =

0.5V)
Ref Control Bias = High

P2[4]+P2[6] 0.075

P2[4]+P2[6] 0.009

P2[4]+P2[6]+
0.057

REFLO = Vcc/2 - BandGap

Ref Control Bias = High

Not Allowed

REFLO = BandGap
Ref Control Bias = High

Not Allowed

REFLO = 2*BandGap - P2[6] (P2[6] = 0.5V)

Ref Control Bias = High

Not Allowed

REFLO = P2[4] BandGap (P2[4] = Vcc/2)

Ref Control Bias = High

Not Allowed

REFLO = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] =

0.5V)
Ref Control Bias = High
1.

P2[4]-P2[6] 0.048

P24-P26 +
0.022

P2[4]-P2[6] +
0.092

AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 2%

13.2.7

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and mini-

<= TA <= 85C. Typical parameters apply to 3.3V and 5V

mum specifications include both voltage ranges, 5V +/-

at 25C and are for design guidance only.

5% and 3.3V +/- 10% and the temperature range -40C

Table 114:
Symbol

136

DC Analog PSoC Block Specifications

DC Analog PSoC Block Specifications

Minimum

Typical

Maximum

Unit

Resistor Unit Value (Continuous Time)

45

Capacitor Unit Value (Switch Cap)

70

fF

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

DC and AC Characteristics

13.2.8

DC Programming Specifications

Table 115:

DC Programming Specifications

Symbol

DC Programming Specifications

Minimum

Typical

Maximum

Unit

Iccp

Supply Current During Programming or Verify

20

mA

Vilp

Input Low Voltage During Programming or Verify

0.8

Vihp

Input High Voltage During Programming or Verify

2.2

Iilp

Input Current when Applying Vilp to P1[0] or P1[1]

During Programming or Verify

0.2

mA

Iihp

Input Current when Applying Vihp to P1[0] or

P1[1] During Programming or Verify

1.51

mA

Volv

Output Low Voltage During Programming or Verify -

Vss + 0.75 V

Vohv

Output High Voltage During Programming or

Verify

Vcc - 1.0

Vcc

Flashenpb

Flash Endurance (Per Block)

50,000

E/W Cycles
per Block

Flashent

Flash Endurance (Total)2

1,800,000

Flashdr

Flash Data Retention (After Cycling)

10

1.
2.

E/W Cycles
-

Years

Driving internal pull-down resistor.

A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1
blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500
maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
The CY8C25xxx/26xxx family of PSoC devices uses an adaptive algorithm to enhance endurance over the industrial temperature range (-40C to +85C ambient). Any temperature range within a 50C span between 0C and
85C is considered constant with respect to endurance enhancements. For instance, if room temperature (25C)
is the nominal operating temperature, then the range from 0C to 50C can be approximated by the constant value
25 and a temperature sensor is not needed.
For the full industrial range, the user must employ a temperature sensor User Module (FlashTemp) and feed the
result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://
www.cypressmicro.com under Support or Active Design Support for more information.

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

137

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

13.3

AC Characteristics

Table 116:

AC Operating Specifications

Symbol

AC Operating Specifications

Minimum

Typical

Maximum

Unit

FCPU1

CPU Frequency (5 V Nominal)1,2,3

91.35

2,400

2,460

kHz

FCPU2

CPU Frequency (3.3V Nominal)

4,3

91.35

1,200

1,230

kHz

F48M

Digital PSoC Block Frequency

48

49.21,5

MHz

F24M

Digital PSoC Block Frequency

24

24.62,4

MHz

FGPIO

GPIO Operating Frequency

12

FIMO

Internal Main Oscillator Frequency

(0oC to +85oC)

23.4

24

24.6

MHz

FIMOC

Internal Main Oscillator Frequency Cold

(-40oC to 0oC)

22.44

24

24.6

MHz

F32K1

Internal Low Speed Oscillator Frequency

(Non Sleep)

156

32

50

kHz

F32K2

Internal Low Speed Oscillator Frequency

(Sleep or Halt)

157

32

64

kHz

F32K3

External Crystal Oscillator

32.7688

kHz

Fpll

PLL Frequency

23.9869

MHz

Tf

Output Fall Time

210

12

ns

Tr

Output Rise Time

310

18

ns

Tpllslew

PLL Lock Time

0.5

10

ms

SVdd

Vdd Rise Rate at Power Up

8011

mV/ms

Tos

External Crystal Oscillator Startup to 1%

100

50012

ms

Tosacc

External Crystal Oscillator Startup to 100 ppm

150

60013

ms

Txrst

External Reset Pulse Width

10

MHz

1.
2.

4.75V < Vcc < 5.25V.

Accuracy derived from Internal Main Oscillator with appropriate trim for Vcc range.

3.
4.
5.

0oC to +85oC.
3.0V < Vcc < 3.6V.
See Application Note AN2012 Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation for information on maximum frequency for User Modules.
Limits are valid only when not in sleep mode.
Limits are valid only when in sleep mode.
Accuracy is capacitor and crystal dependent.
Is a multiple (x732) of crystal frequency.
Load capacitance = 50 pF.
To minimum allowable voltage for desired frequency.
The crystal oscillator frequency is guaranteed to be within 1% of its final value by the end of the 1s startup timer
period. Timer period may be as short as 640 ms for the case where F32K1 is 50 kHz. Correct operation assumes a
properly loaded 1uW maximum drive level 32.768 kHz crystal.
The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct opera-

6.
7.
8.
9.
10.
11.
12.

13.

tion assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V <= Vcc <= 5.5V, -40 oC <= TA
<= 85 oC.

138

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

DC and AC Characteristics

13.3.1

AC Operational Amplifier Specifications

The following table lists guaranteed maximum and mini-

block. The block is configured as an auto zeroed, gain of

mum specifications for the voltage and temperature

0.5, output sampled amplifier. All 32-feedback caps are

ranges, 5V +/- 5% and 40C <= TA <= 85C. Typical

parameters are provided for design guidance only. Typi-

on, 16 input caps are used (divide by 2), and the output

cal parameters apply to 5V and 25C. Settling times and

Continuous Time PSoC blocks. For 3.3V operation, see

slew rates are based on the Analog Switch Cap PSoC

Table 118 on page 140.

Table 117:

steps of 0.625V. Gain bandwidth is based on Analog

5V AC Operational Amplifier Specifications

Symbol

5V AC Operational Amplifier Specifications

Minimum

Typical

Maximum

Unit

Rising Settling Time to 0.1%

Bias = Low
Bias = Medium
Bias = High

2.7
1.4
0.6

s
s
s

Falling Settling Time to 0.1%

Bias = Low
Bias = Medium
Bias = High

1.7
0.9
0.5

s
s
s

Rising Slew Rate (20% to 80%)

Bias = Low
Bias = Medium
Bias = High

0.4
0.7
2.0

V/s
V/s
V/s

Falling Slew Rate (80% to 20%)

Bias = Low
Bias = Medium
Bias = High

0.7
1.7
2.5

V/s
V/s
V/s

Gain Bandwidth Product

Bias = Low
Bias = Medium
Bias = High

1.7
4.6
8.9

MHz
MHz
MHz

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

139

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 118:
Symbol

140

3.3V AC Operational Amplifier Specifications

3.3V AC Operational Amplifier Specifications

Minimum

Typical

Maximum

Unit

Rising Settling Time to 0.1%

Bias = Low
Bias = Medium
Bias = High

3.0
1.6
1.5

s
s
s

Falling Settling Time to 0.1%

Bias = Low
Bias = Medium
Bias = High

2.6
1.7
1.6

s
s
s

Rising Slew Rate (20% to 80%)

Bias = Low
Bias = Medium
Bias = High

0.2
0.3
0.3

V/s
V/s
V/s

Falling Slew Rate (80% to 20%)

Bias = Low
Bias = Medium
Bias = High

0.3
0.3
0.3

V/s
V/s
V/s

Gain Bandwidth Product

Bias = Low
Bias = Medium
Bias = High

1.5
4.4
8.7

MHz
MHz
MHz

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

DC and AC Characteristics

13.3.2

AC Analog Output Buffer Specifications

The following table lists guaranteed maximum and mini-

parameters are provided for design guidance only. Typi-

mum specifications for the voltage and temperature

cal parameters apply to 5V and 25C. For 3.3V opera-

ranges, 5V +/- 5% and 40C <= TA <= 85C. Typical

tion, see Table 120 on page 142.

Table 119:

5V AC Analog Output Buffer Specifications

Symbol

5V AC Analog Output Buffer Specifications

Minimum

Typical

Maximum

Unit

Rising Settling Time to 0.1%, 1V Step, 100pF Load

Bias = Low
Bias = High

2.5
2.5

s
s

Falling Settling Time to 0.1%, 1V Step, 100pF Load

Bias = Low
Bias = High

2.2
2.2

s
s

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

Bias = Low
Bias = High

.9
.9

V/s
V/s

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Bias = Low
Bias = High

.9
.9

V/s
V/s

Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Bias = Low
Bias = High

1.5
1.5

MHz
MHz

Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Bias = Low
Bias = High

600
600

kHz
kHz

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

141

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Table 120:
Symbol

3.3V AC Analog Output Buffer Specifications

3.3V AC Analog Output Buffer Specifications

Typical

Maximum

Unit

Rising Settling Time to 0.1%, 1V Step, 100pF Load

Bias = Low
Bias = High

3.2
3.2

s
s

Falling Settling Time to 0.1%, 1V Step, 100pF Load

Bias = Low
Bias = High

2.6
2.6

s
s

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

Bias = Low
Bias = High

.5
.5

V/s
V/s

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Bias = Low
Bias = High

.5
.5

V/s
V/s

Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Bias = Low
Bias = High

1.3
1.3

MHz
MHz

Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Bias = Low
Bias = High

360
360

kHz
kHz

Maximum

Unit

13.3.3

AC Programming Specifications

Table 121:

AC Programming Specifications

Symbol

Minimum

AC Programming Specifications

Minimum

Typical

Trsclk

Rise Time of SCLK

20

ns

Tfsclk

Fall Time of SCLK

20

ns

Tssclk

Data Set up Time to Rising Edge of SCLK

25

ns

Thsclk

Data Hold Time from Rising Edge of SCLK

25

ns

Fsclk

Frequency of SCLK

20

MHz

Teraseb

Flash Erase Time (Block)

10

ms

Terasef

Flash Erase Time (Full)

40

ms

Twrite

Flash Block Write Time

10

20

ms

142

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Packaging Information

14.0

Packaging Information

51-85064-B

Figure 37: 44-Lead Thin Plastic Quad Flat Pack A44

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

143

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

Figure 38: 20-Pin Shrunk Small Outline Package O20

144

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

51-85077-B

August 18, 2003

Packaging Information

51-85079-B

Figure 39: 28-Lead (210-Mil) Shrunk Small Outline Package O28

8 ead S

S a Out

ac age O 8

51-85061-C

Figure 40: 48-Lead Shrunk Small Outline Package O48

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

145

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

20 Lead (300 Mil) Molded DIP P5

51-85011-A

Figure 41: 20-Lead (300-Mil) Molded DIP P5

(

51-85014-B

Figure 42: 28-Lead (300-Mil) Molded DIP P21

51-85020-A

Figure 43: 48-Lead (600-Mil) Molded DIP P25

146

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Packaging Information

51-85024-A

Figure 44: 20-Lead (300-Mil) Molded SOIC S5

28 Lead (300 Mil) Molded SOIC S21

51-85026-A

Figure 45: 28-Lead (300-Mil) Molded SOIC S21

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

147

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

REVISIONS
ZONE

REV

ECN

**

1550

*A

49422

DESCRIPTION

DATE

APPROVED

NEW RELEASE

04/01/96

CHG. TITLE

04/03/97

8 Lead (300 Mil) PDIP

0.380
0.390

PIN 1 ID

DIMENSIONS IN INCHES MIN.

MAX.
0.240
0.260

0.300
0.325

0.100 BSC.
SEATING
PLANE

0.115
0.145

0.180 MAX.

0.008
0.015

0.015 MIN.

0.125
0.140

0-10

0.055
0.070
0.014
0.022

0.430 MAX.
DATE

DESIGNED BY

UNLESS OTHERWISE SPECIFIED

ALL DIMENSIONS ARE IN INCHES
STANDARD TOLERANCES ON:
DECIMALS
-+

.XX

.XXX
.XXXX

-+
+
-

MATERIAL

DATE

DRAWN
ANGLES
+
-

HTN

DATE

APPROVED BY

DATE

APPROVED BY

DATE

FINISH

CYPRESS
SEMICONDUCTOR

04/03/97

CHK BY

TITLE
SIZE

A
SCALE

8LD (300 MIL) PDIP PKG OUTLINE

PART NO.

P08.3
5X

DWG NO

REV

*A

51-85075
SHEET

OF

Figure 46: 8-Lead (300-Mil) Molded DIP

14.1

Thermal Impedances per Package

Table 122:

Thermal Impedances

Package

Typical JA

8 PDIP

121 C/W

20 PDIP

107 C/W

20 SOIC

80 C/W

20 SSOP

116 C/W

28 PDIP

68 C/W

28 SOIC

72 C/W

28 SSOP

95 C/W

48 PDIP

70 C/W

48 SSOP

69 C/W

44 TQFP

58 C/W

148

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003

Ordering Guide

15.0

Ordering Guide

Table 123:

Ordering Guide
Type

Ordering Code

Flash
(KBytes)

RAM
(Bytes)

SMP

Temperature
Range

8 Pin (300 Mil) Molded DIP

CY8C25122-24PI

256

No

Ind. -40C to +85C

20 Pin (300 Mil) Molded DIP

CY8C26233-24PI

256

Yes

Ind. -40C to +85C

20 Pin (300 Mil) Molded SOIC

CY8C26233-24SI

256

Yes

Ind. -40C to +85C

20 Pin (210 Mil) Shrunk Small Outline

Package

CY8C26233-24PVI

256

Yes

Ind. -40C to +85C

28 Pin (300 Mil) Molded DIP

CY8C26443-24PI

16

256

Yes

Ind. -40C to +85C

28 Pin (300 Mil) Molded SOIC

CY8C26443-24SI

16

256

Yes

Ind. -40C to +85C

28 Pin (210 Mil) Shrunk Small Outline

Package

CY8C26443-24PVI

16

256

Yes

Ind. -40C to +85C

48 Pin (600 Mil) Molded DIP

CY8C26643-24PI

16

256

Yes

Ind. -40C to +85C

48 Pin (300 Mil) Shrunk Small Outline

Package

CY8C26643-24PVI

16

256

Yes

Ind. -40C to +85C

44 Pin Thin Plastic Quad Flatpack

CY8C26643-24AI

16

256

Yes

Ind. -40C to +85C

August 18, 2003

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

149

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet

16.0

Document Revision History

Table 124:

Document Revision History

Document Title: CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet for Silicon Revision D
Document Number: 38-12010
Revision
ECN #
Issue Date
Origin of Change
Description of Change
**

116628

6/17/2002

CMS Cypress Management. New

Silicon Revision.

New document to CY Document Control (Revision **). Revision 3.20 for

CMS customers.

*A

127231

5/22/2003

HMT.

Implementing new error tracking and

document release procedure. Changes
in red for Document #: 38-12010 CY
Rev. *A CMS Rev. 3.20a. Changes
include:
--Bit 6 of the VLT_CR register is RW.
Should be changed from "RW" to "--."
--Analog Output Buffer Control Register
ABF_CR Read/Write in Bank 1 table
was corrected to Write Only.
--Rewrite of section 10.4 Analog Reference Control .
--AC Char. Spec. table changed .080 to
80 in "Vdd Rise Rate at Power Up."
On features pg. 2, changed "Up to 10
bit DAC" to "Up to 8 bit DAC."
--Adding temp. spec. for 24 MHz at
beginning of AC/DC Characteristics
section and Absolute Maximum Value
table.
--In AC Operating Spec. table fixed
footnote for Output Rise Time minimum.
--In AC Operating Spec. table fixed
value for External Reset Pulse Width.
--Changed uS to us units in tables.
--New intro.
--In the Analog Reference Control Register, ARF_CR, state 100 for bits 2:0
should be described as "All Analog
Off.
--Rework title pgs.

*B

127231

5/22/2003

HMT.

Several updates including Thermal

Impedances table, 8 PDIP diagram and
company address. OSC_CR0 register
name.

Distribution: External/Public
Posting: None

150

Document #: 38-12010 CY Rev. *B CMS Rev. 3.22

August 18, 2003