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CS 4141 Digital Systems Lab Report Cover Sheet: Experiment

This lab report describes experiments with shift registers and counters. The experiments included using a serial-to-parallel shift register IC, building a similar register with D flip-flops, using a binary counter IC, and building a 2-bit counter with JK flip-flops. State diagrams were provided to illustrate the behavior of each sequential circuit. The results matched expectations, showing the importance of sequential logic in designing circuits for storing data simply and performing arithmetic functions.

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486 views

CS 4141 Digital Systems Lab Report Cover Sheet: Experiment

This lab report describes experiments with shift registers and counters. The experiments included using a serial-to-parallel shift register IC, building a similar register with D flip-flops, using a binary counter IC, and building a 2-bit counter with JK flip-flops. State diagrams were provided to illustrate the behavior of each sequential circuit. The results matched expectations, showing the importance of sequential logic in designing circuits for storing data simply and performing arithmetic functions.

Uploaded by

[email protected]
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CS 4141 Digital Systems Lab Report

Cover Sheet

Experiment: 5 – Shifters,
Counters, and Their
Architecture

Sections: 002

Names:
Patrick Ring

NetIDs:
Pdr063000

Date of Experiment:
10/25/2009

Date of Report Submission:


11/15/2009
1. Objective:
The purpose of this experimaentis to familiarize ourselves with the
functionality of the serial-to-parallel shift register and the simple binary counter. After
operating the 74LS195 shift register and the 74LS163 binary counter, we constructed
very similar devices from D and J-K flip-flops on our prototype boards.
2. Changes:
No changes were necessary.

3. Answers:
a) D FF Shift Register

b) 2 Bit Binary Counter Using JK FF


c) Parallel in Serial out shift register using D FF

Timing Diagram

4. Diagrams:

1. 4-Bit Serial-to-Parallel Shift Register:


2. Binary
Counter:

5. Statements of Results:

1. The first circuit was a 4-bit shift register. Every clock


pulse shifts all the bits over by one. The last bit is
thrown away and the incoming bit is 1 if the input is
set to 1 and 0 if the input is set to 0

State Chart for 4-Bit Serial-to-Parallel Shift Register:


Current State A B C D Next State Input=0 Next State Input=1
0000 0000 1000
0001 0000 1000
0010 0001 1001
0011 0001 1001
0100 0010 1010
0101 0010 1010
0110 0011 1011
0111 0011 1011
1000 0100 1100
1001 0100 1100
1010 0101 1101
1011 0101 1101
1100 0110 1110
1101 0110 1110
1110 0111 1111
1111 0111 1111
2. The second circuit was a 4-bit binary counter which
had no input. It counts from 0 to 15 in binary and
starts back at 0 afterwards. It increments with every
clock pulse.

State Chart for 4-Bit Binary Counter:


Current State A B C D Next State
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 1010
1010 1011
1011 1100
1100 1101
1101 1110
1110 1111
1111 0000

3. This is the same type of register as in part one


except that we built it from D flip flop rather than just
using the Shift Register IC.

State Chart for 4-Bit Serial-to-Parallel Shift Register


using D FFs:
Current State A B C D Next State Input=0 Next State Input=1
0000 0000 1000
0001 0000 1000
0010 0001 1001
0011 0001 1001
0100 0010 1010
0101 0010 1010
0110 0011 1011
0111 0011 1011
1000 0100 1100
1001 0100 1100
1010 0101 1101
1011 0101 1101
1100 0110 1110
1101 0110 1110
1110 0111 1111
1111 0111 1111
4. This is a 2 bit binary counter built using 2 JK flip
flops. It counts to 3 in binary and then starts over from
0 and counts again. It increments with every clock
pulse. The input is connected to the clear and resets
the counter to 0.

State Chart for 2-Bit Binary Counter Using JK FFs:


Current State A B C D Next State Input = 0 Next State Input = 1
00 01 00
01 10 00
10 11 00
11 00 00

6. Discussion of Results:
The results of this lab are what one would expect. Sequential circuits make high level design
much simpler and provide for an easy way to store data. The toughest part in this lab for
achieving the correct results was tweaking the clock signal to get the right clock pulse rhythm
going. It is interesting to note that unlike previous labs, we started with the ICs that had the
functions already built in first and then moved to try and imitate those functions with their
component parts.
7. Summary and Conclusions:
It is easy to see the importance of using sequential logic to design circuits. It makes for simple
data storage and arithmetic functions. One could theoretically build the same circuits using
combinational circuits of AND, OR, and NOT alone and possibly make it more efficient.
However, in design of major large-scale systems that would be unrealistic. It is better to come
up with the design using available parts that are already there and then try and optimize
afterward.

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