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ANALOGUE Assignment

This document outlines an individual assignment to design and analyze a transimpedance amplifier (TIA) circuit in 0.13 μm CMOS technology. Students are instructed to design a shunt-shunt feedback TIA based on the provided schematic and simulate it in Cadence. They must then submit a technical report analyzing the circuit design, explaining the functioning of components, and verifying simulation results. The report will be graded based on clarity of the technical theory, achievement of the correct circuit design, explanation of component workings, and ability to simulate and answer questions about the designed circuit.

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Chun Hui Tan
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85 views4 pages

ANALOGUE Assignment

This document outlines an individual assignment to design and analyze a transimpedance amplifier (TIA) circuit in 0.13 μm CMOS technology. Students are instructed to design a shunt-shunt feedback TIA based on the provided schematic and simulate it in Cadence. They must then submit a technical report analyzing the circuit design, explaining the functioning of components, and verifying simulation results. The report will be graded based on clarity of the technical theory, achievement of the correct circuit design, explanation of component workings, and ability to simulate and answer questions about the designed circuit.

Uploaded by

Chun Hui Tan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Analog VLSI Circuit Design

Individual Assignment

Page 1 of 4

ASSIGNMENT TOPIC:
Design and Analysis of Transimpedance Amplifier (TIA) in 0.13 m Standard CMOS
Technology

Instructions:

This assignment is to be carried out individually.

Course Outcomes
UPON COMPLETION OF THE MODULE YOU SHOULD BE ABLE TO DEMONSTRATE
THE FOLLOWING COURSE OUTCOMES:

Analyze the theoretical concepts of analog CMOS VLSI circuits.


Integrate basic analog CMOS VLSI circuits.
Evaluate the performance of integrated CMOS analog circuits adapting
standardized state of the art tools.

The objective of this assignment is being devoted to the design and analysis of low voltage
CMOS amplifier.
Theory:
Transimpedance amplifier play a critical role in optical receivers. Trade-offs between noise,
speed, gain and supply voltage present many challenges in TIA design. The TIA bandwidth is
typically chosen to be equal 0.7 times the bit rate a reasonable compromise between total
integrated noise and the intersymbol interference (ISI) resulting from limited bandwidth. Fig. 1
shows a common gate topology is a candidate for TIAs as it provides a relatively low input
impedance, a broad band, and a well behaved time response. However, its input referred noise
current is relatively high.
A TIA configuration that achieves more relaxed noise headroom trade-offs is the shunt-shunt
feedback topology. Actual implementations of feedback TIA suffer from voltage headroom,
stability and overshoot problem. Fig. 2 suggests a modification which allow a greater drop
across RD.

KEEE 4469

University of Malaya

2015

Individual Assignment

Analog VLSI Circuit Design

Page 2 of 4

VDD

RD

Vout

Iin

CD

M1

Vb1

M2

Vb2

Fig. 1 . Common gate TIA

VDD

VDD

RD
RF

M2
Vout
M1

Iin

CL

CD

Fig. 2. Feedback TIA

Work Programme:
Design, verify and analyze a shunt-shunt feedback CMOS Transimpedance Amplifier (TIA) as
in Fig. 2
1) Design and simulate a low voltage CMOS Transimpedance Amplifier in 0.13 m
standard CMOS technology adapting Cadence-Spectre Platform. The amplifier is
targeted in the application 2.5Gb/s optoelectronic transceiver for optical
communication.

KEEE 4469

University of Malaya

2015

Analog VLSI Circuit Design

Individual Assignment

Page 3 of 4

2) A individual technical report and presentation is to be submitted adhering to the below


mentioned requirements :

a) Clear Technical Theory details related to the Assignment.


[30 % ]
b) Achievement of the correct circuit design for the TIA.
[20 % ]

c) Proper explanation for the working of individual components in the designed


circuit.
[15 % ]
d) Able to verify the full in the class simulation, also able to answer the questions
related to the designed circuit.
[15 % ]
e) Discussion and conclusion
[20 % ]

3) The grading criteria of the report are based on :

Grading Criteria:

A: 80% +

Clear and well presented theory details related to your Assignment.


Able to achieve the correct circuit design.
Able to explain the working of individual components in the designed circuit.
Able to perform the full test in the laboratory, also able to answer the questions
related to the designed circuit.

B: 70-79%

KEEE 4469

Clear and well presented theory details related to your Assignment.


Able to achieve the correct circuit design.
Able to explain the working of individual components in the designed circuit.
Not able to perform the full test in the laboratory, but able to answer the questions
related to the designed circuit.
University of Malaya

2015

Individual Assignment

Analog VLSI Circuit Design

Page 4 of 4

C: 60-69%

Clear and well presented theory details related to your Assignment.


Able to achieve the correct circuit design.
Able to explain the working of individual components in the designed circuit.
Not able to perform the full test in the laboratory, also not able to answer the
questions related to the designed circuit.

D: 50-59%

Clear and well presented theory details related to your Assignment.


Able to achieve the correct circuit design.
Not able to explain the working of individual components in the designed
circuit.
Not able to perform the full test in the laboratory, also not able to answer the
questions related to the designed circuit.

E: 40-49%

Clear and well presented theory details related to your Assignment.


Not able to achieve the correct circuit design.
Not able to explain the working of individual components in the designed
circuit.
Not able to perform the full test in the laboratory, also not able to answer the
questions related to the designed circuit.

F: 0-39%

KEEE 4469

Not clear and well presented theory details related to your Assignment.
Not able to achieve the correct circuit design.
Not able to explain the working of individual components in the designed
circuit.
Not able to perform the full test in the laboratory, also not able to answer the
questions related to the designed circuit.

University of Malaya

2015

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