Summary

Introduction
ATEs
Test programs.

Summary

Introduction
ATEs
Test programs.

Introduction

Once

The test vectors have been generated and the

achieved fault coverage is sufficient
The circuit answer to the test vectors is known

it ispossible to move to the application of the test

vectors and to verifying the behavior of the circuit
This operation is performed by the test machine
(Automatic Test Equipment o ATE).

ATE jobs

The ATE must:

Apply the test vectors

Verify the circuit behavior
Identify the faulty circuits.

Summary

Introduction

ATEs

Test programs.

ATEs

The ATE allow t apply a set of test vectors

to a circuit and to verify its response.
The cost of the ATE (that may overcome
one million dollars) may represent one of
the main components of the test costs.

ATE types

There are several categories of ATEs, depending

on the kind of device they must act on:

Wafer
ASIC
Memories
Processors
Boards.

the main focus here will be on ATEs for ASIC

testing.

Structure

An ATE is composed of

An host system, normally corresponding to a

workstation, playing the role of interface
towards the user
A central system
One or more test head, where the circuit under
test (CUT) is placed
A possible loading system, to load the circuit
on the test head.

Example (Teradyne J973)

Test head

They contain the circuitry to connect the

circuit pins to the test system.
Each pin is connected to one or more ATE
channels, each able to

Provide a sequence of bits with a given

frequency (for the input pins)
Read the bits produced by the circuit, sampling
them according to specified time strobe
information (for the output pins).

Probe card

The test head includes a probe card, that

interfaces the signals coming from the ATE
with the DUT, through the probe needles.

Multi-site test

When an ATE controls more than one test

head, we have the so-called multi-site test
In such a case

The DUTs are the same

The test program is the same
The test time can be reduced, optimizing the
ATE usage.

Critical parameters

Number of channels
Max operating frequency
Memory associated to channels
Precision
Accuracy
Supported functions.

Critical parameters

Number of channels
Max operating frequency
Memory associated
to
channels
It must basically be the same as the
Precision number of pins in the circuit under
test.
Accuracy It is possible to multiplex different
on the same channel.
Supportedpins
functions.
The current products support up to
1,024 channels.

Critical parameters

Number of channels
Max operating frequency
Memory associated to channels
Precision
In the last products it may
Accuracy
overcome 1 GhZ.
Supported functions.

Critical parameters

Number of channels
Max operating frequency
Memory associated to channels
Precision
Accuracy
It is often in the range 120
Supported functions.Mbit/channel.

Critical parameters

Number of channels
Max operating frequency
Memory associated to channels
Precision
Accuracy
Supported functions.
It is the maximum resolution

capacity between voltage values

provided by the ATE.

Critical parameters

Number of channels
Max operating frequency
Memory associated
to
channels
It corresponds to the lack of
precision in positioning the
Precision
times of application and
Accuracy
observation of values.
The accuracy of current
Supported functions.
products is around some
hundreds of ps.

Critical parameters

Number of For
channels
example, the possibility of
Performing
Max operating
frequencyIddq test
Specify complex test algorithms
Memory associated
to channels
for memories

Precision
Accuracy
Supported functions.

Test programs

They specify the operation mode of the

ATE, and in particular:

The values to be applied to each pin

The timing for the operation
The timing for observing each pin, and the
expected values
The sequence of test operations to be
performed.

Pin timing

The test program must specify for each pin

the timing for applying vectors (on input
pins) and observing values (for output
pins).
The timing reference may be

The ATE clock, that is then sent to the clock

input
The internal clock of the circuit: the ATE must
be synchronized with it.

Test duration

It is often the most critical parameter, since

it directly impacts the test cost.
It may be reduced

By optimizing the test program

By increasing the number of test head.

Summary

Introduction
ATEs

Test programs.

Test programs

They describe the sequence and

characteristics of the test operations to be
performed.
They resort to specific languages, which
are compatible with other CAD tools.
They normally follow the stop-on-first-fail
approach, where the test is interrupted as
soon as an error is detected.

Languages

Several languages (incompatible one with the

other) exist:

UTIC (Motorola)
TDL (TI)
WGL (SummitDesign)

IEEE defined in 1999 a standard language named

STIL for transferring digital test vectors.

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:

DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

7.
8.
9.
10.
11.

AC Pin Specification
Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

It is based on measuring some

currents and voltages on the pins
once the circuit has been turned on.

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:

DC Pin Parametrics
7.
AC Pin Specification
Test Logic Verification
8.
Memory Testing
DC Logic Stuck-at
9.
Memory Retention
aims at verifying 10. Idd e Iddq
DC LogicItRetention
The
correct connection
of pins to bonds
AC Frequency
Assessment
11. Vettori speciali.
The voltages on the pins
AC Logic Delay
The leakage currents through the pins.

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:

DC Pin Parametrics
7.
AC Pin Specification
Test Logic Verification
8.
Memory Testing
DC Logic Stuck-at
9.
Memory Retention
DC Logic Retention
10. Idd e Iddq
AC Frequency
Assessment
11. correct
Vettori behavior
speciali. of
It aims
at verifying the
test circuitry (if any) before using it.
AC Logic the
Delay

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:

DC Pin Parametrics
7.
AC Pin Specification
In this phase the fuctional
Test Logic Verification vectors
8. are
Memory
Testing
applied,
as well
as those
generated
to detect
DC Logic Stuck-at
9.
Memory
Retention
stuck-at
faults (usually by
DC Logic Retention
10. Idd e Iddq
scan).
AC Frequency Assessment
11. Vettori speciali.
The frequency
is normally
AC Logic Delay
lower than the operating
one.

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:

DC Pin Parametrics
7.
AC Pin Specification
Test Logic Verification
8.
Memory Testing
DC Logic Stuck-at
9.
Memory Retention
It verifies whether the
DC Logic Retention
10. Idd e Iddq
memory elements work
AC Frequency Assessmentcorrectly.
11. Vettori speciali.
AC Logic Delay

Operation sequence

1.
2.
3.
4.
5.
6.

It verifies
whether followed
the
The sequence which
is normally
is
circuit correctly works at the
the sequent:
operating frequency.
Normally, a subset of the
7.
AC Pin isSpecification
functional
vetors
used.

DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

8.
9.
10.
11.

Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:
The vectors generated to
7.
AC
Pin Specification
test delay
faults
are applied.

DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

8.
9.
10.
11.

Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

Operation sequence

It verifies whether the

timing constraints are
verified on the single pins
(e.g.,
The setup
sequence
which
is normally
and hold
times).

the sequent:

1.
2.
3.
4.
5.
6.

DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

7.
8.
9.
10.
11.

followed is

AC Pin Specification
Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

Operation sequence

It performs the test of

memories, possible
exploiting ad hoc BIST
The sequence which
structures.

the sequent:

1.
2.
3.
4.
5.
6.

DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

is normally followed is
7.
8.
9.
10.
11.

AC Pin Specification
Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

Operation sequence

It verifies the ability of

memories to maintain the
data.
The sequence which

the sequent:

1.
2.
3.
4.
5.
6.

DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

is normally followed is
7.
8.
9.
10.
11.

AC Pin Specification
Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

Operation sequence

1.
2.
3.
4.
5.
6.

The sequence which is normally followed is

the sequent:

It
current-based
DCperforms
Pin Parametrics
testing.
Test Logic Verification

DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

7.
8.
9.
10.
11.

AC Pin Specification
Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.

Operation sequence
The sequence which is normally followed is
Finally, the vectors are
the sequent:
applied
for

1.
2.
3.
4.
5.
6.

Analog parts
DC Pin
StillParametrics
untested parts.

Test Logic Verification

DC Logic Stuck-at
DC Logic Retention
AC Frequency Assessment
AC Logic Delay

7.
8.
9.
10.
11.

AC Pin Specification
Memory Testing
Memory Retention
Idd e Iddq
Vettori speciali.