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Assignment 2 Solution

This document summarizes the solution to a computer architecture assignment involving analyzing the performance of RISC pipelines with different stages and hardware. It examines: - Data dependences in a code fragment running on a 5-stage pipeline - Timing of the code on 5-stage and 10-stage pipelines with and without forwarding/bypassing - Clock cycle times and cycles per instruction for the 5-stage and 10-stage pipelines - Speedup and cycles per instruction when comparing a 5-stage and 12-stage pipeline accounting for data hazards and branch mispredictions.

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Aaliya Ali Abdul
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740 views

Assignment 2 Solution

This document summarizes the solution to a computer architecture assignment involving analyzing the performance of RISC pipelines with different stages and hardware. It examines: - Data dependences in a code fragment running on a 5-stage pipeline - Timing of the code on 5-stage and 10-stage pipelines with and without forwarding/bypassing - Clock cycle times and cycles per instruction for the 5-stage and 10-stage pipelines - Speedup and cycles per instruction when comparing a 5-stage and 12-stage pipeline accounting for data hazards and branch mispredictions.

Uploaded by

Aaliya Ali Abdul
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to Computer Architecture

Assignment 2 - Solution
Due April 15, 2014

1. [70 = 10 x 7] Use the following code fragment:


Loop:
LD
R1, 0(R2)
; load R1 from address 0+R2
DADDI
R1, R1, #1
; R1 = R1 + 1
SD
R1, 0, (R2)
; store R1 at address 0+R2
DADDI
R2, R2, #4
; R2 = R2 + 4
DSUB
R4, R3, R2
; R4 = R3 - R2
BNEZ
R4, Loop
; branch to Loop if R4 != 0
Assume that the initial value of R3 is R2 + 396.
a. Data hazards are caused by data dependences in the code. List all of the data
dependences in the code above. Record the register, source instruction, and
destination instruction; for example, there is a data dependency fro register R1
from the LD to DADDI, that is,
R1
LD
DADDI
b. Show the timing of this instruction sequence for the 5-stage RISC pipeline without
any forwarding or bypassing hardware but assuming that a register read and a
write in the same clock forwards through the register file, as shown in Figure
C.6. Use a pipeline timing chart like that in Figure C.5. Assume that the branch is
handled by flushing the pipelining. If all memory references take 1 cycle, how
many cycles does this loop take to execute?
c. Show the time of this instruction sequence for the 5-state RISC pipeline with full
forwarding and bypassing hardware. Use a pipeline timing chart like that shown in
Figure C.5. Assume that the branch is handled by predicting it as not taken. If all
memory references take 1 cycle, how many clock cycles does this loop take to
execute?
d. Show the timing of this instruction sequence for the 5-stage RISC pipeline with
full forwarding and bypassing hardware. Use a pipeline timing chart like that
shown in Figure C.5. Assume that the branch is handled by predicting it as taken.
If all memory references take 1 cycle, how many clock cycles does this loop take
to execute?
e. High-performance processors have very deep pipelines-more than 15 stages.
Imagine that you have a 10-stage pipeline in which every stage of the 5-stage
pipeline has been split in two. The only catch is that, for data forwarding, data are
forwarded from the end of a pair of stages to the beginning of the two stages
where they are needed. For example, data are forwarded from the output of the
second execute stage to the input of the first execute stage, still causing a 1-cycle

delay. Show the timing of this instruction sequence for the 10-stage RISC pipeline
with full forwarding and bypassing hardware. Use a pipeline timing chart like that
shown in Figure C.5. Assume that the branch is handled by predicting it as taken.
If all memory references take 1 cycle, how many cycles does this loop take to
execute?
f. Assume that in the 5-stage pipeline the longest stage requires 0.8 ns, and the
pipeline register delay is 0.1 ns. What is the clock cycle time of the 5-stage
pipeline? If the 10-stage pipeline splits all stages in half, what is the cycle time of
the 10-stage machine?
g. Using you answers from parts (d) and (e), determine the cycles per instruction
(CPI) for the loop on a 5-stage pipeline and a 10-stage pipeline. Make sure you
count only from when the first instruction reaches the write-back stage to the end.
Do not count the start-up of the first instruction. Using the clock cycle time
calculated in part (f), calculate the average instruction execute time for each
machine.
Solution

1586

2. [30 = 10 + 20] In this problem, we will explore how deepening the pipeline affects
performance in two ways: faster clock cycle and increased stalls due to data and
control hazards. Assume that the original machine is a 5-stage pipeline with a 1 ns
clock cycle. The second machine is a 12-stage pipeline with a 0.6 ns clock cycle. The
5-stage pipeline experiences a stall due to a data hazard every 5 instructions, whereas
the 12-stage pipeline experiences 3 stalls every 8 instructions. In addition, branches
constitute 20% of the instructions, and the misprediction rate for both machines is 5%.
a. What is the speed up of the 12-stage pipeline over the 5-stage pipeline, taking into
account only data hazards?
b. If the branch mispredict penalty for the first machine is 2 cycles but the second
machine is 5 cycles, what are the CPIs of each, taking into account the stalls due
to branch mispredictions?
Solution

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