Control

Control unit takes input from

the instruction opcode bits

Control unit generates

ALU control input

write enable (possibly, read enable also) signals for each storage
element
selector controls for each multiplexor

ALU Control

Plan to control ALU: main control sends a 2-bit ALUOp control field
to the ALU control. Based on ALUOp and funct field of instruction the
ALU control generates the 3-bit ALU control field

ALU control
field
000
001
010
110
111

Function
and
or
add
sub
slt

ALU must perform

2
ALUOp

Main
Control

3
ALU
Control

ALU
control
input

6
Instruction
funct field

add for load/stores (ALUOp 00)

sub for branches (ALUOp 01)
one of and, or, add, sub, slt for R-type instructions, depending on the
instructions 6-bit funct field (ALUOp 10)

To
ALU

Setting ALU Control Bits

Instruction AluOp
opcode
LW
SW
Branch eq
R-type
R-type
R-type
R-type
R-type

00
00
01
10
10
10
10
10

Instruction Funct Field Desired

ALU control
operation
ALU action input
load word
store word
branch eq
add
subtract
AND
OR
set on less

xxxxxx
xxxxxx
xxxxxx
100000
100010
100100
100101
101010

add
add
subtract
add
subtract
and
or
set on less

ALUOp
Funct field
Operation
ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0
0
X X X X X X
010
0
1
X X X X X X
110
1
X
X X 0 0 0 0
010
1
X
X X 0 0 1 0
110
1
X
X X 0 1 0 0
000
1
X
X X 0 1 0 1
001
1
X
X X 1 0 1 0
111
Truth table for ALU control bits

010
010
110
010
110
000
001
111

Designing the Main Control

R-type

opcode

31-26
Load/store
or branch

opcode
31-26

rs

25-21

rt

20-16

rs

rt

25-21

20-16

rd

shamt

funct

15-11

10-6

5-0

address
15-0

Observations about MIPS instruction format

opcode is always in bits 31-26

two registers to be read are always rs (bits 25-21) and rt (bits 2016)
base register for load/stores is always rs (bits 25-21)
16-bit offset for branch equal and load/store is always bits 15-0
destination register for loads is in bits 20-16 (rt) while for R-type
instructions it is in bits 15-11 (rd) (will require multiplexor to select)

Datapath with Control I

PCSrc

PC+4

Add
4

Add

New multiplexor

Instruction [25 21] rs

PC

Read
address
Instruction
[31 0]
Instruction
memory

Instruction [20 16] rt

1
M
rd
u
Instruction [15 11] x
0

rd or rt

Read
register 2

rt or SE(offset)
Read
data 1

MemWrite

rs
ALUSrc

Read
Write
data 2
register
Write
Registers
data

rt

Zero
ALU ALU
result

1
M
u
x
0

16

Sign
extend

32

Instruction [5 0] 6 bits of

funct. field

MemtoReg

Address

Write
data

RegDst

Instruction [15 0]

PC+4 or BT

Shift
left 2

RegWrite

Read
register 1

ALU
result

1
M
u
x
0

3 bit
control signal

ALU
control

2 bits of ALUOp
ALUOp

Read
data

Data
memory

1
M
u
x
0

MemRead

use o/p
from ALU
or DM

Adding control to the MIPS Datapath III (and a new multiplexor to select field to
specify destination register): what are the functions of the 9 control signals?

Control Signals
Default Behaviour in a way

Signal Name

Effect when deasserted

Effect when asserted

RegDst

The register destination number for the

Write register comes from the rt field (bits 20-16)
None

The register destination number for the

Write register comes from the rd field (bits 15-11)
The register on the Write register input is written
with the value on the Write data input
The second ALU operand is the sign-extended,
lower 16 bits of the instruction
The PC is replaced by the output of the adder
that computes the branch target
Data memory contents designated by the address
input are put on the first Read data output
Data memory contents designated by the address
input are replaced by the value of the Write data input
The value fed to the register Write data input
comes from the data memory

RegWrite
AlLUSrc

MemRead

The second ALU operand comes from the

second register file output (Read data 2)
The PC is replaced by the output of the adder
that computes the value of PC + 4
None

MemWrite

None

MemtoReg

The value fed to the register Write data input

comes from the ALU

PCSrc

Effects of the seven control signals

Datapath with Control II

0
M
u
x
ALU
Add result
Add
4
Instruction [31 26]

Control

Instruction [25 21]

PC

Read
address

Instruction
memory

Instruction [15 11]

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite

PCSrc

Read
register 1

Instruction [20 16]

Instruction
[31 0]

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Zero
ALU ALU
result

Address

Write
data
Instruction [15 0]

16

Sign
extend

Read
data
Data
memory

32
ALU
control

Instruction [5 0]

MIPS datapath with the control unit: input to control is the 6-bit instruction
opcode field, output is seven 1-bit signals and the 2-bit ALUOp signal

1
M
u
x
0

PCSrc cannot be
set directly from the
opcode: zero test
outcome is required

M
u
x
Add
Add

Shift
left 2

RegDst
Branch

ALU
result

PCSrc

MemRead
Instruction [31 26]

MemtoReg
Control

ALUOp
MemWrite
ALUSrc

RegWrite
Instruction [25 21]
PC

Read
address

Instruction [20 16]

Instruction
[31 0]

Instruction
memory

Read
register 1

Instruction [15 11]

Datapath with
Control II (cont.)

Instruction [15 0]

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Zero
ALU ALU
result

Address

Write
data
16

Sign
extend

Read
data
Data
memory

1
M
u
x
0

32
ALU
control

Instruction [5 0]

Determining control signals for the MIPS datapath based on instruction opcode
Memto- Reg Mem Mem
Instruction RegDst ALUSrc
Reg
Write Read Write Branch ALUOp1 ALUp0
R-format
1 =rd
0
0
1
0
0
0
1
0
lw
0 =rt
1
1
1
1
0
0
0
0
sw
X
1
X
0
0
1
0
0
0
beq
X
0
X
0
0
0
1
0
1
Whenever we need to enable writing to Reg.

Control Signals:
R-Type Instruction
ADD

0
M
U
X

ADD
ADD

rs
rt
rd
I[25:21] I[20:16] I[15:11]

PC

Instruction
ADDR

RD

I
32

Instruction
Memory

RN1

RN2

RegDst

Register File
immediate/
offset
I[15:0]

Value depends on

funct

ALU

Zero

0
M
U
X

RD2
RegWrite

1
Control signals
shown in blue

???

Operation

WN
RD1

WD

PCSrc

MUX

16

<<2

16

E
X
T
N
D

1
32

ALUSrc

MemWrite
ADDR

Data
Memory

MemtoReg
1
RD

M
U
X

WD
MemRead

Control Signals:
lw Instruction
ADD

0
M
U
X

ADD
ADD

rs
rt
rd
I[25:21] I[20:16] I[15:11]

PC

Instruction
ADDR

RD

I
32

Instruction
Memory

RN1

RN2

RegDst

010
Operation

WN
RD1

Register File
WD
immediate/
offset
I[15:0]

ALU

Zero

0
M
U
X

RD2
RegWrite

1
Control signals
shown in blue

PCSrc

MUX

16

<<2

16

E
X
T
N
D

1
32

ALUSrc

MemWrite
ADDR

Data
Memory

MemtoReg
1
RD

M
U
X

WD
MemRead

Control Signals:
sw Instruction
ADD

0
M
U
X

ADD
ADD

rs
I[25:21]

PC

rt
I[20:16]

rd
I[15:11]

Instruction
ADDR

RD

Instruction
Memory

I
32

RN1

RN2

010

RegDst Operation

WN
RD1

Register File
WD
immediate/
offset
I[15:0]

ALU

Zero

0
M
U
X

RD2
RegWrite

0
Control signals
shown in blue

PCSrc

MUX

16

<<2

16

E
X
T
N
D

1
32

ALUSrc

MemWrite
ADDR

Data
Memory

MemtoReg
1
RD

M
U
X

WD
MemRead

Control Signals:
beq Instruction
ADD

0
M
U
X

ADD
ADD

rs
rt
rd
I[25:21] I[20:16] I[15:11]

PC

Instruction
ADDR

RD

I
32

Instruction
Memory

RN1

RN2

RegDst

110
Operation

WN
RD1

Register File
WD
immediate/
offset
I[15:0]

ALU

Zero

0
M
U
X

RD2
RegWrite

0
Control signals
shown in blue

PCSrc

1 if Zero=1
1

MUX

16

<<2

16

E
X
T
N
D

1
32

ALUSrc

MemWrite
ADDR

Data
Memory

MemtoReg
1
RD

M
U
X

WD
MemRead

Datapath with Control III

Jump

opcode

address

31-26

25-0

Composing jump
target address
Instruction [25 0]
26

Shift
left 2

New MUX added since JUMP Target may replace PC, hence
PC value can now go THREE WAYS.

New multiplexor with additional

control bit Jump

Jump address [31 0]

28

PC+4 [31 28]

ALU
Add result
Add

M
u
x

M
u
x

Shift
left 2

RegDst
Jump

Branch
Instruction [31 26]

MemRead
Control

MemtoReg
ALUOp
MemW rite
ALUSrc
RegWrite

Instruction [25 21]

PC

Read
address

Instruction [20 16]

Instruction
[31 0]

Instruction
memory

Read
register 1

Instruction [15 11]

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

Zero
0
M
u
x
1

Write
data

ALU

ALU
result

Address

Write
data
Instruction [15 0]

16

Sign
extend

Read
data
Data
memory

1
M
u
x
0

32
ALU
control

Instruction [5 0]

MIPS datapath extended to jumps: control unit generates new Jump control bit

Datapath Executing j

R-type Instruction: Step 1

add $t1, $t2, $t3 (active = bold)
0
M
u
x
Add
Add
4
Instruction [31 26]

Control

Instruction [25 21]

PC

Read
address

Instruction
memory

Instruction [15 11]

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1

Instruction [20 16]

Instruction
[31 0]

ALU
result

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Zero
ALU ALU
result

Address

Write
data
Instruction [15 0]

16

Sign
extend

32
ALU
control

Instruction [5 0]

Fetch instruction and increment PC count

Read
data
Data
memory

1
M
u
x
0

R-type Instruction: Step 2

add $t1, $t2, $t3 (active = bold)
0
M
u
x

Add
4
Instruction [31 26]

Control

Instruction [25 21]

PC

Read
address

Instruction
memory

Instruction [15 11]

Zero
ALU ALU
result

Address

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1

Instruction [20 16]

Instruction
[31 0]

ALU
Add result

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Write
data
Instruction [15 0]

16

Sign
extend

32
ALU
control

Instruction [5 0]

Read two source registers from the register file

Read
data
Data
memory

1
M
u
x
0

R-type Instruction: Step 3

add $t1, $t2, $t3 (active = bold)
0
M
u
x

Add
4
Instruction [31 26]

Control

Instruction [25 21]

PC

Read
address

Instruction
memory

Instruction [15 11]

Zero
ALU ALU
result

Address

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1

Instruction [20 16]

Instruction
[31 0]

ALU
Add result

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Write
data
Instruction [15 0]

16

Sign
extend

32
ALU
control

Instruction [5 0]

ALU operates on the two register operands

Read
data
Data
memory

1
M
u
x
0

R-type Instruction: Step 4

add $t1, $t2, $t3 (active = bold)
0
M
u
x

Add
4
Instruction [31 26]

Control

Instruction [25 21]

PC

Read
address

Instruction
memory

Instruction [15 11]

Zero
ALU ALU
result

Address

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1

Instruction [20 16]

Instruction
[31 0]

ALU
Add result

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Write
data
Instruction [15 0]

16

Sign
extend

32

Instruction [5 0]

Write result to register

ALU
control

Read
data
Data
memory

1
M
u
x
0

Single-cycle Implementation Notes

The steps are not really distinct as each instruction

completes in exactly one clock cycle they simply indicate

the sequence of data flowing through the datapath

The operation of the datapath during a cycle is purely

combinational nothing is stored during a clock cycle
Therefore, the machine is stable in a particular state at the
start of a cycle and reaches a new stable state only at the
end of the cycle
Very important for understanding single-cycle computing:

Load Instruction Steps

lw $t1, offset($t2)
1.
2.

3.

4.

5.

Fetch instruction and increment PC

Read base register from the register file: the base
register ($t2) is given by bits 25-21 of the instruction
ALU computes sum of value read from the register file
and the sign-extended lower 16 bits (offset) of the
instruction
The sum from the ALU is used as the address for the
data memory
The data from the memory unit is written into the
register file: the destination register ($t1) is given by
bits 20-16 of the instruction

Load Instruction
lw $t1, offset($t2)
0
M
u
x

Add
4
Instruction [31 26]

Read
address

Instruction
memory

Instruction [15 11]

Zero
ALU ALU
result

Address

Read
register 1

Instruction [20 16]

Instruction
[31 0]

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21]

PC

ALU
Add result

0
M
u
x
1

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Write
data
Instruction [15 0]

16

Instruction [5 0]

Sign
extend

32
ALU
control

Read
data
Data
memory

1
M
u
x
0

Branch Instruction Steps

beq $t1, $t2, offset
1.
2.
3.

4.

Fetch instruction and increment PC

Read two register ($t1 and $t2) from the register file
ALU performs a subtract on the data values from the
register file; the value of PC+4 is added to the signextended lower 16 bits (offset) of the instruction
shifted left by two to give the branch target address
The Zero result from the ALU is used to decide which
adder result (from step 1 or 3) to store in the PC

Branch Instruction
beq $t1, $t2, offset
0
M
u
x

Add
4
Instruction [31 26]

PC

Instruction
[31 0]
Instruction
memory

Read
register 1

Instruction [20 16]

Instruction [15 11]

0
M
u
x
1

Zero
ALU ALU
result

Address

Shift
left 2

RegDst
Branch
MemRead
MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21]

Read
address

ALU
Add result

Read
data 1

Read
register 2
Registers Read
Write
data 2
register

0
M
u
x
1

Write
data

Write
data
Instruction [15 0]

16

Instruction [5 0]

Sign
extend

32
ALU
control

Read
data
Data
memory

1
M
u
x
0

Implementation: ALU Control Block

ALUOp
Funct field
Operation
ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0
0
X X X X X X
010
0
1
X X X X X X
110
1
X
X X 0 0 0 0
010
1
X
X X 0 0 1 0
110
1
X
X X 0 1 0 0
000
1
X
X X 0 1 0 1
001
1
X
X X 1 0 1 0
111
Truth table for ALU control bits
6 variable K Map will be constructed.
ALUOp
ALU control block
ALUOp0
ALUOp1

F3
F2
F (5 0)

Operation2
Operation1

F1
Operation0
F0

ALU control logic

Operation

Implementation: Main Control Block

Inputs
Op5
Op4

Outputs

Inputs

Signal
name

Rlw
format

Op5
0
6-bit
Op4 inst opcode 0
Op3 which is 0
Op2 i/p to main 0
Op1 control 0
Op0
0
RegDst
1
ALUSrc
0
MemtoReg
0
RegWrite
1
MemRead
0
MemWrite
0
Branch
0
ALUOp1
1
ALUOP2
0

1
0
0
0
1
1
0
1
1
1
1
0
0
0
0

sw

beq

Op3
Op2
Op1

1
0
1
0
1
1
x
1
x
0
0
1
0
0
0

0
0
0
1
0
0
x
0
x
0
0
0
1
0
1

Op0

Truth table for main control signals

Outputs
R-format

Iw

sw

beq

RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp2

Main control PLA (programmable

logic array): principle underlying
PLAs is that any logical expression
can be written as a sum-of-products

Single-Cycle Design Problems

Assuming fixed-period clock every instruction datapath uses one

clock cycle implies:

CPI = 1
cycle time determined by length of the longest instruction path
(load)

but several instructions could run in a shorter clock cycle: waste of time

consider if we have more complicated instructions like floating point!

resources used more than once in the same cycle need to be

duplicated

waste of hardware and chip area

Example: Fixed-period clock vs. Variable

period clock in a single-cycle implementation

Consider a machine with an additional floating point unit. Assume

functional unit delays as follows

Assume instruction mix as follows

memory: 2 ns., ALU and adders: 2 ns., FPU add: 8 ns., FPU multiply: 16 ns.,
register file access (read or write): 1 ns.
multiplexors, control unit, PC accesses, sign extension, wires: no delay
all loads take same time and comprise 31%
all stores take same time and comprise 21%
R-format instructions comprise 27%
branches comprise 5%
jumps comprise 2%
FP adds and subtracts take the same time and totally comprise 7%
FP multiplys and divides take the same time and totally comprise 7%

Compare the performance of (a) a single-cycle implementation using a fixedperiod clock with (b) one using a variable-period clock where each instruction
executes in one clock cycle that is only as long as it needs to be (not really
practical but pretend its possible!)

Solution
Instruction
class

Load word
Store word
R-format
Branch
Jump
FP mul/div
FP add/sub

Instr. Register ALU

mem. read
oper.

2
2
2
2
2
2
2

1
1
1
1
1
1

2
2
2
2

Data
mem.

2
2
0

Register FPU
write
add/
sub

FPU
mul/
div

1
1

1
1

16
8

Total
time
ns.

8
7
6
5
2
20
12

Clock period for fixed-period clock = longest instruction time = 20

ns.
Average clock period for variable-period clock = 8 31% +
7 21% + 6 27% + 5 5% + 2 2% + 20 7% + 12 7%
= 7.0 ns.
Therefore, performancevar-period /performancefixed-period = 20/7 = 2.9

Fixing the problem with single-cycle

designs

One solution: a variable-period clock with different cycle

times for each instruction class

unfeasible, as implementing a variable-speed clock is technically

difficult

Another solution:

use a smaller cycle time

have different instructions take different numbers of cycles
by breaking instructions into steps and fitting each step into one
cycle
feasible: multicyle approach!