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Question Bank Subject Code: Ec6302 Subject: Digital Electronics Sem / Year: Iii / Ii-Ece Unit-I Minimization Techniques and Logic Gates Part-A

This document contains a question bank for the subject Digital Electronics in the third semester of the second year of an electronics engineering course. It covers topics like minimization techniques, logic gates, Boolean algebra, combinational circuits, adders, comparators, encoders, decoders, multiplexers and parity generators. The question bank has two parts - Part A contains short answer questions to test basic concepts and Part B contains longer design problems to assess understanding of circuit design principles.

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158 views3 pages

Question Bank Subject Code: Ec6302 Subject: Digital Electronics Sem / Year: Iii / Ii-Ece Unit-I Minimization Techniques and Logic Gates Part-A

This document contains a question bank for the subject Digital Electronics in the third semester of the second year of an electronics engineering course. It covers topics like minimization techniques, logic gates, Boolean algebra, combinational circuits, adders, comparators, encoders, decoders, multiplexers and parity generators. The question bank has two parts - Part A contains short answer questions to test basic concepts and Part B contains longer design problems to assess understanding of circuit design principles.

Uploaded by

mohana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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QUESTION BANK

SUBJECT CODE : EC6302


SUBJECT

: DIGITAL ELECTRONICS

SEM / YEAR

: III / II-ECE
UNIT-I MINIMIZATION TECHNIQUES AND LOGIC GATES

PART-A
1. Define De Morgans theorem.
2. Draw an active high tri-state buffer and write the truth table.
3. What is the significance of high impedance state in tri-state gates?
4. What is totem output?
5. Simplify the following Boolean expression to a minimum number of literals
(BC + AD)(AB + CD)
6. Draw the TTL Inverter NOT circuit.
7. Implement the function using NAND gate only, F = xyz + xy
8. Define fan-In and fan-Out.
9. Simplify the Boolean expression using K-map, F = m 3 + m4 + m6 + m7
10. Obtain the Canonical SOP of the function F = A + BC
11. Define Principle of Duality.
12. State the Limitations of K-map.
13. Which gates are called as the Universal gates? What are its advantages?
14. Find the complement and dual of F = x(yz + yz).
15. Define Propagation delay and Power dissipation.
16. Simplify the Boolean function using K-map method.
F(w,x,y,z) = (0,2,4,6,8,10,12,14)
17. What are the basic digital logic gates?
18. Implement two input exclusive NOR gate using only NAND gate.
19. Implement the given function using NAND gate, F(x,y,z) = (0,6)
20. Define Canonical form. Express F = BC + AC in a canonical SOP form.
PART-B
1.

i) Express the Boolean function F=XY+XZ in Product of Maxterm.

(6)

ii) Reduce the following function using K- Map f(A,B,C,D) = (0,3,4,7,8,10,12,14) +d(2,6).
(10)
2.
3.
4.

Simplify the following Boolean function using Quine Mccluskey Method


F(A,B,C,D)=(0,2,3,6,7,8,10,12,13)+d(1,5,11).
(16)
Simplify the following Boolean function using Quine Mccluskey Method
F(A,B,C,D)=(0,1,2,4,5,6,8,9,10,11,13).
(16)
i) Express the Boolean function as POS form and SOP form for D=(A+B)(B+C). (6)
ii) Discuss the general Characteristics of TTL and CMOS logic Families.

(10)

5.

Reduce the following function using K Map


f(A,B,C,D)=(0,1,2,3,4,6,8,10,12,15,17,19,21,23,24,26,28,30).
Reduce the following function using K Map

(16)

6.
7.

f(A,B,C,D)=(0,2,4,6,7,9,11,13,15,16,18,20,21,23,25,27,29,31).
i) Write short notes on Boolean postulates.

(16)
(8)

ii) Express the Boolean function F=A+BC in sum of min terms and product of max terms.
(8)
8.
9.

Prove that NOR gate is an universal gate. Also prove the same for NAND gate.
(16)
(i)Implement the following with NOR gates F(x,y,z) = (0,6).
(6)
(ii)Draw a CMOS NAND gate and explain its operation. What are the characteristics of

CMOS?
(10)
10. (i)Define Canonical form. Express F = BC + AC in a canonical SOP form and canonical POS
form.
(8)
(ii)Explain about the Tristate gates.
(iii) Implement the Boolean expression using gates. X = (AB + C)D + E.

(5)
(3)

UNIT-II - COMBINATIONAL CIRCUITS


PART-A
1. Give the expression for borrow and difference in full subtractor.
2. Explain the 4 bit odd parity generator.
3. Relate carry generation, carry propagation, sum and carry out of carry look ahead adder.
4. Design a half subtractor.
5. Realize the Boolean function using Multiplexer,
F(A,B,C)= (0,1,3,7)
6. Design a single bit magnitude comparator to compare 2 words A and B.

7. Enumerate some of the combinational circuits.


8. Compare binary serial and parallel adder.
9. Define encoder.
10. List out various applications of Multiplexer.
11. Draw the logic diagram of serial adder.
12. Design the 3 bit even parity generator.
13. Explain about Decoder.
14. What is combinational circuit?
15. Distinguish between decoder and demultiplexer.
16. Draw the logic diagram of gray to binary conversion.
17. Write down the algorithm for BCD addition.
18. What is priority encoder?
19. Draw the logic diagram of full adder.
20. Give the design procedure of combinational circuit.

PART-B
1.
2.
3.
4.
5.
6.
7.
8.

Draw the block schematic of Magnitude Comparator and explain its operations.
(16)
Design a carry look ahead adder with necessary diagrams.
(16)
Design a BCD to Excess 3 code converter and Binary to gray converter.
(16)
i) Design a full adder using two half adders
(5)
(ii) Implement following using multiplexer F(A,B,C,D)=(1,2,4,11,12,13,14,15). (10)
Design a 3X8 decoder and 8X3 encoder with truth table and draw the logic diagram.
(16)
(i) Design a four bit parallel adder/subtractor and draw the logic diagram.
(8)
(ii) Draw the logic diagram of BCD adder and explain its operation.
(8)
(i)Implement full subtractor using demultiplexer.
(10)
(ii) Implement the Boolean function using 8: 1 multiplexer F (A,B,) = (1,3,5,6). (6)
(i)Multiply (1011)2 by (1101)2 using addition and shifting operation also draw block diagram

of the 4-bit by 4 bit parallel multiplier.


(8)
(ii) Design a Half Subtractor and full Subtractor using logic gates.
9. Write short notes on Parity generator and Parity Checkers.
10. Draw the logic diagram of BCD-to-Decimal decoder and explain its operations.

(8)
(16)
(16)

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