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KNL4343 Lecture8

The document discusses sources of capacitance in MOS transistors and interconnect wiring. It explains intrinsic MOS transistor capacitances such as gate-channel and junction capacitances. It also examines extrinsic capacitances such as fan-out and wiring capacitance. The document analyzes how capacitance affects transistor speed and outlines techniques to reduce capacitance like low-k dielectrics and copper interconnects.

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82 views32 pages

KNL4343 Lecture8

The document discusses sources of capacitance in MOS transistors and interconnect wiring. It explains intrinsic MOS transistor capacitances such as gate-channel and junction capacitances. It also examines extrinsic capacitances such as fan-out and wiring capacitance. The document analyzes how capacitance affects transistor speed and outlines techniques to reduce capacitance like low-k dielectrics and copper interconnects.

Uploaded by

yikamnn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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KNL4343

VLSI Design And Technology


Lecture 08: MOS & Wire Capacitances
Norhuzaimin Julai

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

Review: Delay Definitions


Vin

Vout

Vin
Propagation delay
input
waveform

50%

tp = (tpHL + tpLH)/2

tpHL

tpLH

Vout
90%

output
waveform

signal slopes

50%
10%

tf

tr

CMOS Inverter: Dynamic

Transient, or dynamic, response determines the


maximum speed at which a device can be operated.
VDD

Todays focus

Vout = 0
CL

Rn

Vin = V DD

tpHL = f(Rn, CL)

Next lectures focus

Sources of Capacitance
Vout

Vin

Vout2

CL

M2

Vin

CG4
M4

CDB2
Vout

CGD12
M1

Vout2

Cw
CDB1

M3

CG3

intrinsic MOS transistor capacitances


extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance

MOS Intrinsic Capacitances

Structure
Channel

capacitances

capacitances

Depletion

regions of the reversebiased pn-junctions of the drain and


source

MOS Structure Capacitances


lateral diffusion

Top view

Source
n+

Poly Gate
xd

xd

Drain
W n+

Ldrawn

n+

Leff

tox
n+

Overlap capacitance (linear)


CGSO = CGDO = Cox xd W = Co W

MOS Channel Capacitances

The gate-to-channel capacitance depends upon


the operating region and the terminal voltages

CGS = CGCS + CGSO

CGD = CGCD + CGDO

VGS

n+

n channel

n+

CGB = CGCB
p substrate

depletion
region

Review: Summary of MOS Operating Regions

Cutoff (really subthreshold) VGS VT

Exponential in VGS with linear VDS dependence


ID = IS e (qVGS/nkT) (1 - e -(qVDS/kT) ) (1 - VDS) where n 1

Strong Inversion VGS > VT

Linear (Resistive) VDS < VDSAT = VGS - VT


ID = k W/L [(VGS VT)VDS VDS2/2] (1+VDS) (VDS)

Saturated (Constant Current) VDS VDSAT = VGS - VT


IDSat = k W/L [(VGS VT)VDSAT VDSAT2/2] (1+VDS) (VDSAT)

NMOS

VT0(V)
0.43

(V0.5)
0.4

VDSAT(V)
0.63

k(A/V2)
115 x 10-6

(V-1)
0.06

PMOS

-0.4

-0.4

-1

-30 x 10-6

-0.1

Average Distribution of Channel Capacitance


Operation
Region

CGCB

CGCS

CGCD

CGC

CG

Cutoff

CoxWL

CoxWL

CoxWL +
2CoW

Resistive

CoxWL/2

CoxWL/2

CoxWL

CoxWL +
2CoW

Saturation

(2/3)CoxWL

(2/3)CoxWL (2/3)CoxWL +
2CoW

Channel capacitance components are nonlinear and


vary with operating voltage
Most important regions are cutoff and saturation
since that is where the device spends most of its time

MOS Diffusion Capacitances

The junction (or diffusion) capacitance is from the


reverse-biased source-body and drain-body pn-junctions.
G
VGS

n+

n channel

n+

p substrate

CSB = CSdiff

depletion
region

CDB = CDdiff
B

Source Junction View


channel-stop
implant (NA+)

source
bottom plate
(ND)

junction xj
depth

channel
side walls

substrate (NA)

LS
Cdiff = Cbp + Csw = Cj AREA + Cjsw PERIMETER
= Cj LS W + Cjsw (2LS + W)

Review: Reverse Bias Diode

All diodes in MOS digital circuits are reverse


biased; the dynamic response of the diode
+
is determined by depletion-region charge or VD
junction capacitance
Cj = Cj0/((1 VD)/0)m
where Cj0 is the capacitance under zero-bias conditions (a
function of physical parameters), 0 is the built-in potential
(a function of physical parameters and temperature)
and m is the grading coefficient

m = for an abrupt junction (transition from n to p-material is


instantaneous)
m = 1/3 for a linear (or graded) junction (transition is gradual)

Nonlinear dependence (that decreases with increasing


reverse bias)

Reverse-Bias Diode Junction Capacitance


2

abrupt (m=1/2)

Cj (fF)

1.5
1

linear (m=1/3)

0.5

Cj0

0
-5

-4

-3

-2
-1
VD (V)

MOS Capacitance Model

CGS = CGCS + CGSO

CGD = CGCD + CGDO

CGS

CGD

CSB
CSB = CSdiff

CGB
B
CGB = CGCB

CDB

CDB = CDdiff

Transistor Capacitance Values for 0.25


Example: For an NMOS with L = 0.24 m, W = 0.36 m,
LD = LS = 0.625 m
CGSO = CGDO = Cox xd W = Co W = 0.11 fF
CGC = Cox WL = 0.52 fF
so Cgate_cap = CoxWL + 2CoW = 0.74 fF
Cbp = Cj LS W = 0.45 fF
Csw = Cjsw (2LS + W) = 0.45 fF
so Cdiffusion_cap = 0.90 fF

NMOS
PMOS

Cox

Co

Cj

(fF/m2)

(fF/m)

(fF/m2)

6
6

0.31
0.27

2
1.9

Cjsw

(V)

(fF/m)

0.5 0.9
0.48 0.9

0.28
0.22

mj

mjsw

bsw
(V)

0.44
0.32

0.9
0.9

Review: Sources of Capacitance


Vout

Vin

Vout2

CL
CG4

M2

Vin

CGD12pdrain

M4

CDB2

ndrain

CDB1
M1

Vout

Vout2

Cw
M3

CG3

intrinsic MOS transistor capacitances


extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance

Gate-Drain Capacitance: The Miller Effect

M1 and M2 are either in cut-off or in saturation.

The floating gate-drain capacitor is replaced by a


capacitance-to-ground (gate-bulk capacitor).

CGD1
Vin

V
M1

Vout

Vout

2CGB1

V
Vin

M1

A capacitor experiencing identical but opposite voltage


swings at both its terminals can be replaced by a
capacitor to ground whose value is two times the original
value

Drain-Bulk Capacitance: Keqs (for 2.5 m)

We can simplify the diffusion capacitance calculations


even further by using a Keq to relate the linearized
capacitor to the value of the junction capacitance under
zero-bias
Ceq = Keq Cj0

NMOS
PMOS

high-to-low
Keqbp
Keqsw
0.57
0.61
0.79
0.86

low-to-high
Keqbp
Keqsw
0.79
0.81
0.59
0.7

Extrinsic (Fan-Out) Capacitance

The extrinsic, or fan-out, capacitance is the total gate


capacitance of the loading gates M3 and M4.

Cfan-out = Cgate (NMOS) + Cgate (PMOS)


= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox)

Simplification of the actual situation

Assumes all the components of Cgate are between Vout and GND
(or VDD)
Assumes the channel capacitances of the loading gates are constant

Layout of Two Chained Inverters


VDD

PMOS
1.125/0.25
1.2m
=2

Out

In

Metal1

Polysilicon

0.125

0.5
NMOS
0.375/0.25

W/L
AD (m2)
NMOS 0.375/0.25
0.3
PMOS 1.125/0.25
0.7

GND

PD (m)
1.875
2.375

AS (m2) PS (m)
0.3
1.875
0.7
2.375

Components of CL (0.25 m)
Expression

Value (fF) Value (fF)


HL
LH
0.23
0.23

C Term
CGD1

2 Con Wn

CGD2

2 Cop Wp

0.61

0.61

CDB1

KeqbpnADnCj + KeqswnPDnCjsw

0.66

0.90

CDB2

KeqbppADpCj + KeqswpPDpCjsw

1.5

1.15

CG3

(2 Con)Wn + CoxWnLn

0.76

0.76

CG4

(2 Cop)Wp + CoxWpLp

2.28

2.28

Cw

from extraction

0.12

0.12

CL

6.1

6.0

Wiring Capacitance

The wiring capacitance depends upon the length and


width of the connecting wires and is a function of the
fan-out from the driving gate and the number of fan-out
gates.

Wiring capacitance is growing in importance with the


scaling of technology.

Parallel Plate Wiring Capacitance


current flow

L
electrical field lines
W
H
tdi

dielectric (SiO2)
substrate

permittivity
constant
(SiO2= 3.9)

Cpp = (di/tdi) WL

Permittivity Values of Some Dielectrics


Material
Free space
Teflon AF
Aromatic thermosets (SiLK)
Polyimides (organic)
Fluorosilicate glass (FSG)
Silicon dioxide
Glass epoxy (PCBs)
Silicon nitride
Alumina (package)
Silicon

di
1
2.1
2.6 2.8
3.1 3.4
3.2 4.0
3.9 4.5
5
7.5
9.5
11.7

Sources of Interwire Capacitance


Cwire = Cpp + Cfringe + Cinterwire
= (di/tdi)WL
+ (2di)/log(tdi/H)
+ (di/tdi)HL

fringe
interwire
pp

Impact of Fringe Capacitance

H/tdi = 1
H/tdi = 0.5
Cpp

W/tdi

(from [Bakoglu89])

Impact of Interwire Capacitance

(from [Bakoglu89])

Insights

For W/H < 1.5, the fringe component dominates the


parallel-plate component. Fringing capacitance can
increase the overall capacitance by a factor of 10 or more.

When W < 1.75H interwire capacitance starts to dominate

Interwire capacitance is more pronounced for wires in the


higher interconnect layers (further from the substrate)

Rules of thumb

Never run wires in diffusion


Use poly only for short runs
Shorter wires lower R and C
Thinner wires lower C but higher R

Wire delay nearly proportional to L2

Wiring Capacitances
Poly
Al1
Al2
Al3

Al4
Al5

Field
88
54
30
40
13
25
8.9
18
6.5
14
5.2
12

Interwire Cap

Active

41
47
15
27
9.4
19
6.8
15
5.4
12

Poly

57
54
17
29
10
20
7
15
5.4
12

Al1

Al2

Al3

Al4

pp in aF/m2
fringe in aF/m
36
45
15
27
8.9
18
6.6
14

41
49
15
27
9.1
19

35
45
14
27

38
52

Poly

Al1

Al2

Al3

Al4

Al5

40

95

85

85

85

115

per unit wire length in aF/m for minimally-spaced wires

Dealing with Capacitance

Low capacitance (low-k) dielectrics (insulators) such


as polymide or even air instead of SiO2

family of materials that are low-k dielectrics


must also be suitable thermally and mechanically and
compatible with (copper) interconnect

Copper interconnect allows wires to be thinner without


increasing their resistance, thereby decreasing
interwire capacitance

SOI (silicon on insulator) to reduce junction


capacitance

Next Time: Dealing with Resistance

MOS structure resistance - Ron

Wiring resistance

Contact resistance

Next Lecture and Reminders

Next lecture

MOS resistance
- Reading assignment Rabaey, et al, 4.3.2, 4.4.1-4.4.4

Reminders

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