E&C-ENGR 5535

Verilog HDL
Lecture 02
Chapter 02

Course Overview
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Introduction
Language Elements
Language Expressions
Gate-Level Modeling
User-Defined Primitives
Dataflow Modeling
Behavioral Modeling
Structural modeling
Task and Functions

Chaudhry-Lecture 02, Ch. 02

Chapter Overview
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Design Methodologies
Verilog Modules and Ports
Styles of Verilog Modeling
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Dataflow Modeling
Behavioral Modeling
Structural Modeling
Mixed-Design Modeling

Chaudhry-Lecture 02, Ch. 02

INCREASING ABSTRACTION

LEVEL

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CHIP

STRUCTURAL

BEHAVIORAL

CPUs RAM, ROM, UART

PERFORMANCE
I/O RESPONSE
ALGORITHMS
OPERATIONS

PARALLEL PORT

REGISTERS, ALUs
REGISTER
COUNTERS, MUXES

TRUTH TABLES
STATE TABLES
OPERATIONS

GATE

GATES, FLIP-FLOPS

BOOLEAN EQUATIONS

CIRCUIT

TRANSISTORS, RLC

DIFFERENTIAL EQUATIONS

SILICON

GEOMETRICAL
OBJECTS

Chaudhry-Lecture 02, Ch. 02

INCREASING DETAIL

Design Abstractions in VLSI Circuits

---

Verilog Built-In Primitives

!

Verilog has 26 built-in Primitives

Combinational Three MOS CMOS Bi-Directional
Pull
Logic
State Gates Gates
Gates
Gates
and
bufif0 nmos cmos
tran
pullup
pmos
rcmos
nand
bufif1
tranif0
pulldown
or
notif0 rnmos
tranif1
nor
notif1 rpmos
rtran
xor
rtranif0
xnor
rtranif1
buf
not

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Propagation delay can be assigned on instance base

Chaudhry-Lecture 02, Ch. 02

Schematic Design
Schematics display the structure of a design.
Main focus on structural details of the design.
Efficient at small design level.

C_out_bar
C_out

Sum

Add_half
b

C_out

sum = a b

a
b

sum

c_out = a b
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Chaudhry-Lecture 02, Ch. 02

Verilog HDL: Design of a Flip-Flop

module flip_flop ( q, data_in, clk, rst );
input
data_in, clk, rst;
output
q;
reg
q;
always @ ( posedge clk )
begin
if ( rst == 1) q = 0;
else q = data_in;
end
endmodule
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rst
data_in

clk

Declaration of synchronous behavior

Procedural statement

Chaudhry-Lecture 02, Ch. 02

Design Methodologies
!

Two main types of design

methodologies:
!
!

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Top-Down Design
Bottom-Up Design

Chaudhry-Lecture 02, Ch. 02

Design Methodologies: Top-Down

!

The top level block is identified, then the blocks in

the next lower level until all levels in the structure
have been defined.
Top-Level Block

2nd Level Block

Bottom-Level
Block: Leaf

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Bottom-Level
Block: Leaf

2nd Level Block

Bottom-Level
Block: Leaf

Bottom-Level
Block: Leaf

Chaudhry-Lecture 02, Ch. 02

2nd Level Block

Bottom-Level
Block: Leaf

Bottom-Level
Block: Leaf

Design Methodologies: Bottom-Up

!

The lowest level contains the leaf cells, is defined

first and considered as building blocks to design
next higher level.
Top-Level Block

2nd Level Block

Bottom-Level
Block: Leaf

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Bottom-Level
Block: Leaf

2nd Level Block

Bottom-Level Bottom-Level
Block: Leaf
Block: Leaf

Chaudhry-Lecture 02, Ch. 02

2nd Level Block

Bottom-Level Bottom-Level
Block: Leaf
Block: Leaf

10

Example 01: Modulo-16

Synchronous Counter (Top-Down)
Modulo-16 synchronous counter using D
flip-flops
! An Illustration of top-down design approach
! The counting sequence is:
!

y3y2y1y0 = 0000, 0001, 0010, 0011, 0100, 0101, 0110,

0111, 1000, 1001, 1010, 1011, 1100, 1101,
1110, 1111, 0000, .

where yi is the name of the flip-flop.

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Chaudhry-Lecture 02, Ch. 02

11

Example 01: Modulo-16

Synchronous Counter: Schematic
!

It contain four D flip-flops, y3y2y1y0

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Chaudhry-Lecture 02, Ch. 02

12

Example 01:Modulo-16 Synchronous

Counter: Excitation Tables
!

After developing the

truth table out of
counter sequence,
0000, 0001, 0010,.. ,
We draw the
excitation tables for
each flip-flop to get
the function controlling
equation, usually
called as logic
equations for each D
flip-flop.

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Chaudhry-Lecture 02, Ch. 02

13

Example 01 : Modulo-16 Synchronous

Counter: Logical Equations
!

Logical Equations:
Dy3 = y3y2 + y3y1 + y3y0
+ y3y2y1y0
Dy2 = y2y1 + y2y0 + y2y1y0
Dy1 = y1y0 + y1y0
Dy0 = y0

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Chaudhry-Lecture 02, Ch. 02

14

Example 02: 4-Bit Ripple Adder:

Top-Down
!

An other top-down design example, in which carry

ripples from one adder to the next adder.

Sum = abcin + abcin

+ abcin + abcin
= a b cin

Cout = ab + (a b)cin

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Chaudhry-Lecture 02, Ch. 02

15

What Verilog Modules Show?

!

Description of internal
structure/function
!

Communicate with
outside through ports
!
!

Implicit semantic of time

associated with each data
object/signal
Implementation is hidden to
outside world

Output ports at the left

Port list is optional

Achieve hardware
encapsulation

module Add_half (sum, c_out, a, b);

input a, b;
output sum, c_out;
wire
c_out_bar;
xor (sum, a, b);
nand (c_out_bar, a, b);
not (c_out, c_out_bar);
endmodule

a
b

sum
c_out_bar
c_out

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Chaudhry-Lecture 02, Ch. 02

16

Modules and Ports

!

General Structure of a Verilog module

module <module name> (port list);
reg, wire, parameter
input ...;
output ;
<module internals>
initial, always,
module instantiations,..
.
endmodule

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//declarations

// other statements

Chaudhry-Lecture 02, Ch. 02

17

Module Instantiation
!

Accomplished by entering:
!
!

!
!

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Module name as a module item within a parent

module
Signal identifiers at appropriate ports

Module instantiation needs a module identifier

A module is never declared within another
module
The order of ports in instantiation usually
matches the order in module declaration

Chaudhry-Lecture 02, Ch. 02

18

Modeling with Primitives

!

Helps to model pre-defined hardwarebased behavior;

!
!
!

Built-in Primitives or Pre-Defined Primitives

All Pre-Defined Primitives are Combinational
The output of Combinational Primitives must
be of type net
The input of any Primitive can be of type
net or register

Verilog supports Combinational and

Sequential User-Defined Primitive (UDP)

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Chaudhry-Lecture 02, Ch. 02

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Characteristics of Verilog Primitives

Basic element to build a module, such as
nand, nor, buf and not gates
! Never used stand-alone in design, must
be within a module
! They may be Pre-defined or User-defined
! Identifier (instance name) is optional
!

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Chaudhry-Lecture 02, Ch. 02

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Smart Primitives
module nand3 (O, A1, A2, A3);
input
A1, A2, A3;
output
O;
nand (O, A1, A2, A3);
endmodule
Smart Primitives: Same primitive can be used to
describe for any number of inputs
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Chaudhry-Lecture 02, Ch. 02

21

Types of Delays and Times

!

Delays can be defined in variety of ways:

!

Symmetrical Delays
! All the delays are uniform
! Default Delay = 0
Asymmetrical Delays
! Min Delay
! Typical Delay
! Max Delay

Times
!
!

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Rising Time (T01)

Falling Time (T10)
Chaudhry-Lecture 02, Ch. 02

22

Symmetric Delay Assignment

module AOI_4 (y, x1, x2, x3, x4);
input
x1 , x 2 , x 3 , x 4 ;
output y;
wire
y1, y2;
and #1 (y1, x1, x2);
and #1 (y2, x3, x4);
nor #1 (y, y1, y2);
endmodule

x1
x2
x3
x4

y1
y
y2

AOI => And OR Invert

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Chaudhry-Lecture 02, Ch. 02

23

Asymmetric Delay Assignment

module nand1 (O, A, B);
input
A, B;
output
O;
nand
(O, A, B);
specify
specparam
T01 = 1.13:3.09:7.75;
T10 = 0.93:2.50:7.34;
(A=>O) = (T01, T10);
(B=>O) = (T01, T10);
endspecify
endmodule
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Min delay
Typical delay
Max delay

Falling time
Rising time

Chaudhry-Lecture 02, Ch. 02

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Construct Definitions
!

Continuous Assignment:
To describe combinational logic where the output of the circuit is
evaluated whenever an input changes:

assign [delay] lhs_net = rhs_expression; (lhs = left hand side)

!

Procedural Continuous Assignment:

Made within a behavioral construct (initial or always) and

creates a dynamic binding to a variable.
!

Blocking Statement (=):

The assignment to LHS variable takes place before the following
statement in the sequential block.
Nonblocking Statement (=>):
Allows scheduling of assignments without blocking execution of the
statements that follow in a sequential block.

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Chaudhry-Lecture 02, Ch. 02

25

Example: Verilog module for

2-input AND Gate
!

Dataflow and 2 input and gate

module and2 (x1, x2, z1);
input
x1, x2;
output
z1;
wire
x1, x2;
wire
z1;
assign z1 = x1 & x2;
endmodule

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Chaudhry-Lecture 02, Ch. 02

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Example: TB
for 2-input
and Gate
(Cont)

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Chaudhry-Lecture 02, Ch. 02

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Example: Output and Waveforms for

2-Input AND Gate (Cont)

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Chaudhry-Lecture 02, Ch. 02

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Styles of Verilog Modeling

Dataflow Modeling:

Used to design combinational logic only.

It implements logical function at a high level of
abstraction using built-in primitives
Example:
assign z1 = x1 & x2;

!
!

Behavioral Modeling:

Build a behavioral module by:

!
1.
2.

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Writing continuous assignment statements, or

Declaring Verilog behaviors

Chaudhry-Lecture 02, Ch. 02

29

Styles for Modeling (Cont)

Structural Modeling:

!
!

Build a structural model by instantiating primitives

and/or other modules within a module declaration,
and interconnect with nets.

Mixed-Design Modeling:

!
!

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Incorporates different modeling styles in the same

module.
This includes gate and module instantiations as
well as continuous assignments and behavioral
constructs.
Chaudhry-Lecture 02, Ch. 02

30

Examples: Dataflow Modeling

1.
2.

Two-input Exclusive-OR gate

Four 2-Input AND Gates with scalar input and a
vector output
Example 1:

module xor2 (x1, x2, z1);

input
x 1 , x2 ;
output z1;
wire
x 1 , x2 ;
wire
z 1;

+X1
+X2

+Z1

assign z1 = x1 ^ x2;
endmodule
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Chaudhry-Lecture 02, Ch. 02

31

Example 1: TB for 2-input XOR Gate

(Cont)

Prints the argument

values within
quotation marks

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Chaudhry-Lecture 02, Ch. 02

32

Example 1: Outputs and Waveforms

for 2-Input XOR Gate (Cont)

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Chaudhry-Lecture 02, Ch. 02

33

Time Units
!

Timescale: The actual unit of time is specified

by the timescale compiler directive.
For example, the statement
timescale 10ns /100ps
indicates that one time unit is specified as 10ns
with a precision of 100ps.
This property is called inertial delay.

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Chaudhry-Lecture 02, Ch. 02

34

Example 2: Four 2-Input AND Gates with

Scalar Input and a Vector Output
!

//dataflow modeling
timescale 10ns/1ns
module four_and_delay (z1, x1, x2);
input x1, x2; output
z 1;
wire x1, x2; wire [3:0] z1;
assign #2
assign #2
assign #2
assign #2
endmodule

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z1[0] = ~x1 & ~x2 ;

z1[1] = ~x1 & x2 ;
z1[2] = x1 & ~x2 ;
z1[3] = x1 & x2 ;

Chaudhry-Lecture 02, Ch. 02

-X1
-X2

+Z1[0]

-X1
+X2

+Z1[1]

+X1
-X2

+Z1[2]

+X1
+X2

+Z1[3]

When input x1 or x2
changes value, the value
of right-hand statement is
assigned to the left-hand
after a delay of 20ns.
35

Example 2: TB for Four 2-Input

AND Gates (Cont)
module four_and_delay (z1,x1,x2);
wire x1, x2;
wire [3:0] z1;
initial
$monitor (x1, x2 = %b, z1 =
%b, {x1, x2}, z1);
initial begin
#0
x1 = 1b 0;
x2 = 1b 0;
#5
x1 = 1b1;
x2 = 1b 0;
#5
x1 = 1b1;
x2 = 1b1;
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#5

x1 = 1b 0;
x2 = 1b 1;
#5 x1 = 1b 0;
x2 = 1b 1;
#5 x1 = 1b 0;
x2 = 1b 0;
#5 $stop;
end
four_and_delay Inst1 (
. x1 (x1), . x2 (x2), . z1 (z1), );
endmodule

Chaudhry-Lecture 02, Ch. 02

36

Example 2: Waveforms for Four 2Input AND Gates (Cont)

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Chaudhry-Lecture 02, Ch. 02

37

Summary
!

What we discussed today;

!
!

Types of Verilog modeling

Types of design approaches
!
!

!
!
!
!

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Top-down
Bottom-up

Modules and Ports

Types of Delays & Times
Time Units
Data Flow Modeling

Chaudhry-Lecture 02, Ch. 02

38

Questions?

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Chaudhry-Lecture 02, Ch. 02

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