CS623 – CAD for VLSI

Lecture 37 – Synthesis II
Shankar Balachandran
Dept. of Computer Science and Engineering
IIT-Madras
[email protected]

3/15/2006 1
Recap - Synthesis
• Three things are needed
– Verilog Model
– Constraints on the circuit
• Area
• Delay
– Library Models
• What kind of components we have?
• How are they characterized for area, delay etc?

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Recap - Verilog as a Synthesis Language
• Verilog is primarily a simulation language
• Features of Verilog
– Describe hardware at Behavioral, RTL and Gate
level
– Create Test Stimulus
– Error checking on the model and its usage
– File I/O

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Recap - Focus on Synthesis
Synthesis Simulatable
Tool X Verilog

Goal of
the
course

Synthesis Synthesis
Tool Y Tool Z
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Recap - Synthesis Flow
• Basic synthesis steps are:
– Analyze
– Elaborate
– Compile
– Report
– Save
• Basic steps are subject to constraints and
options

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Recap - Timing Report

Point Incr Path

-----------------------------------------------------------
clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
COUNT_reg<0>/CP (FJK2S) 0.00 0.00 r
COUNT_reg<0>/Q (FJK2S) 2.08 2.08 r
U57/Z (ND2) 0.30 2.38 f
U55/Z (NR2) 1.07 3.45 r
U54/Z (EO) 1.13 4.57 f
COUNT_reg<3>/TI (FJK2S) 0.00 4.57 f
data arrival time 4.57

clock CLK (rise edge) 10.00 10.00

clock network delay (ideal) 0.00 10.00
COUNT_reg<3>/CP (FJK2S) 0.00 10.00 r
library setup time -1.80 8.20
data required time 8.20
-----------------------------------------------------------
data required time 8.20
data arrival time -4.57
-----------------------------------------------------------
slack (MET) 3.63

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Recap - Area Report
****************************************
Report : area
Design : SM_COUNT

****************************************

Library(s) Used:

lsi_10k (File:
/software/synopsys/1998.02/libraries/syn/lsi_10k.db)

Number of ports: 7
Number of nets: 19
Number of cells: 12
Number of references: 5
Combinational area: 14.000000
Noncombinational area: 52.000000
Net Interconnect area: undefined
(No wire load specified)
Total cell area: 66.000000
Total area: undefined

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Verilog Style for Synthesis
• Verilog coding style is very important for
synthesis
• Hardware corresponds to RTL
– This may be overkill as the synthesis tools can
handle behavioral abstractness
• Hardware structure must be clear for the tool to
understand!
• RTL style allows behavioral abstractions such
as always, integer and parameter types, and
most arithmetic operators

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Verilog Style for Synthesis
• Some elements of Verilog may not be handled
although capabilities improve as tools evolve.
• Verilog allows several ways to describe one thing,
Synthesis tools often require only a limited subset of
constructs; Example: Registers and Flip Flops must be
described in a certain way

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Example Verilog Code
module load_n_select (input CLK, input LOAD_EN, input
[3:0] DATA, input [3:0] SEL_CODE, output RESULT);

reg [3:0] DATA_Q;

always @(posedge CLK)

if (LOAD_EN == 1’b1) DATA_Q <= DATA;

always @(SEL_CODE or DATA_Q)

case SEL_CODE
0 : RESULT <= DATA_Q(0);
1 : RESULT <= DATA_Q(1);
2 : RESULT <= DATA_Q(2);
3 : RESULT <= DATA_Q(3);
default : RESULT <= DATA_Q(0);
endcase

endmodule

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Inference of Hardware
• Two always blocks
correspond to the intended SEL_IN
LOAD_EN DATA
two hardware blocks
• Inferred flip-flop as a
clocked process
CLK
• Combinational process has DATA_Q
all input signals in the
sensitivity list; If not, may
lead to differences in
simulation vs. synthesis
results

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Categories of Verilog Constructs
• Categories of applicability for synthesis tools:
– Ignored - Many constructs are ignored with no error
messages
– Not Supported - Some constructs produce error
messages
– Supported with constraints -Many constructs are
supported but in certain forms produce error
messages
– Fully supported - Generally allowed in all forms

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Constructs – Not Supported
real x;
BEGIN
x <= x/3.0;
--Error: Literal ’of type REAL’ is
--not supported for synthesis

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Constructs – Supported With Restrictions
c <= a/5; --Error: The second operand must
--be a power of two

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Constructs - Ignored
initial
begin
a = 10;
b = 15;
end
-- Warning: initial statements are not supported in
synthesis
always @(a or b)
#5 C <= A + B;
-- Warning: Assignment delays are not
-- supported for synthesis. They are
-- ignored.
$display(“C = %d”,C);
-- Warning: Display statements are not
-- supported for synthesis. They are
-- ignored.
END

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Restricting Ranges
• Some very simple Verilog code can generate
large amounts of circuitry.
integer a,b,c;
always @(a or b) C = A * B;

• If A = 0 to 7 and B = 0 to 7, C = 0 to 49
• The code will compile quickly with no
warnings or errors, but will take hours to
convert into gates.
– The type integer implies 32 bits.
• The range of values should always be specified.

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Restricting Ranges
• The implementation shown below gives
identical results as the previous integer
version and has the advantage of a
standard port interface. It also makes the
range more obvious.
module math_test (input [2:0] a, input
[2:0] b, output [2:0] c);
always @(a or b)
c <= a * b;
endmodule

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Sensitivity List
• Combinational blocks should have all
inputs in the sensitivity list
always @(B or C) Tool X: Error, A should be
BEGIN declared on the sensitivity list of
IF A == 1’b1
the process. Error found in
Y <= B & C;
ELSE
Verilog source Synthesis Failed.
Y <= B | C;
Tool Y: Warning: Variable ’A’ is
end
END being read ... but is not in the
process sensitivity list of the
block
Important : Simulation Synthesis
Mismatch

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Another Tool

C
Y
A

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Logic Eqns Vs Gates
ƒ Sometimes what you expect is not what you get in gates
module simple (input A, input B, input C, output Y);
assign Y = (A AND B) OR C;
endmodule

ƒ One would expect an implementation of one AND gate and one OR

gate; Instead the synthesis tool selected differently

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Influence of Loading

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Tristate
module design (C, C_EN, D, D_EN, y);
input C, C_EN, D, D_EN;
output Y;

always @(C_EN or C)
BEGIN
IF (C_EN == 1’b1) Y <= C;
ELSE Y <= 1’bz;
END

always @(D_EN or D)
BEGIN
IF (D_EN == 1’b1) Y <= D;
ELSE Y <= 1’bz;
END

endmodule

•Assignment of ‘Z’ infers a tri-state

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Trimmed Logic
module design (input IN1, output OUT1);
OUT1 <= IN1;
endmodule

module design (inpu IN1, input IN2);

wire A;

assign a = IN1 ^ IN2;

endmodule

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Miscellaneous
• Masking of unsupported constructs using
special format Verilog comments:
// synopsys synthesis_off
<unsupported Verilog code>
// synopsys synthesis_on

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Inference of Hardware
• A correct hardware model for the given Verilog
code
• Not a simple process
– Many ways of modeling the same thing
• Eg. If-Then-Else vs. Case
– What hardware structure?
– Order of Verilog code Vs. Synthesized Hardware

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Simple Ways to Infer
• Infer from Declarations
– Data types and ranges are available
• Infer from signal assignments
– A data flow view
• From Verilog statements
– If-then, Case, Loops etc
• Registers, Flip-Flops
• State Elements and State Machine Synthesis

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Post-Synthesis Simulation
• We get actual delays and area after synthesis
• Can verify the transformation
• Verify the design for timing
– In terms of library cells from target library – Gives
more confidence

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