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EC2354 - Nov 2011 - AU QP Anna University Exams - VLSI

This document outlines the syllabus for a testing and testability exam for an electronics engineering course. It lists 8 questions that could be answered for the exam, covering topics like fault modeling, ATPG, scan architectures, design for test approaches, self-test, memory testing, JTAG, and hazard detection. It provides the date, time duration, maximum marks, and instructions to answer any 5 questions out of the 8 listed.

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SHARANYA
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128 views

EC2354 - Nov 2011 - AU QP Anna University Exams - VLSI

This document outlines the syllabus for a testing and testability exam for an electronics engineering course. It lists 8 questions that could be answered for the exam, covering topics like fault modeling, ATPG, scan architectures, design for test approaches, self-test, memory testing, JTAG, and hazard detection. It provides the date, time duration, maximum marks, and instructions to answer any 5 questions out of the 8 listed.

Uploaded by

SHARANYA
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Code :9D55201M.

Tech II Semester Supplementary Examinations, April 2011TESTING &


TESTABILITY
(For students admitted in 2009-2010)(Common to VLSI Systems,VLSI Systems Design,
VLSI & VLSID, Embedded Systems)
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Answer any FIVE questionsAll questions carry equal marks

1. (a) Describe the concepts of modeling & digital circuits at logic level
& register level. (b) Explain any two delay models.2. (a) Describe with the help of
examples single struck & multiple struck fault models. (b) Explain any two
fault simulation applications.3. (a) Explain ATPG for SSFs in sequential circuits.
(b) How do you select ATPG tool? Explain.4. (a) With the help of neat block
diagram, explain the scan Architectures & Testing.(b) How do you perform
generic boundary scan?5. (a) Explain board level & s ystem level DFT
approaches.(b) What is meant by signature analysis? Explain.6. (a) Explain the
advanced concept & design for self-test at board level.(b) What is STUMPS?
Describe.7. (a) List & explain any two types of memories & integration.
(b) Explain the memory test architecture.8. Write short notes on the following:(a) JTAG
testing feature.(b) Hazard detection.(c) RTS.

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EC2354 _ Nov 2011_AU QP Anna University Exams - VLSI

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011. Sixth


Semester Electronics and Communication Engineering EC 2354

VLSI DESIGN (Regulation 2008) (Common to PTEC 2354

VLSI Design for B.E. (Part-Time) Fifth Semester Electronics and Communication Engineering,
Regulation 2009) Time : Three hours Maximum : 100 marks Answer ALL questions.
PART A

(10 2 = 20 marks)
1. Determine whether an NMOS transistor with a threshold voltage of 0.7 V is operating in
thesaturation region if GS V = 2 V and =DS V 3V. 2. Write down the equation for describing the
channel length modulation effect in NMOStransistors. 3. Write the expressions for the logical
effort and parasitic delay of n input NOR gate. 4. Why does interconnect increase the circuit
delay? 5. Draw a pseudo NMOS inverter. 6. What are the advantages of differential flip flops? 7.
State the objective of functionality test. 8. What are the test fixtures required to test a chip? 9.
Write the Verilog module for an half adder. 10. What are the delay specifications available in
Verilog HDL for modeling a logic gate?
PART B

(5 16 = 80 marks)
11. (a) (i) An NMOS transistor has the following parameters : gate oxide thickness = 10
nm,relative permittivity of gate oxide = 3.9, electron mobility = 520 2 cm /V-sec, threshold
voltage =
0.7 V, permittivity of free space = 14 10 85 . 8 F/cm and (W/L) = 8. Calculate the drain
current when ( GS V = 2 V and = DS V 1.2 V) and ( GS V = 2 V and = DS V 2 V) and
alsocompute the gate oxide capacitance per unit area. Note that W and L refer to the width
andlength of the channel respectively. (3 + 3 +(ii) Draw and explain the DC and transfer
characteristics of a CMOS inverter with necessaryconditions for the different regions of
operation. (8) Or (b) (i) Explain the gate, source/drain formation and isolation steps of CMOS
fabrication processwith neat diagrams. (8) (ii) Give a brief note on the different process
techniques to enhance the performance of CMOStransistors. (8)

12. (a) (i) Explain the static and dynamic power dissipation in CMOS circuits with
necessarydiagrams and expressions. (10) (ii) Discuss the principle of constant field scaling and
also write its effect on devicecharacteristics . (6) Or (b) (i) Explain the different reliability

problems related to the design of reliable CMOS chips.(10) (ii) Give a brief account on design
margin. (6) 13. (a) (i) Describe the basic principle of operation of dynamic CMOS, domino and
NP dominologic with neat diagrams (12) (ii) Write the basic principle of low power logic design
(4) Or (b) (i) Compare the sequencing in traditional domino and skew tolerant domino circuits
withneat diagrams. (8) (ii) Explain the problem of metastability with neat diagrams and
expressions. (8) 14. (a) Explain the manufacturing test principles in detail. (16) Or (b) Describe
the adhoc testing and scan based approaches to design for testability in detail.(16)15. (a) (i) Draw
the three input CMOS NOR and NAND gates and write the Verilog switch levelmodeling for
both. (10) (ii) Explain the continuous and implicit continuous assignment with two
suitableexamples for each. (6) Or (b) (i) Draw the logic diagram of 4 to 1 MUX using NAND
gates and write the gate levelmodeling using Verilog HDL. (8) (ii) Give a brief note on the
looping statements available in Verilog HDL and write a verilogcode for D Latch. (6 + 2)

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