0% found this document useful (0 votes)
62 views3 pages

Referen

A. Tiwari et al., "ReCycle: Pipeline Adaptation to Tolerate Process Variation" "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency"

Uploaded by

Sannena Govinda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
62 views3 pages

Referen

A. Tiwari et al., "ReCycle: Pipeline Adaptation to Tolerate Process Variation" "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency"

Uploaded by

Sannena Govinda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

[1] A. Wang et al., Adaptive Techniques for Dynamic Processor Optimization. Springer, 2008.

[2] A. Tiwari et al., "ReCycle: Pipeline Adaptation to Tolerate Process Variation," Proc. Int'l
Symp. Computer Architecture, pp. 323-334, 2007.
[3] M. Wieckowski et al., "Timing Yield Enhancement through Soft Edge Flip-Flop Based
Design," Proc. Custom Integrated Circuits Conf., pp. 543-546, 2008.
[4] L.X. Liang et al., "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and
Variable Latency," Proc. Int'l Symp. Microarchitecture, vol. 29, pp. 127-138, 2009.
[5] P. Franco et al., "On-Line Delay Testing of Digital Circuits," Proc. VLSI Test Symp., pp. 167173, 1994.
[6] M. Favalli et al., "Sensing Circuit for On-Line Detection of Delay Faults," IEEE Trans. VLSI
Systems, vol. 4, no. 1, pp. 130-133, Mar. 1996.
[7] C. Metra et al., "On-Line Detection of Logic Errors Due to Crosstalk, Delay, and Transient
Faults," Proc. Int'l Test Conf., pp. 524-533, 1998.
[8] M. Nicolaidis, "Time Redundancy Based Soft Error Tolerance to Rescue Nanometer
Technologies," Proc. VLSI Test Symp., pp. 86-94, 1999.
[9] Y. Tsiatouhas et al., "A Sense Amplifier Based Circuit for Concurrent Detection of Soft and
Timing Errors in CMOS ICs," Proc. Int'l On-Line Testing Symp., pp. 12-16, 2003.
[10] M. Agarwal et al., "Circuit Failure Prediction and Its Application to Transistor Aging," Proc.
VLSI Test Symp., pp. 277-286, 2007.
[11] T. Sato et al., "A Simple Flip-Flop Circuit for Typical-Case Designs for DFM," Proc. Int'l
Symp. Quality Electronic Design, pp. 539-544, 2007.
[12] K. Bowman et al., "Circuit Techniques for Dynamic Variation Tolerance," Proc. Design
Automation Conf., pp. 4-7, 2009.
[13] M.R. Choudhury et al., "Masking Timing Errors on Speed-Paths in Logic Circuits," Proc.
Design Automation and Test in Europe, pp. 87-92, 2009.

[14] M.R. Choudhury et al., "TIMBER: Time Borrowing and Error Relaying for Online Timing
Error Resilience," Proc. Design Automation and Test in Europe, pp. 1554-1559, 2010.
[15] D. Ernst et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation,"
Proc. Int'l Symp. Microarchitecture, pp. 7-18, 2003.
[16] K. Bowman et al., "Energy-Efficient and Metastability-Immune Timing-Error Detection and
Recovery Circuits for Dynamic Variation Tolerance," Proc. Int'l Conf. Integrated Circuit Design
and Technology, pp. 155-158, 2008.
[17] M. Kurimoto et al., "Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven
Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling," Proc. Design
Automation Conf., pp. 884-889, 2008.
[18] K. Hirose et al., "Delay-Compensation Flip-Flop with in-situ Error Monitoring for LowPower and Timing-Error-Tolerant Circuit Design," Japanese J. Applied Physics, vol. 47, pp.
2779-2787, 2008.
[19] C. Kwanyeob et al., "A Dynamic Timing Control Technique Utilizing Time Borrowing and
Clock Stretching," Proc. Custom Integrated Circuits Conf., pp. 1-4, 2010.
[20] A. Paschalis et al., "Concurrent Delay Testing in Totally Self-Checking Systems," J.
Electronic Testing: Theory and Applications, vol. 12, pp. 55-61, 1998.
[21] B. Paul et al., "Impact of NBTI on the Temporal Performance Degradation of Digital
Circuits," IEEE Electron Device Letters, vol. 26, no. 8, pp. 560-562, Aug. 2005.
[22] J. Carmona et al., "Elastic Circuits," IEEE Trans. Computer-Aided Design, vol. 28, no. 10,
pp. 1437-1455, Oct. 2009.
[23] H. Partovi et al., "Flow-through Latch and Edge-Triggered Flip-Flop Hybrid Elements,"
Proc. Int'l Solid-state Circuits Conf., pp. 138-139, 1996.
[24] D. Harris et al., "Skew-Tolerant Domino Circuits," IEEE J. Solid-State Circuits, vol. 32, pp.
1702-1711, 1997.

[25] V.G. Oklobdzija et al., "Clocking and Clocked Storage Elements in a Multi-Gigahertz
Environment," IBM J. Research and Development, vol. 47, pp. 567-583, 2003.
[26] M. Ghasemazar et al., "A Mathematical Solution to Power Optimal Pipeline Design by
Utilizing Soft-Edge Flip-Flops," Proc. Int'l Symp. Low Power Electronics and Design, pp. 33-38,
2008.
[27] J. Tschanz et al., "A 45 nm Resilient and Adaptive Microprocessor Core for Dynamic
Variation Tolerance," Proc. Int'l Solid-state Circuits Conf., pp. 282-283, 2010.
[28] K. Bowman et al., "Energy-Efficient and Metastability-Immune Timing-Error Detection and
Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance," Proc. Int'l SolidState Circuits Conf., no. 623, pp. 402-403, 2008.

You might also like