INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 3 MARCH 2015 ISSN: 2349 9303

Design of Zeta Converter Based Electronic Ballast for

Fluorescent lamps
G.Nithya1

B.Vinoth Kumar2

PG Scholar
Department of EEE
1
Bannari Amman institute of Technology
[email protected]

Assistant Professor
Department of EEE
2
Bannari Amman Institute of Technology
[email protected]

Abstract-This paper presents a power factor correction (PFC) based electronic ballast operated in continuous conduction mode
(DCM), which consists of a buck-boost ZETA topology, and a high frequency DC-AC inverter. The electronic ballast is based
on a high frequency dither signal, which shapes the input current in a sinusoidal form. The analysis, design, modeling and
simulation of high power factor (PF) electronic ballast for a fluorescent lamp are carried out with constant dc link voltage.
In this topology, a half bridge series resonant parallel loaded inverter is used to feed constant current to the lamp. The
power quality indices such as total harmonic distortion of AC mains current (THD), power factor (PF) and crest factor (CF)
are evaluated to demonstrate it satisfactory performance.
Index Terms -Constant lamp power, Crest factor, High switching frequency, Power factor, Total harmonic distortion.

1. INTRODUCTION
The fluorescent lamps were commercially introduced in 1938.
Between lighting sources, the fluorescent lamps are becoming
popular and widespread in many applications, because of
longer lifetime, better luminous efficacy. A fluorescent lamps is a
gas discharge lamp. They have no filament through it. Typical
fluorescent tube is filled with inert gas and a small amount of
mercury that creates vapor. Cathode (a tungsten filament),
which are at each end, send a current through mercury
vapors, sealed in the lamp. The fluorescent lamps use electricity
to excite mercury vapors. Ultraviolet radiation is produced as
electrons from the cathode knock mercury electrons out of their
orbit. The inside of the fluorescent lamps has a phosphor coating.
This coating converts ultraviolet radiation into visible light. The
conversion of electric power into light is more efficient in a
fluorescent lamps than an incandescent lamp. The cost of
fluorescent lamps is higher than the cost of incandescent lamp,
but the energy is saved using fluorescent lamps. A disadvantage
of fluorescent lamps, it is that they require a ballast to
control the current through the lamp.
The lamp ballast has two main functions:
To provide a starting kick and
To limit the current to the proper value for the lamp

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There are two types of ballasts: inductive ballasts and electronic

ballasts. The electronic ballasts are more efficient as inductive
ballasts. Inductive ballasts have to be operated in conjunction
with starters for lamp ignition. Electronic ballast operates at high
frequencies from 20kHz to 50kHz and uses electronics
circuitry to optimize the operation of the lamp. Electronic
ballasts for fluorescent lamps becoming more common due to it
superior performances.
EMI Filter

Rectifier
~

AC Line

~
Inverter

Resonant Filter

PFC Converter

Lamp

Fig .1 General Block Diagram of Electronic Ballast

A typical Fluorescent lamps drive consists of a set of stages as
shown in Fig. 1, which should provide satisfactory lamp
operation, fulfilling the standards of power factor and efficiency
of the energy drained from grid [10]. The electromagnetic
interference (EMI) filter is designed to eliminate the harmonic

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components generated by the high frequency switching of the PF
correction (PFC) stage, because otherwise, high-frequency
harmonics can decrease the system PF and cause interference
problems with other equipment. The requirements for this first
stage will depend on the selected converter and design
methodology. This circuit typically employs a half-bridge inverter
to generate the square waveform applied to the resonant load and
set the lamp operating frequency [12], [13].
AC Line

Rectifier

ZETA Converter

+
~

Lamp
Half bridge series loaded
Inverter

Fig .2 Proposed system

In the proposed method ZETA converter is used in the PFC
stage and the series resonant half bridge parallel loaded inverter
in the power control stage. The input inductor reduces the ripples
and henceforth increases the power factor at the input stage. The
SRPLI is used to operate the lamp at the power lamp. The
proposed topology is capable of withstanding the large input
voltage 90V-270V and a low input current total harmonic
distortion.

Fig.3 Schematic diagram of proposed electronic ballast

The schematic diagram of proposed electronic ballast is
shown in Fig. 3 , which consists of a PFC based ac-dc converter
consisting of a diode bridge and a ZETA and a high frequency
dc-ac half bridge inverter in cascade connection to drive the
lamp. The ac-dc converter facilitates the ac current to follow
the ac mains voltage and achieves nearly unity power factor
at input ac mains and the dc-ac inverter provides sufficient
ignition voltage and supplies constant lamp current at high
frequency to maintain proper illumination.

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In the proposed electronic ballast, the selection of proper

converter is made based upon the following considerations.
1. An energy storage element must be present between a
PFC ac-dc converter and a lamp-driving dc-ac inverter to
prevent the lamp current to be directly controlled by the
ac mains voltage. For this purpose, a capacitor is preferred
over an inductor due to it less cost and size.
2. A lamp-driving dc-ac converter is used to be a voltage fed
inverter to save filter components.
3. Low ac mains voltage should be boosted-up to generate a
high voltage to ignite lamp without use of a boost-up
transformer.
4. For a wide variation of input ac mains voltage, the dc
link voltage should be maintained constant.
As per the considerations made above, a ZETA buck
boost ac-dc converter is chosen as the PFC converter and a
half bridge series resonant inverter is used to drive the lamp.
Fig. shows the proposed electronic ballast derived from
DCM controlled ZETA converter and half bridge series
resonant parallel loaded inverter (SRPLI).The power switches
MI and M2 are alternately turned on and off at a 40 kHz
frequency. The switching frequency of the resonant inverter
is maintained more than the resonance frequency of the load
circuit to achieve the ZVS (Zero Voltage Switching), which
reduces the high frequency switching losses.

2. ZETA CONVERTER AS POWER STAGE

2.1 Basic Operation
Fig 1 shows a simple circuit diagram of a ZETA converter,
consisting of an output capacitor, C2; coupled inductors L1 and
L2; an AC coupling capacitor, C1;a power PMOSFET,Q; and a
diode, D. Fig 3 shows the ZETA converter operating in DCM
when Q is on and when Q is off.
To understand the voltages at the various circuit nodes,
it is important to analyze the circuit at DC when both switches
are off and not switching. Capacitor C1 will be in parallel with
C2, so C1is charged to the output voltage, VOUT, during steadystate DCM. Fig 2 shows the volt ages across L1 and L2 during
DCM operation. When Q is off, the voltage across L2 must be
VOUT since it is in parallel with C2. Since C2 is charged to
VOUT, the voltage across Q when Q is off is V IN+ VOUT;
therefore the voltage across L1 is VOUT relative to the drain of
Q. When Q is on, capacitor C1, charged to VOUT, is connected
in series with L2; so the voltage across L2 is +VIN, and diode D
sees VIN+ VOUT. The currents flowing through various circuit
components are shown in Fig 3. When Q is on, energy from
the input supply is being stored in L1, L2, and C1. L2 also
provides IOUT. When Q turns off, L1s current continues to
flow from current provided by C1, and L2 again provides IOUT.

3. DESIGN CONSIDERATIONS

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3.1 Duty cycle
Assuming 100% efficiency, the duty cycle, D, for a
ZETA converter operating in DCM is given by
D=

V out
V in + V out

(1)

This can be rewritten as

D
1D

I IN
I out

V out
V in

1D

Where D is duty cycle. VOUT is plotted as a function of D in Fig 6.

As can be seen, for D less than 0.5 the converter performs
buck function and for D larger than 0.5 it is a boost topology.

4. COMPONENT SELECTION
4.1 L1 Selection
Select L1 for inductance L, saturation current I SAT and
DC rating IDC.
Calculate inductance from:
V in ,max
I ripple f V in ,max +V out

(4)

Where: IRIPPLE is the permissible peak-to-peak ripple current

(nominally 50% of IOUT)
. Switching frequency
V INmax . Maximum input voltage
Calculate DC rating of L1 from:
=

I +
V in ,min E ff

(5)

Where: VIN,min is the minimum input voltage

Eff is converter efficiency (nominally 85%)
Calculate saturation current from:
Isat 1.15 X IDC (6)
Where IDC is DC rating of L1 calculated above.
4.2 L2 Selection
Let L2 equal L1 thereby ensuring both inductors will
have same ripple current. This is true since during ON time

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(7)

for both inductors . Selecting L2=L1 also makes it possible to

wind both inductors on the same core if it is so desired. I DC
should be at least equal to IOUT. Calculate saturation current as
shown for L1.
4.3 C1 Selection

Voltage Conversion Ratio Output voltage is given by the

following equation:
D
V0 = Vin
(3)

T on

(2)

Dmax occurs at VIN(min), and Dmin occurs at VIN(max).

L1 =

L = Vin X

Select C1 for capacitance, voltage rating V DC and ripple

current rating IRIPPLE.
Calculate C1 from
C1 =

I o +V 0
V in +V 0 f V ripple

(8)

Where: VIN is minimum input voltage

VRIPPLE is voltage ripple across C1 (nominal 1% of VOUT)
DC Voltage rating should be greater than VOUT and ripple
current should be greater than IOUT.
4.4 CIN Selection
Select the input capacitor CIN for Voltage rating, ripple
current and Capacitance. A simplified expression for ripple
current can be obtained by assuming D=0.5 and Efficiency
=100%. Then IIN = IOUT and IRMS can be estimated from:
ICin = 0.5 X I0 (9)
In general, input voltage ripple should be kept below
1.5% of VIN (not to exceed 0.18V). By using the same
assumptions that were applied for simplifying ripple
current calculation, required input capacitance can be
estimated from:
CIN = I0

1
2f0.18v

(10)

Note that in the CIN equation the effect of ESR and

ESL has been assumed to be negligible. This assumption is
valid for ceramic capacitors and high quality Tantalum and
Aluminum electrolytic capacitors.
4.5 COUT Selection
Select the output capacitor for capacitance, voltage
rating and Equivalent Series Resistance (ESR). To simplify
analysis, assume that a ceramic capacitor is used with ESR =
5mOhm. Then VOUT ripple due to ESR is negligible. To
calculate COUT, let inductor current ripple equal 30% of output
current and use the following equation:
C0 =

I rip
8V riff f

(11)

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Where: IRIP is inductor ripple current (nominally 30% of IOUT)
VRIP is output voltage permissible ripple (nominally 1%of
VOUT)

By applying the voltage division rule (Fig. 3.8), the ratio of

rated lamp voltage (Vlamp) and the fundamental component
of input square voltage (Vab) is given as,
Vlamp (j)
Vab (j)

5. SRPLI as PC stage
5.1 Basic operation
The SRPLI is normally referred as the symmetric half-bridge and
uses one of the resonant tank capacitors (C b in the Fig 4) to block
the dc voltage level of the square wave generated by the bridge.
This means that capacitor Cb will exhibit a dc level equal to half
the dc input voltage superimposed on it normal alternating
voltage. A transformer can also be used in this inverter to step the
input voltage up or down to the required level for each
application. In this case the use of the series capacitor C b prevents
any dc current from circulating through the primary winding, thus
avoiding transformer saturation. This topology is often used by
ballast manufacturers to supply fluorescent lamps, especially in
the self-oscillating version, which allows drastic reductions in
cost. When supplying hot cathode fluorescent lamps, the parallel
capacitor Cp is normally placed across two electrodes, as shown
in Fig 4, in order to provide a preheating current for the electrodes
and achieve soft ignition.

Ls
j
Cp
2
[1+
Cb LrCp +j R CR ]

(12)

Now substituting quality factor Q s = sLr/R lamp ,

the frequency ratio x = r/s and resonance frequency after
ignition, fr = 1/ in equation (12), results in as,
Vlamp
Vab

Cp
2 2 +Q (x1 )2 ]
[1+
s
Cb 1+x
x

(13)

Under steady state condition, the resistance of fluorescent lamps

is given as,
2
R lamp = Vlamp
/Plamp (14)

The parallel resonant capacitor is given as,

Cp = 1

Cb

(15)

x 21

The series resonant inductor is given as,

6. DESIGN OF RESONANT CIRCUIT

PARAMETERS

Lr =

The equivalent circuit of the series resonant parallel loaded

inverter (SRPLI) under the steady-state operation of the
fluorescent lamp is shown in Fig. 4. In this equivalent
circuit LrCb and Cp are the resonant circuit parameters and
R lamp is the steady state resistance of the fluorescent lamps.
The purpose of Cb (blocking capacitor) is to block the dc
component otherwise they can distort the lamp current.

1
Cb Cp
C b +C p

2s (16)

where, Vlampis the rated lamp voltage, Vab is the

fundamental component of square voltage, R lamp is the lamp
resistance under steady state condition, f f is the angular
switching frequency, Cb is blocking capacitor, Cp is parallel
resonant capacitor and Lr is the series resonant inductor.
Table 1. Design Specifications

Zs
Cb
Lf
Vab

Rlamp

Cp

Fig 4 Equivalent circuit of resonant tank

At the time of starting, a high voltage is required to
ionize the gas present inside the lamp. Thus the series
resonant inverter is designed such that during pre-heating, the
resonance frequency is equal to the switching frequency to
ensure high voltage generation across the lamp electrodes.
Before the starting of the lamp, a resonant circuit is formed
by LrCb and Cp. After the ignition, the switching frequency is
changed and becomes higher than the resonance frequency to
achieve ZVS at turn-on transition of both the switches (i.e. M1
and M2) .After ignition the circuit is formed by LrCb and R lamp.

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Parameters

Specification

Input RMS Voltage ,Frequency

200V,50 HZ

Switching frequency, Duty cycle

40 HZ, 0.57

Output Power,Efficiency, Ripple Current 600W, 85%, 15%

PFC Stage Output Voltage

110-120V

Lamp Parameters
Rlamp

400

Llamp

600 H

ZETA Converter Parameters

L1 L2
3.2 mH,194H
C1 Cbus
12 nF, 3F
Resonant Elements

Fig 6. Waveform of Source current and voltage

Lr

2.68 mH

Cb

95 nF

Cp

6.6 nF

7. SIMULATION AND RESULTS

The simulation diagram of proposed topology having
ZETA converter as the PFC stage and series resonant half bridge
parallel loaded inverter as the power control stage is shown in the
Fig 5.

Fig.7 Output voltage Diode Bridge Rectifier

The output voltages of ZETA converter and half bridge
inverter is shown in the Figs 8 and 9 respectively.

Fig 5 .Simulation of ZETA PFC based Electronic Ballast

7.1 Waveforms
The source voltage and current waveform of the proposed
topology is shown in Fig 6. The output voltage of the diode
bridge rectifier is shown in Fig 7
Fig 8. Output voltage of ZETA converter

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Table 2 shows the comparison of results of SEPIC based
electronic ballast in the reference [14] and the proposed ZETA
converter based electronic ballast which shows the satisfactory
performance of proposed ballast.

8. CONCLUSION

Fig 9.Output voltage of Half Bridge Inverter

7.2 THD Analysis of the Proposed System

A DCM controlled ZETA converter with low THD

has been proposed for PFC based electronic ballast. The
proposed converter can be applied as an electronic ballast for
fluorescent lamps as well as medium power supply. The proposed
electronic ballast with PFC ZETA converter has shown high
performance such as high power factor and crest factor of
1.237 for the wide range of input ac mains voltage. The dc link
voltage has been maintained constant, irrespective of the
change in ac mains voltage. Moreover, when operating in
closed loop, an output power control can be achieved. With an
appropriate design of PFC ZETA converter and a resonant
converter, the need of electromagnetic interference filter has
neglected.
The ballast can withstand the variation in the input
voltage and delivers constant power to the lamp thus improving
the performance and stability of the lighting by avoiding flickers.
The SRPLI is used to deliver a constant power to the lamp and it
is self-protected against short circuit .The proposed ballast has
THD of ac mains current under 11.52% for the universal
voltage range of 90V-270V. The zero voltage switching
(ZVS) has been ensured because switching frequency is kept
more than the resonance frequency of the resonant inverter,
which reduces the switching losses and improves the efficiency
of ballast.

REFERENCES
Fig 10. THD analysis of Input Current
The Fig 10 shows the THD analysis of the input current
of the ZETA converter based electronic ballasts. The harmonics
order is shown that the THD of 11.60% is so obtained from the
proposed system.
Table 2. Comparison of Results

Parameters

SEPIC Converter
Based Electronic
Ballast

ZETAConverter
Based Electronic
Ballast

Current THD

14.89

11.60

Crest Factor

1.4501

1.237

Power Factor

0.989

0.98

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