University of Southern California

Electrical Engineering Department

EE 477L Lab Assignment #1

Logic Gate Design/Layout and Simulation Experiments with Combinational Cells

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YOU MUST WORK INDEPENDENTLY ON THE LABS: THERE ARE NO GROUP
PROJECTS.

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This lab has six parts:
Part 1 (30 pts)

Use CADENCE Virtuoso schematic to design CMOS logic gates at the

transistor circuit level for the following functions:
I.
II.
III.
IV.

3 inverters: INV1, INV2, INV4

2-input NAND gate: NAND2
3-input NAND gate: NAND3
A compound gate that implements the function:

= [( + ) + ] +

Transistor Sizing:
Your lab technology lambda () is 0.1m (or 100 nm). Assume Vdd = 1.8V. For your
schematic and layout you must make the transistor dimensions in multiples of 0.5 .
This means: W=0.3m, 0.35m, 0.4m, 0.45m are only allowed.
Start your device sizing by experimentally determining an approximate value for the
transistor beta ratio (R) for the inverter: R = N / P.
The Basic Inverter: INV1 - The nMOS device in the inverter should be a unit-sized
transistor, as defined in the text and lectures. For the inverter, make the width of the pMOS
device so that the rise time (TR) and fall time (TF) of this inverter are within about 10% of
each other (TR TF). This is called a Balanced Inverter.
Note: Rise time is defined as 0.1Vdd-to-0.9Vdd for the output rising edge. Fall-time is
defined as 0.9Vdd-to-0.1Vdd for the output falling edge.

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The Larger Inverter: INV2 - Size both the transistors in this inverter 2 times as wide as
in the basic inverter.
The Largest Inverter: INV4 - Size both the transistors in this inverter 4 times as wide as
in the basic inverter.
Note: you can put two or more unit-sized transistors in parallel instead of widening a
single transistor. This keeps your methodology consistent. Use m (multiplier) factors for
devices in the schematics.
The NAND Gates: For the NAND2 and NAND3 gates, use unit-sized nMOS devices and
make the pMOS transistors wide enough to have the rise and fall times within 25% of each
other. This is a balanced NAND gate.
The Compound Gate: For the compound gate, experiment with transistor widths that give
output rise and fall times within 25% of each other, in the worst case. Note: the sequence
of inputs that give worst-case timing and critical path timing might be different from the
required input sequences specified below.

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Part 2 (20 pts)

Simulate your transistor-level circuits using Cadence Spectre to determine

that they function properly.

Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label
your outputs: INV1OUT, INV2OUT, INV4OUT, NAND2OUT, NAND3OUT, and COMPOUT.

Simulation Test-bench: Every test-bench circuit consists of three distinctive components:

Device-Under-Test (DUT), Input or Inputs Stimulus, and Output Load.

Fig. 1. Simulation Test-bench for logic circuits

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Attach your INV1 to the output of each designed gate (INV1, INV2, INV4, NAND2,
NAND3, and Compound Gate) prior to circuit extraction and simulation to represent an
output load capacitance. The output that you should plot is the input to the load inverter.

Make input voltage source rise time, fall time, and delay all 10 pico-second (ps) and
period 4 nano-second (ns). Use 50% duty cycle for inputs. Show simulations of each gate
with all possible combinations of inputs.

Change the inputs in the following manner:

NAND2: AB = 00, AB = 01, AB = 10, AB = 11.
NAND3: ABC = 000, ABC = 001, ABC = 010....etc.
Compound Gate: simulate all combinations of A, B, C, D, and E from 00000 to 11111.
Change the inputs in the order given here.
Measure the rise time and fall time for each cell. Make sure that the rise and fall times for INV1,
the NAND gates, and the compound gates meet the requirements from Part 1.
Average Power Measurement
For inverters INV1, INV2, and INV4, measure average power using Spectre
Simulation/Calculator. Measure the average power consumption of the device under test (DUT)
over a period of 400ns. This is 100 cycles. Use INV1 as a load for each of DUT.
Voltage Transfer Curve (VTC) Characteristics
Only for the INV1 sweep the DC input voltage starting at 0 V to 1.8V (rail-to-rail).

Find the slope of output voltage transfer curve (VTC).

Find two points on the VTC at which the slope is -1. These are the VIL and VIH
values for the inverter. Compute NMH and NML.
Find the slope of the VTC at the peak point. This is the inverter threshold voltage.

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Part 3 (30 pts)

Layout your cells with Cadence (each circuit layout is a "cell"). Use the
TSMC20N technology as instructed in lab. Put at least one ntap and ptap
(ohmic contacts) in each cell. If you have multiple n-wells in a cell, each nwell needs at least one ohmic contact.

Required Layout Design Methodology:

Design your entire cell layouts so that they can be placed next to each other either
vertically or horizontally without having layers connect that should not. We need to tile
different cells together later.
1.
2.
3.
4.
5.

Layout of all your cells must follow Fig. 1.

The width of the vdd! Power supply and gnd! Supply must be 10 =1 m.
The height of the cell must be less than 100=10 m.
The height of the N-Well may be (not necessarily) about half of the cell height.
The width of the cell must be as small as possible (optimizing the area).

Cell Width

vdd!

Metal-1

10=1m

pMOS
Devices

N-Well

N-Well
Height

nMOS
Devices
gnd!

Metal-1

Cell
Height

10=1m

Poly
Inputs A, B, C, ...
Fig. 2. Standard Cell Layout
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Use a uniform methodology to design all the gates, and only use metal-1 and
metal-2 for interconnects between the cells.

Make sure that you minimize the use of poly (for example, you could only use poly
around the gate region of each transistor).

Your goal is to insure that it is easy to build more complex designs out of your
gates, and to keep the cells small, with few layer changes for each connection.

You want to extend your methodology to design compound gates as well.

Keep in mind as you design the inverter that you may want to redesign it later with
wider transistors.

Try to minimize the white space to create cells that are as small as possible, but
easily combined into larger circuits. One hint: you could design the cells so that the
output of each cell lines up exactly with an input of every cell type. The output and
input can line up horizontally or vertically.

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Part 4 (5 pts)

Use LVS to verify that your cell layouts are identical to the schematics. You
will simulate the layouts with Cadence SPECTRE in Lab 2 not in this Lab.
(Post-layout simulations are done in Lab 2).
Save the si.out files so to verify that the (layout vs. Schematics) LVS have
passed.

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Part 5 (10 pts)

Layout a small logic block that implements the Boolean function of the
compound gate that you have done before:

= [( + ) + ] +
using only your INV1 and/or NAND gate cells from Part 3. This exercise should help you
tune your cells so that they can be connected easily into logic blocks for the final project.
Be sure that inputs/outputs with the same name are connected on the layout. Do not be
concerned with simulation or device sizing. You need to do DRC and LVS for this.

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Part 6 (5pts)

Submit your lab write-up. The lab write-up is worth 5% of the Lab #1 grade.

Turn in final transistor-level schematics, layouts and schematic Cadence SPECTRE

simulation outputs for all cells. Turn in the layout for the logic block. You do not need to
simulate the layout for this lab (post layout simulations).

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Lab Report Contents:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.

14.
15.

Title page
Discussion and explanation of how you designed the logic gates and sized transistors.
Include the transistor beta ratio you found and the measured rise and fall times.
Transistor schematics of gates.
Cadence Spectre outputs for each gate schematic simulation in the form of images
showing the waveforms.
Average power measurements for the 3 inverters: INV1, INV2, INV4.
Low and high noise margins for INV1.
Layouts of gates, captured as images, making sure the images are high enough resolution
so the grader can see layout details and inputs/outputs are labeled.
Table showing cell sizes for all the cell designs.
Layout of the logic block, captured as an image.
Conclusions about the lab, especially about sizing the transistors in the compound gate.
Your lab report should be a pdf file format. Please do not submit a .doc or .docx file.
Name the report as follows: LastnameLab1.pdf
Include as separate files: Each file called si.out generated in a folder called LVS showing
the results either match or mismatch for each cell layout. Be sure you rename the si.out
file after each cell is verified to something like NAND2.out. Otherwise it will get
overwritten.
Use the "tar function" on UNIX to put all the files including the report into a single file.
(See Wikipedia for instructions on how to tar a file). Do not put into rar format.
Provide a table that shows the area, speed and power for cells as follows.

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Instructions on how to print your layout and waveform images in color for layouts:
In the layout editing window:
File => Print
"Submit Plot" window will pop up.
You can choose plot with "header" or "notes" or disabled both
Click on Plot Options
"Plot Options" window will pop up.
Display type: display
Plotter Name: (change to) Generic 300 dpi Adobe Post Script Level 2 Plotter (for color images)
Send Plot Only To File : (type in file name ending with .ps)
Then use distill function to convert .ps to .pdf
The same instruction can be used to print the schematic.

Here is the instruction to print waveforms from Cadence:

File => Save as Image
>> Then enter a name and save in PNG format.
It might take several minutes (so please be patient.) The hourglass should appear.

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Some Important Guidance:
(1)

Unix enviorenment and Cadence is case sensitive. Case sensitive means that the labels
in your schematic should be consistent with the labels in your layout. For example, if in
my schematic you use A for the input of the inverter then in the layout you should use A
for the input of the layout inverter (If we use a instead of A, it wont work).

(2)

The label for the power supply terminal in the layout should be vdd! (do not use Vdd!),
for ground use gnd! (do not use Gnd!).

(3)

Rise/Fall time. There is an option in the rise time window that allows you to measure all
the rise times in a simulation. It is the # of occurrences. The default is single, you can
change it.

(4)

Transmission gate: It is necessary to put on the schematic a floating vdd and a floating
gnd in order to compare the LVS because you have them in your layout (vdd! and gnd!).

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(5)

Flipping layouts: In case you need to flip the layout cells you can do the following:
select the cell => right click => move and then select the rotate option of your preference.

(6)

A final comment. If the layout/schematic does not match, please verify all the pins and all
the connections on each node. Also, please remember to put ntap and ptap on the layout.
If you couldn't find the errors, then I suggest repeating the layout again, though 99.9% of
the time the LVS error is due to a wrong connection or wrong pin labels. These cells are
small enough to be able to find the error. You can use the help of the LVS output file to
identify the error. Before sending the TAs emails please try all the possible options and
verify all possible layout/schematic errors.

Good luck!

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