Programmable Logic Devices (PLDs)

I. Introduction to Programmable Logic Device

A. Definition

A Programmable Logic Device is an integrated circuit with internal logic

gates and interconnects. These gates can be connected to obtain the
required logic configuration.
The term programmable means changing either hardware or
software configuration of an internal logic and interconnects.
The configuration of the internal logic is done by the user.
PROM, EPROM, PAL, GAL etc. are examples of Programmable Logic
Devices.
A programmable Logic device refers to any type of integrated circuit
that a logic design can be implemented and reconfigured in the field by
the end user. Since these logic devices can be programmed in the field
they are also called Field Programmable Logic Devices (FPLDs). The
PLD provides flexibility for designers to implement many different
designs in varying complexities for many different applications. One of
the most common PLDs is the one time Programmable Read-only
Memory (PROM). This comes in two different types: (a) mask
programmable devices programmed by the vendor using a custom
mask and interconnects and (b) field programmable devices that are
configured by the user. One of the great advantages of PLDs is that
they are very inexpensive at low quantities.
Block Diagram of PLD

B. Programming Technologies
Programmable Logic Device can be programmed in two ways:
1. Mask programming (in some few cases): programming of device is
done in the mask level.
+ good timing performance due to internal connections
hardwired during manufacture
+ cheap at high volume production
- programmed by manufacturer
- development cycle = weeks or months
- not re-programmable
2. Field programming: programming of device is done by the user. The
programming technologies are of two types
Permanent type (Non-volatile):
Fuse (normal on) - CLOSE (intact) OPEN (blown)
Anti-fuse (normal off) - just the opposite of a FUSE
EPROM
EEPROM
Nonpermanent type (Volatile):
driving n-MOS pass transistor by SRAM
NOTE:
-When power of device is switched off then the content of SRAM is lost.

II. Types of PLDs

A. Simple Programmable Logic Devices

The simple PAL architecture has become an industry standard. PLAs
and PALs that have pin packages of 20 44 pins and density ranging from
100 to several hundred gates are considered SPLDs. The Basic AND/OR
architecture PALs are flexible devices that can implement logic equations in

Boolean sum-of-product (SOP) form. Some enhancements to SPLDs have

been programmable input/outputs (I/Os), bidirectional I/Os, programmable
output polarity, flexible register configurations and chip clocks.
One important advantage for PLDs is that they can replace small to
medium- scale integrated (SSI/MSI) circuits for higher packaging density. One
PLD could replace tens of integrated circuits with 200 500 gate equivalent.
Other benefits for SPLD is that they reduce power, have faster turn-around
time, faster performance because they reduce interconnects between chips
and higher reliability. SPLDs are available in bipolar and Complementary
Metal Oxide Semiconductor (CMOS) technology. In CMOS technology, they
come in Erasable PROM (EPROM) based which are Ultraviolet Erasable
(UVEPROM) and Electronically Erasable (EEPROM).
Due to the simple architecture of an SPLD they offer very high
performance. The SPLD devices are at 0.5 um CMOS process with logic
delays down to 3.5 ns and frequencies as high as 200 MHz. Higher density
devices are coming on the market in the area of Complex Programmable
Logic Devices (CPLD) with high performance, but SPLDs still have the best
performance, easier to use and design with because they are an industry
standard. Computer networking components and other telecommunication
equipment still demand the need for SPLD devices due their high
performance. Because of the trend to migrate to higher densities SPLDs have
been driven to specialty markets such as cellular phones, video games and
hand held web browsers.
New innovative advancements in SPLD include programmable output
logic, macrocells that can be configured as combinatorial or register
operation and active low or active high polarity. SPLDs are also available in
lower-voltage and low power offering 5 volt and 3.3 volt devices. This allows
more flexibility for design applications that require trade-offs between low
power, high frequency and low voltage.
1. PLA (Programmable Logic Array)
array of AND and OR gates are programmable
product term sharing: every product term of the AND array can
be connected to the input of any OR gate
unidirectional input/output pins.
2. Memory based: Device with fixed AND array and programmable OR
array
output of OR gate has fixed connection with input of AND gates
PROM, EPROM and EEPROM are memory based PLD device
3. PAL/GAL(Programmable Array Logic/ Gate Array Logic): AND array is
programmable and OR array has fix connection with outputs of AND gates.
PAL/GAL devices may have bi-directional I/O pins.

There are three different types of PAL/GAL devices

combinational PAL devices are used for the implementation of
logic function
sequential PAL devices are used for the implementation of
sequential logic (finite state machines)
arithmetic PAL devices sum of product terms may be combined
by XOR gates at the input of the macrocell D flip-flop.
Additional features of PAL/GAL devices
PAL:
- EPROM - based programming Technology
GAL:
- has array of programmable AND gates and OLMC (Output
Logic Macro Cell)
- EEPROM - based programming Technology
- programmable output polarity
- device can be configured as dedicated input and output mode
B. High Density Programmable Logic Devices
The main disadvantage for the SPLD is an architectural limitation.
SPLDs have a limited amount of logic structures that can be allocated in a
design in a fixed way. High-density or high-capacity PLDs (HDPLDs/HCPLDs),
which are also called complex PLDs (CPLDs) and Field Programmable Gate
Arrays (FPGAs), try to solve the silicon limitation by adding more flexible
block structures and interconnects. Programmable Logic Devices include
simple as well as high-density PLDs.
The two major elements of CPLDs and FPGAs are the logic elements
and the interconnect structure. The logic elements are also known as
macrocells, logic cells and/or logic blocks. The interconnect structure is how
those elements are connected together to perform the design for a specific
application. As mentioned there are two high-density programmable logic
devices. Those are complex programmable logic devices (CPLDs) and field
programmable gate arrays (FPGAs). It is hard to determine the difference
between the two but usually in CPLDS there is fixed routing resources on-chip
and routing is done via a switching matrix, which leads to predictable delays.
In the SPLD architecture, each macrocell contains its own product term.
However, in the CPLD architecture the vendor takes advantage of the
complex macrocells and employs product term steering or product term

sharing between the macrocells. The term complex in CPLD refers to pin
count and the amount of internal macrocells.
1. Complex PLDs

is combination of multiple PAL or GAL type devices on a single chip

CPLD architectures consists of
- Macrocells
- configurable flip-flop (D, T, JK or SR)
- Output enable/clock select
- Feedback select
CPLD has predictable time delay because of hierarchical interconnection
easy to route, very fast turnaround
performance independent of netlist
device is erasable and programmable with non-volatile EPROM or
EEPRO configuration.
wide designer acceptance
has more logic density than any classical PLDs device
relatively mature technology, but some innovation still ongoing

2. Field Programmable Gate Array

FPGA is a general purpose, multi-level programmable logic device

FPGA is composed of
- logic blocks to implement combinational and sequential logic
circuit
- programmable interconnect wire to connect input and output of
logic blocks
- I/O blocks logic blocks at periphery of device for the external
connection
The routing resources are both the greatest strength and weakness
of the FPGAs
Field Programmable means that the FPGA's function is defined by a
user's program rather than by the manufacturer of the device.
A typical integrated circuit performs a particular function defined at
the time of manufacture. In contrast, the FPGA's function is defined
by a program written by someone other than the device
manufacturer.

Depending on the particular device, the program is either 'burned'

in permanently or semi-permanently as part of a board assembly
process, or is loaded from an external memory each time the device
is powered up.
This user programmability gives the user access to complex
integrated designs without the high engineering costs associated
with application specific integrated circuits.