Scribd
Upload
45 views21 pages

Testing4 PDF

This document discusses fault simulation techniques for verifying VLSI chip designs. It begins with an overview of fault models and types including stuck-at faults. It then discusses fault simulation algorithms including serial and parallel approaches. Serial simulation injects one fault at a time into the circuit model while parallel simulation simulates multiple faults simultaneously by exploiting bit-level parallelism in computer word operations. The document provides details on how parallel simulation packs fault responses into a single computer word for efficient simulation of many faults in parallel.

Uploaded by

doomachaley
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
45 views21 pages

Testing4 PDF

This document discusses fault simulation techniques for verifying VLSI chip designs. It begins with an overview of fault models and types including stuck-at faults. It then discusses fault simulation algorithms including serial and parallel approaches. Serial simulation injects one fault at a time into the circuit model while parallel simulation simulates multiple faults simultaneously by exploiting bit-level parallelism in computer word operations. The document provides details on how parallel simulation packs fault responses into a single computer word for efficient simulation of many faults in parallel.

Uploaded by

doomachaley
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

VLSI

VLSI Testing
Testing
Fault
Fault Simulation
Simulation
Virendra Singh
Indian Institute of Science
Bangalore
[email protected]
E0 286: Test & Verification of SoC Design
Lecture - 4
Jan 25, 2008

E0-286@SERC

Fault
Fault Model
Model -- Summary
Summary
Fault models are analyzable approximations of
defects and are essential for a test
methodology.
For digital logic single stuck-at fault model
offers best advantage of tools and experience.
Many other faults (bridging, stuck-open and
multiple stuck-at) are largely covered by
stuck-at fault tests.
Stuck-short and delay faults and technologydependent faults require special tests.
Memory and analog circuits need other
specialized fault models and tests.
Jan 25, 2008

E0-286@SERC

Fault Simulation

Jan 25, 2008

E0-286@SERC

Simulation
Simulation Defined
Defined

Definition: Simulation refers to modeling of a


design, its function and performance.
A software simulator is a computer program;
an emulator is a hardware simulator.
Simulation is used for design verification:

Validate assumptions
Verify logic
Verify performance (timing)

Types of simulation:

Jan 25, 2008

Logic or switch level


Timing
Circuit
Fault

E0-286@SERC

Simulation
Simulation for
for Verification
Verification
Specification
Synthesis
Response
analysis

Computed
responses

Jan 25, 2008

Design
changes

Design
(netlist)

True-value
simulation

E0-286@SERC

Input stimuli

Modeling
Modeling Levels
Levels
Modeling
level

Signal
values

Circuit
description

Programming
Function,
behavior, RTL language-like HDL

0, 1

Timing

Application

Clock
boundary

Architectural
and functional
verification

Logic

Connectivity of
Boolean gates,
flip-flops and
transistors

0, 1, X
and Z

Zero-delay
unit-delay,
multipledelay

Logic
verification
and test

Switch

Transistor size
and connectivity,
node capacitances

0, 1
and X

Zero-delay

Logic
verification

Timing

Transistor technology Analog


voltage
data, connectivity,
node capacitances

Fine-grain
timing

Timing
verification

Circuit

Tech. Data, active/


passive component
connectivity

Continuous
time

Digital timing
and analog
circuit
verification

Jan 25, 2008

Analog
voltage,
current

E0-286@SERC

True-Value
True-Value Simulation
Simulation
Algorithms
Algorithms

Compiled-code simulation

Applicable to zero-delay combinational logic


Also used for cycle-accurate synchronous sequential
circuits for logic verification
Efficient for highly active circuits, but inefficient for
low-activity circuits
High-level (e.g., C language) models can be used

Event-driven simulation

Jan 25, 2008

Only gates or modules with input events are


evaluated (event means a signal change)
Delays can be accurately simulated for timing
verification
Efficient for low-activity circuits
Can be extended for fault simulation
E0-286@SERC

Compiled-Code
Compiled-Code Algorithm
Algorithm
Step 1: Levelize combinational logic and

encode in a compilable programming language


Step 2: Initialize internal state variables (flipflops)
Step 3: For each input vector
Set primary input variables
Repeat (until steady-state or max. iterations)

Execute compiled code

Report or save computed variables

Jan 25, 2008

E0-286@SERC

Event-Driven
Event-Driven Algorithm
Algorithm
Scheduled
events

e =1

d=0
4

b =1

t=0

f =0

g
0

E0-286@SERC

d = 1, e = 0

f, g

g=0

f=1

7
8

Jan 25, 2008

d, e

Time, t

c=0

g =1
Time stack

a =1
c =1

Activity
list

g=1
9

Time
Time Wheel
Wheel ((Circular
Circular Stack
Stack))
Current
time
pointer

max
t=0
1

Event link-list

2
3
4
5
6
7

Jan 25, 2008

E0-286@SERC

10

Efficiency
Efficiency of
of EventEventdriven
driven Simulator
Simulator
Simulates events (value changes) only
Speed up over compiled-code can be ten
times or more; in large logic circuits about
0.1 to 10% gates become active for an input
change
Steady 0
0 to 1 event

Jan 25, 2008

Steady 0
(no event)

E0-286@SERC

Large logic
block without
activity

11

Problem
Problem and
and Motivation
Motivation
Fault simulation Problem: Given
A circuit
A sequence of test vectors
A fault model

Determine
Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
Set of undetected faults

Motivation
Determine test quality and in turn product quality
Find undetected fault targets to improve tests

Jan 25, 2008

E0-286@SERC

12

Fault
Fault simulator
simulator in
in a
a VLSI
VLSI
Design
Design Process
Process
Verified design
netlist

Verification
input stimuli

Fault simulator

Test vectors

Remove
Modeled
fault list tested faults
Fault
coverage
?

Low

Test
Delete
compactor vectors

Test
generator

Add vectors

Adequate
Stop

Jan 25, 2008

E0-286@SERC

13

Fault
Fault Simulation
Simulation Scenario
Scenario
Circuit model: mixed-level
Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals
High-level models (memory, etc.) with pin faults

Signal states: logic


Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
Four states (0, 1, X, Z) for sequential MOS circuits

Timing
Zero-delay for combinational and synchronous
circuits
Mostly unit-delay for circuits with feedback

Jan 25, 2008

E0-286@SERC

14

Fault
Fault Simulation
Simulation Scenario
Scenario
Faults
Mostly single stuck-at faults
Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
Equivalence fault collapsing of single stuck-at
faults
Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
Fault sampling -- a random sample of faults is
simulated when the circuit is large

Jan 25, 2008

E0-286@SERC

15

Fault
Fault Simulation
Simulation Algorithms
Algorithms

Jan 25, 2008

Serial

Parallel

Deductive

Concurrent

E0-286@SERC

16

Serial
Serial Algorithm
Algorithm
Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each
fault in the fault list:
Modify netlist by injecting one fault
Simulate modified netlist, vector by vector,
comparing responses with saved responses
If response differs, report fault detection and
suspend simulation of remaining vectors

Advantages:
Easy to implement; needs only a true-value
simulator, less memory
Most faults, including analog faults, can be
simulated

Jan 25, 2008

E0-286@SERC

17

Serial
Serial Algorithm
Algorithm

Disadvantage: Much repeated computation;


CPU time prohibitive for VLSI circuits
Alternative: Simulate many faults together

Test vectors

Fault-free circuit

Comparator

f1 detected?

Comparator

f2 detected?

Comparator

fn detected?

Circuit with fault f1


Circuit with fault f2

Circuit with fault fn

Jan 25, 2008

E0-286@SERC

18

Parallel
Parallel Fault
Fault Simulation
Simulation
Compiled-code method; best with twostates (0,1)
Exploits inherent bit-parallelism of logic
operations on computer words
Storage: one word per line for two-state
simulation
Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine
word length
Speed up over serial method ~ w-1
Not suitable for circuits with timing-critical
and non-Boolean logic
Jan 25, 2008

E0-286@SERC

19

Parallel
Parallel Fault
Fault Simulation
Simulation
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
1

a
b

1
1

s-a-0
0

Jan 25, 2008

c s-a-0 detected

0
s-a-1

E0-286@SERC

20

Thank You
Jan 25, 2008

E0-286@SERC

21

You might also like