Birla Institute of Technology and Science, Pilani- KK Birla Goa
Campus
Instruction Division
First Semester 2012-13
Course Handout (Part-II)
Date: 03/08/12
In addition to Part I (General Handout for all the courses appended to the time table),
this portion gives further specific details regarding the course.
Course No.
Course Title
Instructor-in-charge
Instructor
Tutorial & Lab Instructors
: CS /EEE /INSTR F215
: Digital Electronics and Computer Organization
: K.R.Anupama
: Ch.S.Sankhar Reddy
: A.Amalin Prince, M.A.Bhamare, Sarang Dhongdi,
Santosh Kumar, Preeti Jayabal, S.S.Sahu, Prateek
Bindra
Course Description:
This course covers the topics on logic circuits and
minimization, Combinational and sequential logic circuits,
Programmable Logic devices, State table and state
diagrams, Digital ICs, Arithmetic operations and
algorithms, Introduction to Computer organization,
Algorithmic State Machines.
Scope and Objective:
The objective of the course is to impart knowledge of the
basic tools for the design of digital circuits and to provide
methods and procedures suitable for a variety of digital
design applications. The course also introduces
fundamental concepts of computer organization. The
course also provides laboratory practice using MSI devices,
Xilinx ISE software tools and FPGA.
Text Books.
:
1. M.Moris Mano, Digital Design, PHI, 3rd Edition, 2002.
2. Brian Holdsworth, Clive Woods Digital Logic Design, Elsevier, 4th Edition
,2008
.
Reference Books:
R1. Donald D. Givone., Digital Principles and Design TMH, 2003
R2. Robert K.Dueck, Digital Design with CPLD Applications and VHDL.,
Thomson, 2002.
Course Plan:
Lect.
No.
1
Learning Objectives
Topics to be covered
Introduction to Digital
Systems and
Characteristics of
Digital ICs.
Codes number systems
Digital Systems, Digital ICs
Reference to Text
Book
1.1; 1.9; 2.8
Number systems and codes
1.2-1.8
Boolean Algebra
Simplification of
Boolean functions
Simulation and
synthesis basics
Law of Boolean Algebra, KMaps (4,5 variables),
QM Method
Hardware Description
Language
2.1-2.7, 3.1 to 3.3,
3.5 to 3.8
7-9
Combinational Logic,
Arithmetic circuits
Adders, Subtracters
Multipliers
4.1 - 4-6
10-12
MSI Components
4.7 to 4.10
AS-2
Simulation of
Combinational Logic
Functions.
Digital Integrated
Circuits
Sequential Logic
Comparators, Decoders,
Encoders, MUXs, DEMUXs
HDL for Combinational
Logic
TTL, MOS Logic families
and their characteristics
Flip-Flops & Characteristic
tables, Latches.
Analysis of clocked
sequential circuits, state
diagram and reduction
Shift registers, Synchronous
& Asynchronous counters
Asynchronous Sequential
Logic
HDL for Sequential Logic,
HDL for registers and
counters
RAM, ROM, PLA, PAL
Multiplication & Division
algorithms
RTL, HDL description
10.3, 10.5, 10.7 to
10.10
5.1 to 5.3
Algorithmic State Machines
R2. Chapter 8
Memory Hierarchy &
different types of memories
T2: Ch 6
T1.
2- 6
AS1
13-14
15-16
17-18
Clocked Sequential
Circuits
19-23
Registers & Counters
24-28
Design of
Asynchronous Circuits.
Simulation of
Sequential Logic
Functions.
Memory and PLDs
Analysis of arithmetic
units
Modular approach for
CPU Design
Design of Digital
Systems
Memory Organization
AS3
29-30
31-32
33-35
36-38
39-40
3.9
4.11
5.4, 5.6
6.1 to 6.5
9.1 9.7
5.5, 6.6
7.1, 7.5 to 7.7
T2: Appendix A
8.1,8.2, 8.4 to 8.7
Evaluation Scheme:
Component
Duration
Maximum
Marks
Date
Remarks
CB
CB/OB
Test I
Theory
60 Min
40
Test II
60 Min
40
Comprehensive Examination
3 Hrs
100
16/9/2012
8:30-9:30 AM
29/10/2012
8:30- 9:30 AM
8/12/2012
Practicals: H/w Lab
Evaluation
Practicals: S/w Lab
Evaluation
Project
H/w Lab Comprehensive
S/w Lab Comprehensive
_____
40
Regularly
OB
20
Regularly
OB
30
30
10
To be announced
15/11-21/11
To be announced
OB
OB
OB
Lab
Project: To be announced in the class
Chamber Consultation Hour: To be announced in the class
Notices: On Moodle
Make-up Policy:
Prior Permission of the Instructor-in-Charge is required to take a make-up
and make-up will be granted only for medical reasons approved by the
Institutes Chief Medical Officer
INSTRUCTOR-IN-CHARGE
OB
