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L 6: T H e 8 0 8 6 M I C R o P R o C e S S o R H A R D W A R e

The document describes the pins and signals of the 8086 microprocessor. It details the functions of pins like VCC, GND, CLK, READY, AD/DATA, AD/STATUS, RD, BHE/S7, RESET, NMI, INTR, MN/MX and others. It explains the operating modes, bus request/grant sequence and functions of signals like LOCK in minimum and maximum mode.

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Mohammad Samheel
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63 views7 pages

L 6: T H e 8 0 8 6 M I C R o P R o C e S S o R H A R D W A R e

The document describes the pins and signals of the 8086 microprocessor. It details the functions of pins like VCC, GND, CLK, READY, AD/DATA, AD/STATUS, RD, BHE/S7, RESET, NMI, INTR, MN/MX and others. It explains the operating modes, bus request/grant sequence and functions of signals like LOCK in minimum and maximum mode.

Uploaded by

Mohammad Samheel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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L6: The 8086 Microprocessor Hardware

The 8086 Signals

Functional pin diagram

Microprocessors (BME 307)

Page 1

Pin Diagram

Pin Descriptions
Vcc: Single +5V power supply.
GND: Have to be connected to ground ( 2 pins).
Clock: For timing purposes, generated using an external clock generator chip 8284 clock
generator.
READY
* 4 clock cycles Machine cycle

Microprocessors (BME 307)

Page 2

CLK
T1

T2

T3

T4

READY
Sampling
Address /Data :AD15 - 0
16 data pins bidirectional.
20 address lines LS 16-bits (A15-0) are multiplexed with the data bus.
During T1 of the machine cycle LS 16-bits of the address is sent on these pins.
In the later part of the machine cycle (T2-T4) sends out or receives the data role changes
to data bus.
Address / Status: A19-16/S6-3
* A19-16: provide the most significant 4 bits of the address
* These bits are sent during T1 of the machine cycle
* In the subsequent cycles different status information S6-3 are sent on these lines
* S4-3: The segment register (segment) to be used for accessing the data
*
*
*
*

* S5: Status of Interrupt Enable flag (IF)


* S6: always 0, not used

RD Read
* Active low output
* To get information (data) from memory or I/O port

Microprocessors (BME 307)

Page 3

BHE / S7: Bus High Enable / Status


* During T1, BHE is sent by the processor to enable higher order data bus for accessing
memory
* In the subsequent cycles S& is sent always 0 spare status signal used by numeric
co-processor to determine whether the CPU is 8086 or 8088
* 0: 8086 , 1: 8088

RESET
*
*
*
*
*
*
*

High for at least 4-clock cycles


CPU starts from a clearly defined initial state
CS reg is set to FFFFH
IP reg is set to 0000H
All other registers are set to 0000H
INTR is disabled
Starts fetching instruction from memory location FFFF0H

NMI and INTR


NMI: Non-maskable interrupt input cant be prevented.
INTR: Interrupt Request maskable interrupt request can be prevented using the IF bit in the
flags register.
Used to carry out critical task requests given by the peripherals or other hardwares in the system.

MN/MX
*
*
*
*

Used to switch the operating mode of the microprocessor


If HIGH Minimum mode Single processor mode for simple systems.
If LOW Maximum mode multiple processors for complex system.
Mode is permanently fixed.

Minimum mode signals ( Pin 24 to 31)


*
*

Functions of pin 24 to 31 depends on the operating mode of the microprocessor.


Minimum mode signals bus control signals of minimum mode.

WR

Microprocessors (BME 307)

Page 4

M/IO

ALE

INTA

HOLD

HLDA

DT/R

DEN

TEST
* Maximum mode signal.
* Used only in the multi-processor mode.
* When processor has to wait for the result from co-processors WAIT instruction is used.
* On execution of WAIT processor waits for the result from co-processor.
* Once the result is ready co- processor drives TEST line low processor reads the result and
continues further.
* To synchronize with the co-processor.

Maximum mode signals


* Status S0, S1 and S2
* Queue status QS0 & QS1
* RQ0/ GT0 and RQ1/GT1
* LOCK

Status signals
Microprocessors (BME 307)

Page 5

Queue Status
Allows the co-processor to track the internal queue of the 8086.

RQ0/GT0 and RQ1/GT1


Request/Grant
These pins are used by the other local bus master in maximum mode, to force the
processor to release the local bus at the end of the processor current bus cycle.
Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
RQ/GT pins have internal pull-up resistors and may be left unconnected.

Request/Grant sequence
Microprocessors (BME 307)

Page 6

1. A pulse of one clock wide from another bus master requests the bus access to 8086.
2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it will
enter the hold acknowledge state at next cycle. The CPU bus interface unit is likely to be
disconnected from the local bus of the system.
3. A one clock wide pulse from the another master indicates to the 8086 that the hold request
is about to end and the 8086 may regain control of the local bus at the next clock cycle.
Thus each master to master exchange of the local bus is a sequence of 3 pulses.
*
*
*

There must be at least one dead clock cycle after each bus exchange.
The request and grant pulses are active low.
For the bus request those are received while 8086 is performing memory or I/O cycle, the
granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum
mode.

LOCK

Output pin, indicates that other system bus master will be prevented from gaining the system
bus, while the LOCK signal is low.

The LOCK signal is activated by the LOCK prefix instruction and remains active until the
completion of the next instruction. When the CPU is executing a critical instruction which
requires the system bus, the LOCK prefix instruction ensures that other processors
connected in the system will not gain the control of the bus.

The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which
may be connected to an external bus controller.

Microprocessors (BME 307)

Page 7

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