module mux41(

input [1:0] s,
input [3:0] d,
output y);
wire [1:0] s;
wire [3:0] d;
reg y;
always @ (s or d)
begin
y = d[s];
end
endmodule
`timescale 1ns / 1ps
module mux41_tb();
reg [1:0] S;
reg [3:0] D;
wire MyOutput;
mux41 mux1(.s(S), .d(D), .y(MyOutput));
initial begin
D = 1;
S = 0;
#100;
S = 1;
#100;
S = 2;
#100;
S = 3;
#100;
D = 2;
S = 0;
#100;
S = 1;
#100;
S = 2;
#100;
S = 3;
#100;
end
endmodule

Verilog Notes:
==============
module and3 ( i0, i1, i2, o);
input i0;
input i1;
input i2;
output o;

each statement ends with a ";"

endmodule
module and3 ( input i0, //input 1
input i1, //input 2
input i2, //input 3
output o); //output 1

endmodule
module and3 ( input i0, i1, i2, //inputs
output o); //output 1

endmodule
a block of statements
start
....;
....;
....;
end
extension of .v
comments //till end of line /* multi line */

Logic Operators:
---------------and
or
not

& (bitwise)
|
~

xor

nand

~&

and
or

&& (logical)
||

x = 1010

y = 0101 x && y => False

x & y => 0000

Relational Operators:
--------------------==
!=
<
>
<=

equal
not equal
less than
greater than
less or equal

>=

greater or eaqual

Arithmetic Operators:
---------------------+
*
/
%
**
{,}

modules
exponent
concatenation

Shift Operators:
---------------A << 1 shift left once
A >> 1 shift right once

1100 shift left 100x

1100 shift right x110

Data Types:
----------values:
0
1
z
x

low
false
high
true
high impedance
unknown

net
wire
register
reg
vector wire[3:0] reg[1:0]

(bundled wires)

wire[7:4],wire[3:0]
wire[0:3]
Endianness
reg[3:0] a = 7;
reg[3:0] b = 4'b0110; 4'd7;
integer
real
====================================
e.g.
half adder
module half_adder(
input a,
input b,
output s,
output c);
reg c,s;
wire a,b;
xor XOR1 (s, a, b);
and AND1 (c, a, b);
begin
assign s = a ^ b;

assign c = a & b;
end
always@(a or b)
begin
s = a ^ b;
c = a & b;
end
endmodule
Most important step in successful design is: PLANNING
Exercise:
A = 1100

B = 1001

A & B
A && B
A | B
~|(A)

`timescale 1ns / 1ps

//without clear option
module sr(
input d,
input c,
input cl,
output q,
output q_bar
);
// method 1
wire w1, w2, w3, w4;
not
and
and
nor
nor

I1 (w4, d);
(w1, d, c);
(w3, c, w4);
(q_bar, q, w1);
(q, q_bar, w3);

// method 2
/*
reg q, q_bar;
always @ ( d or c )
if (c)
begin
q <= d;
q_bar <= ~d;
end
*/
/*

//method 3
wire w1, w2, w3, w4;
INV I1 (w4, d);
AND2 A1 (w1, d, c);
AND2 A2 (w3, c, w4);
NOR2 NO1 (q_bar, q, w1);
NOR2 NO2 (q, q_bar, w3);
*/
endmodule
=======================
`timescale 1ns / 1ps
//with clear option
module sr(
input d,
input c,
input cl,
output q,
output q_bar
);
/*
// method 1
wire w1, w2, w3, w4;
not I1 (w4, d);
and (w1, d, c);
and (w2, c, w4);
or (w3, w2, cl);
nor (q_bar, q, w1);
nor (q, q_bar, w3);
*/
/*
// method 2
reg q, q_bar;
always @ ( d or c or cl )
if (cl)
begin
q <= 1'b0;
q_bar <= 1'b1;
end
else if (c)
begin
q <= d;
q_bar <= ~d;
end
*/
//method 3
wire w1, w2, w3, w4;
INV I1 (w4, d);
AND2 A1 (w1, d, c);
AND2 A2 (w2, c, w4);
OR2 O1 (w3, cl, w2);
NOR2 NO1 (q_bar, q, w1);
NOR2 NO2 (q, q_bar, w3);

endmodule
====================================
`timescale 1ns / 1ps
// test bench
module sr_tb;
// Inputs
reg d;
reg c;
reg cl;
// Outputs
wire q;
wire q_bar;
// Instantiate the Unit Under Test (UUT)
sr uut (
.d(d),
.c(c),
.cl(cl),
.q(q),
.q_bar(q_bar)
);
initial begin
// Initialize Inputs
d = 0;
c = 0;
cl = 0;
#50;
//clear
cl = 1;
#50;
cl = 0;
#100;
d = 0;
c = 0;
cl = 0;
#100;
// Wait 100 ns for global reset to finish
d = 1;
c = 0;
cl = 0;
#100;
d = 1;
c = 0;
cl = 0;
#100;
d = 1;
c = 1;
cl = 0;
#100;
d = 0;

c = 1;
cl = 0;
#100;
d = 1;
c = 0;
cl = 0;
#100;
// Add stimulus here
end
endmodule
=====================

primitives:
primitive myand(
output o,
input i0,
input i1);
table
//i0 i1 : o
0 ? : 0; // ? = 0 or 1 or x
? 0 : 0; // b = 0 or 1
1 1 : 1;
x x : x;
1 x : x;
x 1 : x;
endtable
endprimitive

delays:
module testmyand(
//primitive #<time> <inst> (nodes);
//#<rise, fall, off>
//#<max:def:min>
not #10 N1 (w1, c);
not #10 N2 (w2, b);
endmodule
control statements
==================
if(cond)
begin
statement;
statement;
end
else

statement;
case(select)
0: out = a;
1: out = b;
default out = 1'bx;
endcase
loops
=====
integer i;
for (i=0; i<8; i=i+1)
begin
...;
...;
end
while (i<8)
begin
...;
i= i+1;
end
block
=====
begin:checkparity
...;
...;
if (cond) distable checkparity;//skip rest of the loop
...;
...;
end

http://www.play-hookey.com/digital/sequential/jk_nand_flip-flop.html
`timescale 1ns / 1ps
`include "flipflop.v"
////////////////////////////////////////////////////////////////////////////////
// User definded primitives dont simulate in Xilinx ISE
////////////////////////////////////////////////////////////////////////////////
module ff_tb;
// Inputs
reg e;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)

/*ff uut (
.e(e),
.d(d),
.q(q)
);*/
flipflop uut (.q(q), .en(e), .d(d));
initial begin
// Initialize Inputs
e = 0;
d = 0;
// Wait 100 ns for global reset to finish
#100;
e = 0;
d = 1;
#100;
e = 1;
d = 1;
#100;
e = 0;
d = 0;
#100;
e = 1;
d = 0;
#100;
e = 0;
d = 1;
#100;
e = 1;
d = 1;
#100;
e = 0;
d = 0;
#100;
e = 1;
d = 0;
#100;
// Add stimulus here
end
endmodule
`timescale 1ns / 1ps
`include "flipflop.v"
////////////////////////////////////////////////////////////////////////////////
//
// User definded primitives dont simulate in Xilinx ISE
////////////////////////////////////////////////////////////////////////////////
//
module ff(
input e,
input d,
output q
);
reg q;

flipflop FF1(.q(q), .en(e), .d(d));

endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
//
// User definded primitives dont simulate in Xilinx ISE
////////////////////////////////////////////////////////////////////////////////
//
primitive flipflop(
output q,
input en,
input d
);
reg q;
table
//en d : q_curr : q_next;
1 1 : 1 : 0;
0 1 : 1 : 0;
1 0 : 1 : 0;
0 0 : 1 : 0;
1 1 : 0 : 1;
0 1 : 0 : 1;
1 0 : 0 : 1;
0 0 : 0 : 1;
endtable
endprimitive

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
//
module mux(
input a0,
input a1,
input a2,
input a3,
input s0,
input s1,
output o
);
output [3:0] o;
input [3:0] a0, a1, a2, a3;
input s0, s1;
reg o;
always@(a0 or a1 or a2 or a3 or s0 or s1)
if (s0 == 0)

begin
if (s1 == 0)
o = a0;
else
o = a1;
end
else
begin
if (s1 == 0)
o = a2;
else
o = a3;
end
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
//
module mux(
input a0,
input a1,
input a2,
input a3,
input s,
output o
);
output [3:0] o;
input [3:0] a0, a1, a2, a3;
input [1:0] s;
reg o;
assign o = 4'b0;
always@(a0 or a1 or a2 or a3 or s0 or s1)
if (s == 0)
o =
else if (s == 1)
o =
else if(s == 2)
o =
else
o =

a0;
a1;
a2;
a3;

endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
//
module mux(

input a0,
input a1,
input a2,
input a3,
input s,
output o
);
output [3:0] o;
input [3:0] a0, a1, a2, a3;
input [1:0] s;
reg o;
assign o = 4'b0;
always@(a0 or a1 or a2 or a3 or s0 or s1)
case (s)
0 : o = a0;
1 : o = a1;
2 : o = a2;
3 : o = a3;
default: o = 4'b0;
endcase
endmodule

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module mux_tb;
// Inputs
reg a0;
reg a1;
reg a2;
reg a3;
reg s;
// Outputs
wire o;
// Instantiate the Unit Under Test (UUT)
mux uut (
.a0(a0),
.a1(a1),
.a2(a2),
.a3(a3),
.s(s),
.o(o)
);
initial begin
// Initialize Inputs
a0 = 0;

a1 = 0;
a2 = 0;
a3 = 0;
s = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
forever
/*
begin
//#5 clk = ~clk;
#100 s = 2'b00;
#100 s = 2'b01;
#100 s = 2'b10;
#100 s = 2'b11;
end
*/
begin
#100 s[0] = ~s[0]
end
begin
#200 s[1] = ~s[1]
end

endmodule

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
//
module seven_seg(
input [3:0] s,
output [6:0] o
);
assign
case (s)
0 : o =
1 : o =
2 : o =
default
endmodule

7'b011_1111;
7'b101_1011;
7'b111_0011;
o = 7'b100_0001;