EE/CE 6301: Advanced Digital Logic

Bill Swartz
Dept. of EE
Univ. of Texas at Dallas
EEDG/CE6301 B. Swartz

Session 11
Multi-Level Optimization

State Minimization - Example

Map states to flow table

Flow table

State Minimization Implication Chart

B

AC
--

AD
--

X marks output
conflicts

D
E

--BC

Flow table

AD
--

--BC

Implication Chart
First pass

State Minimization Implication Chart

B

AC
--

AD
--

X marks output
conflicts

D
E

--BC

Flow table

AD
--

--BC

Implication Chart
Second Pass Transitive Closure
Is any checked boxes a next state?
If true, mark that box as well.
In this case, we have to check for BC and BE
5

State Minimization Compatible Pairs

B

AC
--

AD
--

Enumerate Chart
Right to Left
Bottom to Top

D
E

--BC

Flow table

AD
--

--BC

From Column D, nothing compatible

From Column C, we have CE and CD
From Column B, we get BD
From Column A, we get AD, AC, and AB
6

State Minimization Incompatible Pairs

B

AC
--

AD
--

Enumerate Chart
Right to Left
Bottom to Top

D
E

--BC

Flow table

AD
--

--BC

From Column D, we find DE

From Column C, everything compatible
From Column B, we find BE, and BC
From Column A, we get AE
7

State Minimization - Result

B

AC
--

AD
--

D
E

--BC

Flow table

AD
--

--BC

Implication Chart

State Minimization Compatible Cliques

Graph Representation build chord graph
A

From Column D, nothing compatible

From Column C, we have CE and CD
From Column B, we get BD
From Column A, we get AD, AC, and AB

State Minimization Incompatible Cliques

Graph Representation build chord graph

From Column D, we find DE

From Column C, everything compatible
From Column B, we find BE, and BC
From Column A, we get AE

10

State Minimization Trial and Error

A

Graph Representation
Cummulative
Set here!

Note carefully that three conditions must be

satisfied:
1. Completeness: all states must be covered
2. Minimality: the smallest number of
compatibles required is chosen.
3. Consistency: Next states of each selected
maximal compatibles (cliques) is contained by
another maximal compatible within the
selected set.

Order is trial
and error
11

State Minimization Pick CE

A

Graph Representation
E

Next
State

Present
State

A
B
C
D
E

Present
State

X=0

X=1

A,
C,
D,
-,
A,

B, B, -,B, 1
C, -

1
0
0

Flow table

Combine
CE

A
B
CE
D

Next
State
X=0

X=1

A, C, 1
AD, 0
-, -

B, B, C,B, 1

Closure Table

12

State Minimization Update Graph

A

Graph Representation
E

Mark or delete edge

from graph
Next
State

Present
State

A
B
C
D
E

Present
State

X=0

X=1

A,
C,
D,
-,
A,

B, B, -,B, 1
C, -

1
0
0

Flow table

Combine
CE

A
B
CE
D

Next
State
X=0

X=1

A, C, 1
AD, 0
-, -

B, B, C,B, 1

Closure Table

13

State Minimization Pick ABD

Graph Representation

Present
State

A
B
CE
D

Next
State

Present
State

X=0

X=1

A, C, 1
AD, 0
-, -

B, B, C,B, 1

Flow table

Combine
ABD

ABD
CE

Next
State
X=0

X=1

AC, 1
AD, 0

B, 1
C,-

Closure Table

14

State Minimization Update Graph

Graph Representation

C
What about ACD?

Present
State

A
B
CE
D

Next
State

Present
State

X=0

X=1

A, C, 1
AD, 0
-, -

B, B, C,B, 1

Combine
ABD

ABD
CE

Next
State
X=0

X=1

AC, 1
AD, 0

B, 1
C,-

ACD would form

AD,1 and B, 1
which is not present in any row!
Cant remove rows until all
states are covered! State E was
an exception because no other
interaction with any other state
than C.
You can see this in the graph
representation. Edge AD is
missing from the clique in
graph.

Closure Table

15

State Minimization Pick ABD redo

Graph Representation

Present
State

A
B
CE
D

Next
State

Present
State

X=0

X=1

A, C, 1
AD, 0
-, -

B, B, C,B, 1

Combine
ABD

A
ABD
CE
C
D

Next
State
X=0

X=1

A, AC, 1
AD, 0
D, 0
-, -

B, B, 1
C,-,B, 1

Closure Table

Dont remove rows

until the end

16

State Minimization Update graph

Graph Representation

Present
State

A
ABD
CE
C
D

Next
State

Present
State

X=0

X=1

A, AC, 1
AD, 0
D, 0
-, -

B, B, 1
C,-,B, 1

Combine
ABD

A
ABD
CE
C
D

Next
State
X=0

X=1

A, AC, 1
AD, 0
D, 0
-, -

B, B, 1
C,-,B, 1

Closure Table

Delete only edges

not in common
with the remaining
cliques

17

State Minimization Pick ACD

Graph Representation

Present
State

A
ABD
CE
C
D

Next
State

Present
State

X=0

X=1

A, AC, 1
AD, 0
D, 0
-, -

B, B, 1
C,-,B, 1

Combine
ACD

A
ABD
ACD
CE
C
D

Next
State
X=0

X=1

A, AC, 1
AD, 0
AD, 0
D, 0
-, -

B, B, 1
B, 1
C,-,B, 1

Closure Table

18

State Minimization Update Graph

Graph Representation

Present
State

A
ABD
CE
C
D

Next
State

Present
State

X=0

X=1

A, AC, 1
AD, 0
D, 0
-, -

B, B, 1
C,-,B, 1

Combine
ACD

A
ABD
ACD
CE
C
D

Next
State
X=0

X=1

A, AC, 1
AD, 0
AD, 0
D, 0
-, -

B, B, 1
B, 1
C,-,B, 1

Closure Table

No chords left!
Remove covered
rows

19

Conditions for State Reduction (cont.)

Rename states
P = ABD
Q= ACD
R = CE

How do we
know how to
name the next
state? Renamed
state must cover
or contain
original state

,1

,1

,0
,0

,1

Closure Table

,--

Reduced Table

20

Conditions for State Reduction (cont.)

Considering condition 3:
A

Can be Q or P because AD is
contained in (ABD) as well as
(ACD)

,1

,1

,0
,0

,1

Closure Table

,--

Reduced Table

21

Can we reduce more?

If we ignore condition 3:

Note carefully that three conditions

must be satisfied:
1. Completeness: all states must be
covered
2. Minimality: the smallest number of
compatibles required is chosen.
3. Consistency: Next states of each
selected maximal compatibles
(cliques) is contained by another
maximal compatible within the
selected set.

ABD
ACD
CE

A
x
x

B
x

C
x
x

Present State
ABD=P
CE=R

Present State
P
R

D
x
x

Next State
X=0
X=1
AC,1
B,1
AD,0 C, --

Next State
X=0
X=1
?,1
P,1
P,0
R, --

Which one?
A is contained in P
C is contained in R

22

Requirements for Proper Operation

1. Only one input change at a time (fundamental
mode assumption).
2. The state assignment (transition table) is free of
critical race
3. The excitation logic is hazard free
4. The minimum propagation delay is satisfied
5. The maximum propagation delay is satisfied

23

Race-Free State Code Assignment

Example of a flow table

State Diagram
Contains information of flow table in
graphical form

xy
S

00

01

11

10

S*

xy+xy

B
xy

xy

y
C

xy

D
24

Race-Free State Code Assignment

xy+xy

xy

xy

xy

Need to assign each of the states an unique

binary pattern

25

State Assignment Guidelines

For m states, we need at least r bits such that
2 r 1 m 2 r or r log 2 m
Number of ways to select m codes out of 2r codes

2r
2r !

m m!( 2 r m)!

Number of ways to assign m selected codes to m state

is m!.
Overall, number of ways to assign r-bit codes to m
states
r
r

2!
2!
m! r
r
m!(2 m)!
(2 m)!

Only some of these will be race-free. For previous

example, m=4, r=2, we have total of 24 assignments 8
of which are race-free and only 3 unique
26

State Assignment
Not all state assignments are unique or distinct
Complementing a bit does not increase complexity of
logic
Similarly, swapping columns of bits does not change
circuit complexity
For two state circuits, only one unique assignment
For three and four state circuits, there are only 3 unique
assignments out of 24
Number of unique state assignments is given by:
=

2 1 !
2 ! !

27

State Assignment
Number of unique state assignments is given by:
=
States

Flip-flops

2 1 !
2 ! !
Possible states

Unique states

24

24

6,720

140

20,160

420

40,320

840

40,320

840

415x107

10,810,800

10

219x108

75,675,600

28

Adjacent States
Each bit of the encode state may be represented by a
flip-flop bit
An encode of the state forms a vector of length r:
1 2 1 0

Two state vectors are said to be adjacent if they differ

in only one bit position
Two states, A and B, are said to be adjacent if their
state vectors are adjacent

29

Adjacency Graph
Edge between adjacent states
Let
State

e1

e0

This is not the

state transition
graph!
30

Unique assignments of 4 states

D B

D C

D B

D A

D C

D A

D C

D B

D B

D A

D A

D C

Shift sequence by one bit to

left and rotate in from right

Mirror image of first

sequence around y axis

Unique vectors are {ABCD, ABDC, and ADBC}

Move D to unique position in ring sequence
24 total assignment
3 unique
Only 1 of 3 a Gray code (named after Frank Gray of Bell Labs 1947)

31

Gray code assignment

Given previous
A
encoding:
B

D C

D C

D B

D B

State

e1

e0

32

Races
A race exists when two or more secondary variables
must change when the circuit makes a transition from
one stable state to another
If the circuit reaches the correct stable state, it is non-

critical

If the circuit reaches an erroneous state, the race is said

to be critical
A circuit is said to have a cycle when it goes thru a
unique sequence of unstable states

33

Transitions
May go thru cycle

x
1 0

00

10

00

01

01

11

11

01

10

10

11

00

01 -> 11 -> 10 -> 00

00 -> 10 -> 11 -> 01

34

Transitions
Oscillation

x
1 0

00

--

01

01

01

11

11

--

10

10

--

00

01 -> 11 -> 10 -> 00 -> 01 -> 11 ->

35

Assignment Rules
How do we avoid critical races and oscillations?

36

Example with Critical Race

State diagram
Confusing! Why?
Bad engineering practice
State table

37

Example with Critical Race

State diagram uses S0, S1, Sn to
denote state
Implies that this is the encoding
Look state S1 is encoded 11
Bad convention

38

Without convention
In Sept 1999, NASA lost a $125 million Mars
orbiter because a Lockheed Martin engineering
team used English units of measurement while
the agencys team used the more conventional
metric system for a key spacecraft operation,
according to a review finding released Thursday.
The units mismatch prevented navigation
information from transferring between the Mars
Climate Orbiter spacecraft team in at Lockheed
Martin in Denver and the flight team at NASAs
Jet Propulsion Laboratory in Pasadena,
California.

Convention to minimize errors

Moore machine directly uses state encoding
Natural biases
How can we do this applied to states?

40

Convention in this class

Perhaps, states all are capital alphabetic letters
starting from A, ie, A, B, C, D,
All circuit inputs or literals should be italicized
lower case to denote the difference
Encoding flip-flops bits are denoted with script
letter

41

Example with Critical Race

State diagram
Now is it clear why it is
confusing?
Plus this edge is wrong direction

State table

42

Example with Critical Race

State diagram
A

1 0
0 0

1 0
1 1

x
B

1 0
0 1

Unused
encoding 1 0
1 0

43

Example with Critical Race

Now transition from state A with input
change to x
x

1 0
0 0

01

1 1

1 0

1 0

1 0

Unused state D encoded

1 0 = 1 0
Oops!
44

Adding Dummy States

Original state diagram
A

Adding a dummy state

to make it race-free and
change encoding

x
1 0
0 0

1 0
1 0

1 0
0 1

1 0
0 1

x
x

1 0
1 1

1 0
0 0

1 0
1 1

45

New State Table

Now table looks like
this:
x

11

0 1

1 0

1 0
0 0

1 0
0 1

x
1 0
1 0

1 0
0 0

1 0
1 1

46

A Worst Case Scenario

4-state adjacency diagram
Wrong! This is not the
adjacency graph
Assignment using pairs of equivalent states

47

A Worst Case Scenario

4-state state transition graph

Assignment using pairs of equivalent states

C
110

B
100

D
111
A
010

B
011

D
000

C
001
A
101

48

State Assignment Guidelines (cont.)

For a general flow table with 2n rows (states),
we can define a race-free assignment (not
necessarily minimum length) using 2n-1 bits.
Need to assign tables with more than two rows!

49

Assignment Methods
Need to avoid critical races
Proposed Methods:
Shared-Row
Multiple-Row
One-Hot
Race-Free State Assignments for Synthesizing
Large-Scale Asynchronous Sequential Logic Circuits,
P.D. Fisher and Sheng-Fu Wu, IEEE Transactions on
Computers, September 1993 (vol. 42 no. 9), pp.
1025-1034.

50

Shared-Row Method
Include an extra row in the flow table to
introduce a cycle into each transition that
contributes a critical race
New row is shared by two stable states

51

What constitutes a critical race?

More than one different stable state in a column
Columns with only one stable state can be
removed from critical race consideration
xy

A
S

00

01

11

10

y
xy
xy

xy
C

52

What constitutes a critical race?

Every column has one stable state
No critical races
Any arbitrary assignment will work
xy

A
S

00

01

11

10

53

Shared-row state assignment

Multiple stable states in a column
xy
xy
S

00

01

11

10

xy
xy

xy

xy

54

Shared-row state assignment

Arbitrarily assign encodings from both ends
1 0
0 0

xy

xy

xy

xy
1 0
1 0

xy

xy
xy

xy

1 0
0 1

enc

00

01

11

10

00

01

10

11

Efficient but difficult (trial and error)

55

Shared-row Example
4 Columns are all critical
xy

xy

A
xy

xy
x'y

x'y

xy

00

01

11

10

56

Shared-row Example
Insert new nodes in edges to remove races
xy

xy

A
xy

xy
x'y
G

E
xy

x'y

Use K map to work out adjacencies

xy

enc

00

01

11

10

000

001

010

100

011

00

01

11

10

110

101

F
57

Multiple-Row Method
Notice how the K-map helped us
Universal assignment for 4 states

xy
00

01

11

10

58

Multiple-Row Method
But the universal assignment is not unique
xy
00

01

11

10

xy
00

01

11

10

59

Multiple-Row Method
Start with one row per state. If the state
transition has multiple bit changes, duplicate
the row and use the universal assignment to
assign the states.

60

Multiple-row Example Revisited

4 Columns are all critical
xy

xy

A
xy

xy
x'y

x'y

xy

00

01

11

10

61

Multiple-row Example Revisited

Duplicate rows and use adjacency table
xy

xy
00

01

11

10

00

01

11

10

A1

B1

C1

D1

A1

C2

A1

B1

A1

C2

D2

A2

B2

A2

C1

A2

B2

A2

B1

B1

C1

B1

A1

B2

B2

C2

B2

A2

C1

C1

C1

D1

D1

C2

C2

C2

D2

D2

D1

B2

A1

D1

D1

D2

B1

A2

D2

D2

Look in the universal table

and find adjacency

62

Multiple-row Example Revisited

Duplicate rows and use adjacency table
yz

xy

enc

00

01

11

10

A1

000

C2

A1

B1

A1

A2

111

C1

A2

B2

A2

B1

001

B1

C1

B1

A1

B2

110

B2

C2

B2

A2

C1

011

C1

C1

D1

D1

C2

100

C2

C2

D2

D2

D1

010

B2

A1

D1

D1

D2

101

B1

A2

D2

D2

00

01

11

10

A1

B1

C1

D1

C2

D2

A2

B2

63

Multiple-row Example Revisited

Show encoding and reorder rows
yz

xy

enc

00

01

11

10

A1

000

C2

A1

B1

A1

B1

001

B1

C1

B1

A1

C1

011

C1

C1

D1

D1

D1

010

B2

A1

D1

D1

B2

110

B2

C2

B2

A2

A2

111

C1

A2

B2

A2

D2

101

B1

A2

D2

D2

C2

100

C2

C2

D2

D2

00

01

11

10

A1

B1

C1

D1

C2

D2

A2

B2

64

Multiple-row state assignment

Can be extended to any number of states using
a predefined table
Inefficient but straight forward
wx
yz

00

01

11

10

00

A1

B1

C1

D1

01

E1

F1

G1

H1

11

C2

D2

A2

B2

10

G2

H2

E2

F2

65

Other state assignment methods

One-Hot
Each state has one 1 in it
A: 0001
B: 0010
C: 0100
D: 1000

State transitions become new states which are

the logical OR of the two final states
66

One-hot method
Insertion into every edge

67

Race-Free State Assignments for

Synthesizing Large-Scale Asynchronous
Sequential Logic Circuits
P.D. Fisher and Sheng-Fu Wu, IEEE Transactions on
Computers, September 1993 (vol. 42 no. 9), pp. 10251034.

68

Hazards

69

Hazard
Temporary wrong output calculation due to
propagation delay
Static
Static-1 starts in 1, ends up in 1 but transitions to 0
Static-0 starts in 0, ends up in 0 but transitions to 1

Dynamic
Multiple transitions
Cant occur if no static hazards exist

70

Avoiding Output Glitches

Sometimes you need to change the dont-cares
to care situations to avoid possible glitches.
Otherwise, after optimization some glitches may
be generated.
Example: (a) original, (b) decided by optimizer,
(c) and (d) guided by replacing some of dontcares.

71

Adding Dummy State Example

Theoretically 2 bits are
enough to encode 4 states.
But it is not race-free.
Using 3 bits

72

Static Hazard on the Outputs

If the Boolean expression is reduced to AA or A+A, the
possibility of static hazard (glitch) exist

73

Static Hazard - Examples

When B=C=1, f is reduced to A+A

1-hazard

When B=C=0, f is reduced to AA

0-hazard

74

Hazard-Free Implementation
Function f=ABC+(A+B)(A+D)

Function f

75

Hazard Free Implementation D-Latch

To be on the safe side and avoid undesired transitions,
hazard-free equations for state variables and output
functions should be used.
Example: unreliable D-latch (subject to static-1 hazard)

Adjacent 1s not
covered by the same
Prime Implicant

Reliable D-latch (hazard eliminated)

Redundant
Term

76

Hazard Free Implementation D-Latch (cont.)

QCD: 111101 ; Assume 1 time unit delay for each gate
X
C

Q
C
D

1 Hazard

X
Y
Q*
X
C

Z
Q*

Z
77

Hazard Free Implementation - T-FF

Behavior of T Flip-Flop

78

Hazard Free Implementation - T-FF

Possibility of hazard

ABC: 110111 (No hazard)

Only C: 10
causes 1-hazard

ABC: 111110 (1-hazard)

79

Hazard-Free Implementation T-FF

One possible implementation

80

Dynamic Hazard on the Outputs

Those cases that
instead of 10 we get 1010
Instead of 01 we get 0101

In SoP and PoS circuits, if there are no static

hazards, then the circuit will have no dynamic
hazards.
81

Dynamic Hazard - Example

82

Functional Hazard on the Outputs

This is due to multiple-bit change (or sequence of single-bit
change according to the fundamental mode assumption)
They appear as 0-hazard or 1-hazard
Example

Static 1-hazard occurs

Static 0-hazard occurs

83

Essential Hazards
This is caused by a race between
An input signal and
A state variable

Usually, if input transition time (ti) is bigger than state

transition time (tt), incorrect circuit operation will occur.
Example: Suppose we are in S0 and X:01 occurs.
Correct operation (ti<tt)
X:01 and AB:0001 (S0S1)
Incorrect operation (ti>tt)
X:001 and AB:000111 (S0S1S2)

84

Timing Issues

85

Timing Requirement One Change at a Time

Only one input signal changes at a time, with a minimum
bound between successive input changes

86

Timing Requirement Maximum Delay

Maximum propagation delay through excitation logic and
feedback paths is less than the time between successive
input changes
Tmax_prop + Tfeedback < Tmin_input=1/fmax_input

87

Timing Requirement Minimum Delay

Minimum propagation delay through excitation logic and
feedback paths is greater than the maximum timing skew
through input logic
Tmin_prop + Tfeedback > Tmax_skew_input

88

Design Procedure Pulse Catching Example

89

Basic Design Steps

1. Construct the primitive flow table from the
circuits word description.
2. Minimize the number of states in the flow table.
3. Find a race-free assignment for the coded states,
adding auxiliary states or splitting the states as
required.
4. Construct the transition table.
5. Construct the excitation maps and obtain a
hazard-free realization of the equations.
6. Draw the logic diagram.
7. Check for essential hazards. Modify the circuit if
needed.
90

A Pulse-Catching Circuit Example

Design an asynchronous (feedback) circuit with
two inputs P (pulse) and R (reset) and a signal
output Z that is normally zero. The output should
become 1 whenever a 01 transition occurs on P,
and should be reset to 0 whenever R is 1.

91

A Pulse-Catching Circuit Example

Design an asynchronous (feedback) circuit with
two inputs P (pulse) and R (reset) and a signal
output Z that is normally zero. The output should
become 1 whenever a 01 transition occurs on P,
and should be reset to 0 whenever R is 1.
Typical behavior

92

Pulse-Catching Flow Table

The primitive flow table

93

Pulse-Catching State Minimization

94

State Assignment
No race-free assignment using 2-bits codes exist. Add one
transitional state (IDLE) to have it.

95

K-Map Optimization

Y 1* P R P Y 1
Y 2* Y 2 R'Y 1'Y 2 P Y 1'P R'
Z Y2

96

Circuit Implementation
All functions are static hazard-free
Y 1* P R P Y 1
Y 2* Y 2 R'Y 1'Y 2 P Y 1'P R'
Z Y2

97

Essential Hazards
Essential hazard occurs if the input change is not
seen by all of the excitation logic before the
resulting state transitions propagate back to the
inputs.

Essential hazards exists in a flow table if there is a

stable state from which three consecutive
changes in a single input variable will take the
circuit to a different state than the first change
alone.
98

Check for Essential Hazards

99

Avoiding Essential Hazards

Essential hazards are called essential because they are
inherent in the flow table for a particular sequential
function, and will appear in any circuit realization of that
function.
Essential hazards can be masked only by controlling the
delays in the circuit. Compare with static hazard in
combinational logic, where we could eliminate hazards by
adding consensus terms to a logic expression.
In previous example, the only way to avoid the erroneous
behavior is to ensure that changes in P arrive at the inputs
of all the excitation logic before any changes in state
variables do. That is Tmin_prop + Tfeedback > Tmax_skew_input 100

Design Procedure Double-Edge Pulse Catching Example

101

Review of Basic Design Steps

1. Construct the primitive flow table from the
circuits word description.
2. Minimize the number of states in the flow table.
3. Find a race-free assignment for the coded states,
adding auxiliary states or splitting the states as
required.
4. Construct the transition table.
5. Construct the excitation maps and obtain a
hazard-free realization of the equations.
6. Draw the logic diagram.
7. Check for essential hazards. Modify the circuit if
needed.
102

Double-Edge Pulse Catching Example

Design a fundamental mode circuit with two inputs x1
and x2 and a single output z. The circuit output is to be
z=0 whenever x1=0. The first change (01 or 1 0) in
the input x2 occurring while x1=1, will cause the circuit
output to go to 1. The output is then to remain 1 until
x1 returns to 0. Changes in inputs will always be
separated sufficiently in time to permit the circuit to
stabilize before a second input transition takes place.
Typical Behavior

103

Double-Edge PC Example (cont.)

Typical Behavior

Flow Table

Blanks are dont cares

104

State Minimization
Implication Chart (Initial and Final)

All compatibles (e.g. cliques in graph representation):

(12)(13)(24)(5678)
Smallest collection (e.g. covering table): (13)(24)(5678)

105

Minimal Flow Table

106

Design Procedure Control Delay Example

107

Control Delay Example

Design a circuit that has a control pulse input x, a clock input
C and a control pulse output z. Pulses on line x will always be
separated by several clock periods. Whenever a pulse occurs
on line x, it will overlap a clock pulse and be of approximately
the same width as a clock pulse. That is line z will only go to
1 after the clock has gone to 1 and will return to 0 only after
the clock has returned to 0. For each input pulse, there is to
be an output pulse on line z coinciding with the next clock
pulse following the x pulse. Thus each x pulse results in a z
pulse delayed by approximately one clock period.

108

Control Delay Example (cont.)

Typical Behavior

Flow Table

Blanks are dont cares

109

State Minimization
Implication Chart

110

Minimal Flow Table

Replace dont cares carefully to avoid glitches

111

State Assignment Race Exists

This is not a race-free assignment

State Assignment (Y2Y1)

Critical race exists for
110100 or
111000

112

State Assignment Race Exists (cont.)

K-Maps

113

State Assignment Race Exists (cont.)

If the gates have unequal delays, the change in C will
first drive the output of A1 to 1, which will in turn drive
A2 to 0 before the output of A3 goes to 1. As a result,
Y1 will not change and the circuit will make an
erroneous transition to Y2Y1=01 (i.e. state 01 instead
of 00 in the first column).

114

Race-Free Assignment
This is not a race-free assignment

State Assignment (Y2Y1)

115

Race-Free Assignment (cont.)

K-Maps

Z=Y2
116

Race-Free Assignment (Cont.)

This circuit will be race-free provided the input
pulses satisfy the fundamental mode
constraints.

117

Design Procedure Lamp Switching Example

EEDG/CE6301 - M. Nourani

118

Lamp Switching Example

Design a switching circuit by which an operator
can control two lights. If switch X is made
followed by switch Y, then a red lamp (LR) is to
be turned on indicating that an incorrect
switching procedure has been followed. If
switch Y is made followed by switch X, then a
green lamp (LG) is to be turned on indicating
that a correct procedure has been adopted.

119

State Diagram and State Table

120

State Minimization
S0=S1
S0=S2

S0=S3
S0=S4
S1=S2
S3=S4

Compact Representation

121

Implementation
K-Maps

SR latch can be used to provide

feedbacks
SR latch: Q* = S + R Q
Here: A* = X Y + Y A
So, S=X Y and R=Y
X
Y

Q(A)

122

Implementation (SR-Latch Mapping)

More formal mapping of Next state function to SR latch
can be done similar to synchronous design approach

SR-latch transition table

xy
A 00

01

11

10

0
1

x
S=XY

xy
A 00

01

11

10

0
1

0
R=Y

X
Y

Q(A)

123

Modified Lamp Switching Example

Same as before only add an extra state to go back to
quiescent state S0 after a light is turned on.

124

State Minimization
No critical race exists.

125

Design Procedure Pump Control Example

126

Pump Control Example - Problem Definition

Water is pumped into a water tank by two

pumps p1 and p2. Both pumps are to turn on
when the water goes below level 1 and they are
to remain on until water reaches level 2, when
pump p1 turns off and remains off until water is
below level 1 again. Pump p2 remains on until
level 3 is reached when it also turns off and
remains off until water falls below level 1 again.
Sensors
a=1 when water is at or above level 1, otherwise a=0
b=1 when water is at or above level 2, otherwise b=0
c=1 when water is at or above level 3, otherwise c=0
127

Pump Control Example - Schematic

System schematic and input/output

128

State Diagram
Original vs. Modified state diagram to get racefree assignment

129

Implementation
5-variable K-Map needed. For example for A* :

130

Implementation (cont.)
One typical implementation (direct or using SR
latch)

131

Design Procedure Sequence Detector Example

132

Sequence Detector - Problem Definition

Design a sequence detector which has two
inputs X1 and X2, and one output Z. The circuit is
required to give an output Z=1 when the
sequence of input signals X1X2=00, 10, 11 has
occurred.
System schematic

133

State Diagram
A typical FSM construction

134

Flow Table
Before and after state minimization

135

Race-Free State Code Assignment

Adding dummy state to avoid race
Arithmetic State
Machine (ASM)

136

K-Maps
Choose a state assignment

AB

X1X2

00

01

11

00

01

10

11
10
=(X1X2+ BX2+AX1)

=(AX1X2+AB)

Z=AB

137

Implementation Direct Feedbacks

Direct feedbacks
A+= (X1 X2 + B X2 + A X1)
B+= A X1 X2 + A B
Z = A B

138

Implementation Using SR Latch

Do re-mapping using SR-latch transition table

139

Implementation Using SR Latch (cont.)

Final circuit

140