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ASIC Library Design: Application-Specific Integrated Circuits

This document discusses ASIC library design and characterization. It states that ASIC design is typically done using predefined library cells that were optimized for speed and area without knowledge of the specific application. Being aware of how load capacitance and fan-out affect cell performance allows designers to optimally use library cells for their applications. It also provides figures illustrating CMOS inverter models and their parameters, as well as the concept of logical effort for analyzing gate delays.

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manoranjan varshney
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61 views12 pages

ASIC Library Design: Application-Specific Integrated Circuits

This document discusses ASIC library design and characterization. It states that ASIC design is typically done using predefined library cells that were optimized for speed and area without knowledge of the specific application. Being aware of how load capacitance and fan-out affect cell performance allows designers to optimally use library cells for their applications. It also provides figures illustrating CMOS inverter models and their parameters, as well as the concept of logical effort for analyzing gate delays.

Uploaded by

manoranjan varshney
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 3

ASIC Library Design

Application-Specific Integrated Circuits


Michael John Sebastian Smith
Addison Wesley, 1997
EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

ASIC Library Design

ASIC design is usually performed using a predefined and


precharacterized library of cells

In designing this library, the original designer had to optimize


speed and area without knowing the actual application that
the cells will be used for - i.e., how large a load they will be
driving

wire load
fanout load

Being aware of the source and effect of these trade-offs will


make it easier to understand how to optimally design using
the library cells

EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

Model of CMOS Inverter with Parasitic


Resistances and Capacitances

Figure 3.1

A model for CMOS logic delay. (a) A CMOS inverter with load capacitance. (b) Input and output waveforms
showing the definition of falling propagation delay tPDF. (c) The switch model of the inverter showing parasitic
resistances and capacitances.

EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

Effect of Load Capacitance on Inverter


Performance
Figure 3.3

Simulation of an inverter
driving a variable number of
gates on its output

EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

Parasitic Capacitances of a CMOS


Transistor
Figure 3.4 Transistor parasitic
capacitance. (a) An Nchannel MOS transistor
with gate length L and
width W. (b) The
components of the gate
capacitance. (c)
Approximating
capacitances with planar
components. (d) The
components of the diffusion
capacitance. (e)-(h) The
dimensions of the gate,
overlap, and sidewall
capacitances.

EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

CMOS Inverter: Steady State Response


VDD

VDD

RPon

VOH = VDD
Vout

Vout

VOL = 0

VM = f(RNon,RPon)

RNon

RNon 1/WN
Vin = V DD

EGRE 427 Advanced Digital Design

Vin = 0

RPon 1/WP
Figures
from
material provided with
DigitalCircuits,
Integrated
Circuits,
A Design
Figures
from
Application-Specific
Integrated
Michael
John
Sebastian
Perspective,
Jan Rabaey,
Smith,
Addison by
Wesley,
1997 Prentice Hall, 1996

CMOS Inverter VTC

NMOS off
PMOS lin

Vou t

NMOS sat
PMOS lin

NMOS sat
PMOS sat

NMOS lin
PMOS sat

EGRE 427 Advanced Digital Design

NMOS lin
PMOS off
5

Vin

Figures
from
material provided with
DigitalCircuits,
Integrated
Circuits,
A Design
Figures
from
Application-Specific
Integrated
Michael
John
Sebastian
Perspective,
Jan Rabaey,
Smith,
Addison by
Wesley,
1997 Prentice Hall, 1996

The Ideal Gate

Vout

Ri =
Ro = 0
g=

Vin

Vm = Vdd/2
EGRE 427 Advanced Digital Design

Figures
from
material provided with
DigitalCircuits,
Integrated
Circuits,
A Design
Figures
from
Application-Specific
Integrated
Michael
John
Sebastian
Perspective,
Jan Rabaey,
Smith,
Addison by
Wesley,
1997 Prentice Hall, 1996

Balanced CMOS Inverter


Assume that due to differences in p and n, for a minimum
sized transistor, Rp = 2Rn
For a balanced inverter we want RP = RN, so in this case, WP
must be 2WN
VDD

WP/LP = 2/1
Vin

Vout
CL

WN/LN = 2/1

EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

Logical Effort

Figure 3.8 Logical effort. (a) The input capacitance looking into the input capacitance of a minimum size inverter. (b) Sizing a
logic cells transistors to have the same delay as a minimum size inverter. (c) The logical effort of a cell is C in/Cinv.

EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

Logical Effort Of a Complex Gate

Figure 3.10 An AOI221 cell with logical effort vector g=(8/3, 8/3, 7/3).
EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

The Basic Trade-off


to other gates (fanout)

to other gates (fanout)

Which is faster?

to other gates (fanout)


buffer

to other gates (fanout)


EGRE 427 Advanced Digital Design

Figures from Application-Specific Integrated Circuits, Michael John Sebastian


Smith, Addison Wesley, 1997

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