TP2804

TP2804
8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Features
General Description
The TP2804 is an 8-bit microcontroller which has an
Fully static design of 8-bit CMOS microcontroller
in-system programmable FLASH EPROM for firmware
Running clock up to 40MHz
updated.
64K-byte FLASH EPROM
Its instruction set is fully compatible with
the standard 8051.

EPROM,
512-byte
It contains a 64K-byte FLASH

on-chip
RAM,
four
Low standby current at full supply voltage
8-bit
512-byte
on-chip
RAM
(including
256-byte
bi-directional and bit-addressable I/O ports, an
AUX-RAM, software selectable)
additional 4-bit I/O port, three 16-bit timer/counters
64K-byte program memory address space and
and one serial port.
64K-byte data memory address space
Applications
Four 8-bit bi-directional ports

One 4-bit multipurpose programmable port
LCD Monitor
Three 16-bit timer/counters
LCD TV
One full duplex serial port

Eight-source and two-level interrupt capability
Built-in power management
Code protection
Two voltage types: 3.3V and 5V
Package Forms: DIP40, PLCC44 and PQFP44
Ordering Information
Voltage
TP2804
Package Type
Package Type
Voltage
L: 3.3V
H: 5V
P: DIP
C: PLCC
Q: PQFP
Block Diagram
P1.0
Port
1
P1.7
Port 1
Latch
A
B
P0.0
Port 0
Interrupt
T1
Timer
2
Latch
T2
Port
0
P0.7
DPTR
Timer
0
PSW
Stack
Pointer
ALU
Timer
1
Temp Reg.
PC
Intcrementor
UART
Intcrementor
P3.0
Port
3
Port 3
Latch
Instruction
Decoder &
Sequencer
P3.7
INT2 / INT3
SFR RAM
Address
64KB
MTP-ROM
512 bytes
RAM & SFR
P2.0
Port 2
P4.0
P4.3
Bus&Clock
Controller
Port 4
Port
4
P2.7
Latch
Oscillator
XTAL1
Data Sheet - Version 1.2

June 2004
Latch
Port
2
XTAL2
Page 1 of 17
Reset Block
ALE
PSEN
RST
Power control
VCC
VSS
http://www.topro.com.tw
TP2804
Pin Configuration
40-PIN DIP
P1.4
P1.3
P1.2
P1.1,T2EX
P1.0,T2
P4.2,INT3
VDD
P0.0,AD0
P0.1,AD1
P0.2,AD2
P0.3,AD3
44
43
42
41
40
44-PIN PQFP
PSEN
INT1,P3.3
15
31
P2.7,A15
T0,P3.4
16
30
P2.6,A14
T1,P3.5
17
29
P2.5,A13
28
32
A12,P2.4
14
27
ALE
INT0,P3.2
A11,P2.3
33
26
13
A10,P2.2
P4.1
TXD,P3.1
25
34
A9,P2.1
12
24
EA
INT2,P4.3
A8,P2.0
35
23
11
P4.0
P0.7,AD7
RXD,P3.0
22
36
VSS
10
21
P0.6,AD6
RST
XTAL1
37
20
XTAL2
P0.5,AD5
P1.7
19
P0.4,AD4
38
18
39
RD,P3.7
P1.6
WR,P3.6
P1.5
P1.4
P1.3
P1.2
P1.1,T2EX
P1.0,T2
P4.2,INT3
VDD
P0.0,AD0
P0.1,AD1
P0.2,AD2
P0.3,AD3
44
43
42
41
40
44-PIN PLCC
PSEN
INT1,P3.3
15
31
P2.7,A15
T0,P3.4
16
30
P2.6,A14
T1,P3.5
17
29
P2.5,A13
28
32
A12,P2.4
14
27
ALE
INT0,P3.2
A11,P2.3
33
26
13
A10,P2.2
P4.1
TXD,P3.1
25
34
A9,P2.1
12
24
EA
INT2,P4.3
A8,P2.0
35
23
11
P4.0
P0.7,AD7
RXD,P3.0
22
36
VSS
10
21
P0.6,AD6
RST
XTAL1
37
20
XTAL2
P0.5,AD5
P1.7
19
P0.4,AD4
38
18
39
RD,P3.7
P1.6
WR,P3.6
P1.5

June 2004
Page 2 of 17
TP2804
Pin Description
Symbol
Type
EA
PSEN
O/H
ALE
O/H
RST
I/L
XTAL1
XTAL2
VSS
VDD
P0.0 - P0.7
P1.0 - P1.7
P2.0 - P2.7
P3.0 - P3.7
P4.0 - P4.3
O
I
I
I/O/D
I/O/H
I/O/H
I/O/H
I/O/H
Description
EXTERIAL ACCESS ENABLE: This pin should be forced to high level and the program
counter is within the 64 KB area.
PROGRAM STORE ENABLE: When internal ROM access is performed, no PSEN
strobe signal output is originated from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE
pulse is omitted during external data memory accesses.
RESET: A high on this pin for two machine cycles resets the device while the oscillator is
running.
CRYSTAL 1: This is the crystal oscillator input. The pin may be driven by an external
clock.
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential.
POWER SUPPLY: Supply voltage for operation.
PORT 0: Function is the same as that of standard 8051.
PORT 4: A bi-directional I/O port with internal pull-ups.
NOTES: TYPE I: input; O: output; I/O: bi-directional; H: pull-high; L: pull-low; D: open drain.
Functional Description
The TP2804 architecture consists of a core controller
with the MOVX instruction.
surrounded by various registers, four general-purpose
are R0 and R1 of the selected register bank and
I/O port, 512-byte RAM, three timer/counters, a serial
DPTR register.
port.
after a reset.
Its processor supports 111 different opcodes
Address pointers
The AUX-RAM is disabled

Setting the bit 4 in CHPCON
and references, both 64K program address space and
register will enable the access to on-chip
64K data storage space.
AUX-RAM.
RAM
Timers 0, 1, and 2
The internal data RAM of TP2804 has 512 bytes and
Timers 0, 1, and 2 each consist of two 8-bit data

registers. These are called TL0 and TH0 for Timer 0,
is divided into two banks: scratchpad 256-byte RAM
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer
and
256-byte
AUX-RAM.
These
RAMs
are
2. The TCON and TMOD registers provide control
addressed by different ways:
functions for timers 0 and 1.
The T2CON register
provides control functions for Timer 2. RCAP2H and

RAM 00H-7FH can be addressed directly and
RCAP2L are used as auto-reload or capture registers
indirectly as the same as in 8051.
for Timer 2 as it in 8051.
Address
pointers are R0 and R1 of the selected register
The operations of Timer 0 and Timer 1 are the same
bank.
as the standard 8051.
Timer 2 is a 16-bit
timer/counter that is configured and controlled by the

RAM 80H-FFH can only be addressed indirectly
T2CON register. Like timers 0 and 1, Timer 2 can
as the same as in 8051.
operate as either an external event counter or as an
Address pointers are
internal timer, depending on the setting of bit C/T2 in
R0 and R1 of the selected registers bank.
T2CON.
AUX-RAM 00H-FFH is addressed indirectly as
clock speed at capture or auto-reload mode is the
the same way to access external data memory

June 2004
Timer 2 has three operating modes:
capture, auto-reload, and baud rate generator. The

same as that of timers 0 and 1.
Page 3 of 17
TP2804
INT 2
INT 3
EX3: External interrupt 3 enable if set.
Two additional external interrupts,
INT 3 ,
INT 2
IE3: If IT3 = 1, IE3 is set/cleared automatically by
and
hardware when interrupt is detected/serviced.
whose functions are similar to those of
external interrupt 0 and 1 in the XICON (External

Interrupt Control) register.
IT3: External interrupt 3 is falling-edge/low-level
The XICON register is
triggered when this bit is set/cleared by software.
bit-addressable but is not a standard register in the

standard 8051.
Its address is at 0C0H. To set/clear
PX2: External interrupt 2 priority high if set.
bits in the XICON register, one can use the SETB

( INT 3 ) bit instruction.
EX2: External interrupt 2 enable if set.
XICON external interrupt control

(C0H)
IE2: If IT2 = 1, IE2 is set/cleared automatically by
PX3
EX3
IE3
IT3
PX2
EX2
hardware when interrupt is detected/serviced.
IE2
IT2
IT2: External interrupt 2 is falling-edge/low-level

triggered when this bit is set/cleared by software.
PX3: External interrupt 3 priority high if set.
Eight-source Interrupt Information

Interrupt Source
External Interrupt 0
Timer/Counter 0
Timer/Counter 1
Serial Port
Timer/Counter 2
Vector
Address
03H
0BH
13H
1BH
23H
2BH
33H
3BH
Polling Sequence
Within Priority Level
0 (highest)
1
2
3
4
5
6
7 (lowest)
Enable Required
Settings
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
XICON.2
XICON.6
Interrupt Type
Edge/Level
TCON.0
TCON.2
XICON.0
XICON.3
Watchdog Timer
The Watchdog timer is a free-running timer that can
NOTES:
be programmed by the user to serve as a system
ENW: Enable watchdog if set.
monitor, a time-base generator or an event timer.
CLRW: Clear watchdog timer and prescaler if set.
It
is basically a set of divider that divides the system
This flag will be cleared automatically.
clock and the divider output is selectable and
WIDL: If this bit is set, the watchdog is enabled under
determines the time-out interval for the time-out
IDLE mode.
system monitor.
under IDLE mode.
This is important in the real-time
control applications.
In case of power glitches or
Prescaler is selected when set PS2~0 as follows:
If this is left
unchecked, the entire system may crash.
PS2 PS1 PS0

0 0 0
0 1 0
0 0 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The
watchdog time-out selection will result in different

time-out values depending on the clock speed, and
the watchdog timer will be disabled on reset.
In
general, software should restart the watchdog timer to

put it into a known state.
Default is cleared.
PS2, PS1, PS0: Watchdog prescaler timer select.
electro-magnetic interference, the processor may

begin to execute errant code.
If cleared, the watchdog is disabled
The control bits that
support the watchdog timer are discussed as follows:
Prescaler Select
2
4
8
16
32
64
128
256
Watchdog Timer Control Register (8FH)

Bit
7
ENW
6
CLRW

June 2004
5
WIDL
4
-
3
-
2
PS2
1
PS1
0
PS0
Page 4 of 17
TP2804
Clock
internal trigger circuit in the reset line is used to
The TP2804 should be used with either a crystal
an external RC network. The reset logic also has a
oscillator or an external clock.
special glitch removal circuit that ignores glitches on
deglitch the reset line when the TP2804 is used with
Internally, the clock is
divided by twelve before it is used by default. This
the reset line.
During reset, the ports are initialized
makes the TP2804 relatively insensitive to duty cycle
to FFH, the stack pointer to 07H, PCON (with the
variations in the clock.
exception of bit 4) to 00H, and all of the other SFR

registers except SBUF to 00H. SBUF is not reset.
Crystal Oscillator
The TP2804 incorporates a built-in crystal oscillator.
To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2.
In
addition, a load capacitor must be connected from

each pin to ground, and a resistor must also be
connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHZ.
External Clock
An external clock should be connected to pin XTAL1.
Pin XTAL2 should be left unconnected. The XTAL1
input is a CMOS-type input as required by the crystal
oscillator.
Consequently, the external clock signal
should have an input of one level greater than 3.5

volts.
Power Management
Idle Mode
By setting the IDL bit in the PCON register, the idle
mode is set up. In the idle mode, the internal clock
to the processor is stopped.
The peripherals and the
interrupt logic continue to be clocked. The processor

will exit idle mode when either an interrupt or a reset
occurs.
Power-down Mode
When the PD bit in the PCON register is set, the
processor enters the power-down mode.
In this
mode, all of the clocks are stopped including the

oscillator. To exit from the power-down mode, it is by
a hardware reset or external interrupts
INT 3
INT 0
to
when enabled and set to edge triggered.
Reset
The external RESET signal is sampled at S5P2. To
take effect, it must be held high for at least two
machine cycles while the oscillator is running.

June 2004
An
Page 5 of 17
TP2804
TP2804 Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
FF
+B
00000000
ISP_CTRL
00000000
+ACC
00000000
+P4
xxxx1111
+PSW
00000000
+T2CON
00000000
XICON
00000000
+IP
00000000
+P3
00000000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
F7
ISP_ADDR
00000000
EF
E7
DF
D7
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
CF
C7
CHPCON
0xx00000
BF
B7
AF
A7
SBUF
xxxxxxxx
9F
97
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
TH1
00000000
WDTC
00000000
PCON
00110000
8F
87
In-System Programming Control Register (CHPCON)

The TP2804 equips one main Flash EPROM bank of
001XXXXXb, the application program range is
64K bytes for application program, but it can be set
from address 0000h to F1FFh and loader program
for a maximum of 4K-byte loader program and
range is from address F200h to FFFFh and so on.
60K-byte
of
User can enter ISP mode with two different ways.
application program depends on the content
One is by software, for example, using JMP F000h
(bit5~bit7) of address FFFFh in the 64K bytes.
to loader program address.
application
program.
The
size
If
one unit is 512 bytes, user can set for eight
hardware.
different units (000~111). For example, if the data
microcontroller executes the code in the 64K bytes.
of address FFFFh is 000XXXXXb, the application
If the content of application program needs to be
program range is from address 0000h to EFFFh
modified, the TP2804 allows user to activate the
and loader program range is from address F000h
In-System Programming (ISP) mode by setting the
to FFFFh.
CHPCON register.
If the data of address FFFFh is
In
the
normal
The other is by
operation,
the
CHPCON (BFH)
Bit
Name
SWRESET
6
5
ENAUXRAM
3
2
1
0
0
FPROGEN

June 2004
Function
When this bit is and FPROGEN are set to 1, it will enforce microcontroller reset to initial
condition just like power on rest.
Reserve.
Reserve.
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
Reserve
Must set to 0.
Must set to 0
FLASH EPROM Programming Enable.
= 1: enable. The microcontroller enter the in-system programming mode.
= 0: disable. The on-chip flash memory is read-only. In-system programmability is disabled.
Page 6 of 17
TP2804
ISP_CTRL(E8H)
Bit
7
6
5
4
3
2
1
0
Name
ISP_EN
1
0
ERASE
Write
READ
The Reset Timing for Entering ISP Mode
Function
1:ISP enable
Reserve.
Reserve.
Must 1
Must 0
Erase bit
Program write into AUX RAM
Read program from AUX RAM
Name
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Hi-Z
P2.6
Hi-Z
RST
30ms
10ms
ISP_ADDR(E9H)
Bit
7
6
5
4
3
2
1
0
P2.7
Security
Function
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
During the on-chip FLASH EPROM programming mode,

the FLASH EPROM can be programmed and verified
repeatedly. Until the code inside the FLASH EPROM is
confirmed OK, the code can be protected.
The
protection of FLASH EPROM and those operations on it
Hardware Enter ISP MODE
are described below.
When the reset pin of TP2804 is at high level and any of
The TP2804 has several Special Setting Registers,
the two conditions described below is fit in.
including
the
Security
Register
that
cannot
be
programmed from low to high. They can only be reset

P4.3
X
L
P2.7
L
X
P2.6
L
X
Mode
ISP
ISP
through erases-all operation.
Special Setting Registers

0000h
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5
B1
Security Bits
B1 : Lock bit, logic 0 : active

B5~B7 : Set ISP Address
B7 B6 B5
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
64KB Flash EROM

Program Memory
APROM
Address
F000~FFFF
F200~FFFF
F400~FFFF
F600~FFFF
F800~FFFF
FA00~FFFF
FC00~FFFF
FE00~FFFF
FFFFh Security Register
XReserved
Lock bit
This bit is used to protect the customers program code
Once this bit is set to logic 0, both the Flash EROM data
in the TP2804.
and Setting Registers cannot be accessed again.
It may be set after the programmer
finishes the programming and verifies the sequence.

June 2004
Page 7 of 17
TP2804
Absolute Maximum Ratings
(VDD-VSS = 5V 10% for TP2804H, VDD-VSS = 3.3V 10% for TP2804L)
Parameter
DC Power Supply
Input Voltage
Operation Temperature
Storage Temperature
Symbol
VDD-VSS
VIN
TA
TST
Min
-0.3
VSS-0.3
0
-55
Max
VDD+1
VDD+0.3
70
+150
Unit
V
V
C
C
NOTE: Exposure to conditions beyond those listed under Absolute

Maximum Ratings may adversely affect the life and reliability of the
device.
DC Electrical Characteristics
(VDD-VSS = 5V 10% for TP2804H, VDD-VSS = 3.3V 10% for TP2804L, TA = 25C,
Fosc = 12MHz, unless otherwise specified)
Parameter
Operating Voltage
Operating Current
Idle Current
Symbol
VDD
IDD
IIDLE
Min
0.9 VDD
-
Max
1.1 VDD
20/8
6/3
Power Down Current
IPWDN
100
IIN1
-50
+10
A VIN = 0V or VDD
IIN2
-10
+300
A 0VINVDD
VIL1
0.2VDD 0.2
VDD
VIL2
VIL3
0
0
0.2VDD 0.2
0.2VDD 0.3
V
V
VDD
VDD
VIH1
3.5/2.6
VDD+0.2
VDD = 5.5V/3.3V
VIH2
VIH3
3.5/2.6
3.5/2.6
VDD+0.2
VDD+0.2
V
V
VOL1
0.45
VOL2
0.45
VDD = 5.5V/3.3V
VDD = 5.5V/3.3V
VDD = 5V/3.3V
IOL = +2mA
VDD = 5V/3.3V,
IOL = +4mA
ISK1
8/6
mA
VDD = 5V/3.3V, VIN = -0.45V
ISK2
8/6
mA
VDD = 5V/3.3V,
VIN = 0.45V
VOH1
2.4/2.0
VDD = 5V/3.3V
VOH2
2.4/2.0
VDD = 5V/3.3V
I S r1
-120/-80
-200/-120
VDD = 5V/3.3V,
VIN = 2.4V
Input Current
P1, P2, P3, P4
Input Current RST
Input Low Voltage
P0, P1, P3, P4, EA
Input Low Voltage RST
Input Low Voltage XTAL1*4
Output Low Voltage
P1, P2, P3, P4, EA
Input High Voltage RST
Input High Voltage XTAL1*4
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
*3
P0 , ALE, /PSEN
Sink Current
P1, P3, P4
Sink Current
P0, P2, ALE, /PSEN
Output Low Voltage
P1, P2, P3, P4
Output High Voltage
*3
P0 , ALE, /PSEN
Source Current
P0, P2, P3, P4
Unit
Test Condition
V RST = 1, P0 = VDD
mA No load, VDD = 5V/3.3V
mA Idle mode, VDD = 5V/3.3V
Power-down mode,
A
VDD = 5V/3.3V
NOTES:
1.
RST pin is an Schmitt trigger input.
2.
P0, ALE and /PSEN are tested in the external access mode.
*3.
XTAL1 is a CMOS input.
*4.
Pins of P1, P2, P3 and P4 can source a transition current when they are being externally driven 1 to 0.
The
transition current reaches its maximum value when VIN approximates to 2V.

June 2004
Page 8 of 17
TP2804
AC Electrical Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the
capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input
clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. The numbers below represent the
performance expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
Parameter
Operating Speed
Clock Period
Clock High
Clock Low
Symbol
FOP
TCP
TCH
TCL
Min
0
25
10
10
Max
40
-
Unit Test Conditions

MHz
1
nS
2
nS
3
nS
3
NOTES:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL 1 input.
Clock lnput Waveform
XTAL1
TCH
T CL
FOP. TCP
Data Read Cycle

Parameter
ALE Low to /RD Low
/RD Low to Data Valid
Data Hold from /RD High
Data Float from /RD High
/RD Pulse Width
Symbol
TDAR
TDDA
TDDH
TDDZ
TDRD
Min.
3 TCP-
0
0
6 TCP-
Typ.
6 TCP
Max.
-3 TCP+
4 TCP
2 TCP
2 TCP
-
Unit
nS
nS
nS
nS
nS
Notes
1, 2
1
NOTES:
1.
Data memory access time is 8 TCP.
2.
due to buffer driving delay and wire loading is 20 nS.
Data Write Cycle

Parameter
ALE Low /WR Low
Data Valid to /WR Low
Data Hold from /WR High
/WR Pulse Width
Symbol
TDAW
TDAD
TDWD
TDWR
Min.
3 TCP-
1 TCP-
1 TCP-
6 TCP-
Typ.
6 TCP
Max.
3 TCP
-
Unit
nS
nS
nS
nS
NOTE:
due to buffer driving delay and wire loading is 20 nS.
Port Access Cycle

Parameter
Port lnput Setup to ALE Low
Port lnput Hold from ALE Low
Port Output to ALE
Symbol
TPDS
TPDH
TPDA
Min.
1 TCP
0
1 TCP
Typ.
-
Max.
-
Unit
nS
nS
nS
NOTES:
1.
Ports are read during S5P2, and output data becomes available at the end of S6P2.
2.
The timing data are referenced to ALE, since it provides a convenient reference.

June 2004
Page 9 of 17
TP2804
Timing Waveforms
1.
Data Read Cycle
XTAL1
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S6
S1
S2
S3
ALE
PSEN
A8-A15
PORT 2
A0-A7
DATA
PORT 0
TDAR
TDDA
TDDH ,TDDZ
RD
TDRD
2.
Data Write Cycle
XTAL1
S4
S5
S6
S1
S2
S3
S4
S5
S2
S3
ALE
PSEN
PORT 2
A8-A15
A0-A7
PORT 0
DATA OUT
TDAD
TDWD
WR
TDAW

June 2004
TDWR
Page 10 of 17
TP2804
Timing Waveforms (continued)
3.
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
T PDH
TPDA
DATA OUT
PORT
INPUT
SAMPLE

June 2004
Page 11 of 17
TP2804
Application Diagrams
1.
Internal Program, Memory and Crystal

VCC
C4
10uF
40
C3
0.1uF
C1
U2
31
19
S1
RESET
C5
10uf
Y1
VCC
VCC
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
R2
18
X2
C2
9
R1
10k
RESET
12
13
14
15
VSS
TP2804
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
20
1
2
3
4
5
6
7
8
INT0
INT1
T0
T1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Figure A
CRYSTAL
6MHz
16MHz
24MHz
32MHz
40MHz
C1
47P
30P
15P
10P
5P
C2
47P
30P
15P
10P
5P
R2
6.8K
4.7K
NOTE: Above table shows the reference values for crystal applications.

June 2004
Page 12 of 17
TP2804
2.
Expanded External Program and Data Memory and Oscillator

VCC
U1
P27
P26
P25
P24
P23
P22
P21
P20
OSC1
VCC
14
C2 1
0.1uF
VCC OSC
1
VSS
8
VCC
OSC
C3
0.1uF
C6
10uF
31
3
28
4
25
23
26
27
5
6
7
8
9
10
11
12
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
32
VDD
16
22
30
29 WE
24 RD
VSS
CS1
CS2
WE
OE
21
20
19
18
17
15
14
13
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
C1
0.1uF
VCC
P07
P06
P05
P04
P03
P02
P01
P00
W24512A
U2
VCC
31
19
S1
RESET
C5
10uF
18
9
R1
10K
P32
P33
P34
P35
12
13
14
15
P10
P11
P12
P13
P14
P15
P16
P17
1
2
3
4
5
6
7
8
EA/VP
X1
X2
U3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/P
TXD
RXD
39
38
37
36
35
34
33
32
P00
P01
P02
P03
P04
P05
P06
P07
21
22
23
24
25
26
27
28
P20
P21
P22
P23
P24
P25
P26
P27
17
16
29
30
11
10
RD
WE
1
11
P00 3
P01 4
P02 7
P03 8
P04 13
P05 14
P06 17
P07 18
ALE
P31
P30
U4
OC
C
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
74LS373
VCC
C7
CAP
2
5
6
9
12
15
16
19
10
9
8
7
6
5
4
3
P20 25
P21 24
P22 21
P23 23
P24 2
P25 26
P26 27
P27 1
20
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
11
12
13
15
16
17
18
19
P00
P01
P02
P03
P04
P05
P06
P07
E
G/VPP
27C512
VCC
C4
0.1uF
TP2804
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
GND
Figure B

June 2004
Page 13 of 17
TP2804
Package Information
40-pin DIP
Unit: Inch
Dimension in Inch
Symbol
NOTES:
1. Dimension D Max. includes mold flash or tie bar burrs.
Min.
Nom.
Max.
0.220
A1
0.015
2. Dimension E1 does not include interlead flash.

3. Dimensions D and E1 include mold mismatch and are determined
at the mold parting line.
4. Dimension B1 does not include dam bar protrusion/intrusion.
A2
0.150
0.155
0.160
0.018
B1
0.050
2.055
2.060
2.070

June 2004
5. JEDEC Outline: MS-011 AC
0.600 BSC
E1
0.540
0.545
0.550
e1
0.100
0.115
0.130
0.150
15
eA
0.630
0.650
0.670
Page 14 of 17
TP2804
44-pin PLCC
HD
D
6
44
40
39
17
29
GE
HE
E
18
28
GD
A
A2
L
e
A1
b1
Unit: Inch
Symbol
A
Nom.
Max.
0.185
A1
0.020
A2
0.145
0.150
0.155
b1
0.026
0.028
0.032
0.016
0.018
0.022
0.007
0.010
0.013
0.648
0.653
0.658
0.648
0.653
0.658
e
GD
1. Dimensions D and E do not include interlead flash and

mold protrusion.
Allowable protrusion is 10 mil per
side.
2. Dimension b1 does not include dam bar
protrusion/intrusion.
3. JEDEC Outline: M0-047 AC.
0.050 BSC
0.590
0.610
0.630
GE
0.590
0.610
0.630
HD
0.680
0.690
0.700
HE
0.680
0.690
0.700
0.090
0.100
0.110

June 2004
NOTES:
Dimension in Inch
Min.
Page 15 of 17
TP2804
44-pin PQFP
Unit: Millimeter
Symbol
Dimension in mm
Min.
Nom.
Max.
2.7
A1
0.25
0.5
A2
1.9
2.0
2.2
b
0.10
0.15
0.20
9.9
10.00
10.1
9.9
10.00
10.1
2. Dimension b does not include dam bar protrusion/intrusion.

3. JEDEC Outline: MO-108 AA-1.
0.80 TYP.
HD
13
13.2
13.4
HE
13
13.2
13.4
0.73
0.88
0.93
L1
1.6

June 2004
1. Dimensions D and E do not include interlead flash.
0.3 TYP.
NOTES:
0.10
0
Page 16 of 17
TP2804
Headquarters
5 F, No. 10, Prosperity Road 1, Science-Based Industrial Park, Hsinchu, Taiwan 300, R.O.C
Tel.: 886-3-563-2515
Fax: 886-3-564-1728
Taipei Office
2 F, No. 26, Lane 583, Ruiguang Rd., Neihu, Taipei, Taiwan 114, R.O.C.
Tel.: 886-2-2585-6858
Fax: 886-2-2594-1104
Shenzhen Office
Room 802, Tower A, World Trade Plaza, Fuhong Rd., Futian, Shenzhen, China
Tel.: 86-755-8367-9985
Fax: 86-755-8367-9518

June 2004
Page 17 of 17

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TP2804

8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Fully static design of 8-bit CMOS microcontroller

in-system programmable FLASH EPROM for firmware

Running clock up to 40MHz

64K-byte FLASH EPROM

Its instruction set is fully compatible with

the standard 8051.

It contains a 64K-byte FLASH

Low standby current at full supply voltage

bi-directional and bit-addressable I/O ports, an

AUX-RAM, software selectable)

additional 4-bit I/O port, three 16-bit timer/counters

64K-byte program memory address space and

and one serial port.

64K-byte data memory address space

Four 8-bit bi-directional ports

Three 16-bit timer/counters

One full duplex serial port

Data Sheet - Version 1.2

Data Sheet - Version 1.2

with the MOVX instruction.

surrounded by various registers, four general-purpose

are R0 and R1 of the selected register bank and

I/O port, 512-byte RAM, three timer/counters, a serial

Its processor supports 111 different opcodes

The AUX-RAM is disabled

and references, both 64K program address space and

register will enable the access to on-chip

64K data storage space.

The internal data RAM of TP2804 has 512 bytes and

Timers 0, 1, and 2 each consist of two 8-bit data

is divided into two banks: scratchpad 256-byte RAM

2. The TCON and TMOD registers provide control

addressed by different ways:

functions for timers 0 and 1.

The T2CON register

provides control functions for Timer 2. RCAP2H and

RCAP2L are used as auto-reload or capture registers

indirectly as the same as in 8051.

for Timer 2 as it in 8051.

pointers are R0 and R1 of the selected register

The operations of Timer 0 and Timer 1 are the same

as the standard 8051.

timer/counter that is configured and controlled by the

T2CON register. Like timers 0 and 1, Timer 2 can

as the same as in 8051.

operate as either an external event counter or as an

Address pointers are

internal timer, depending on the setting of bit C/T2 in

R0 and R1 of the selected registers bank.

AUX-RAM 00H-FFH is addressed indirectly as

clock speed at capture or auto-reload mode is the

the same way to access external data memory

Data Sheet - Version 1.2

Timer 2 has three operating modes:

capture, auto-reload, and baud rate generator. The

EX3: External interrupt 3 enable if set.

Two additional external interrupts,