Introduction To Verilog Design

Chun-Hung Chou

1
 Outline
• Typical Design Flow
• Design Method
• Lexical Convention
• Data Type
• Data Assignment
• Event Control
• Conditional Description
• Register Description
• Synthesizable Verilog Code
• Simulation Environment 2
 Typical Design Flow

Design Specification

Algorithmic Model
Behavior
Language
RTL Model
Verilog HDL
Gate-Level Model
Structural
Language
Switch-Level Model

Physical Layout

3
 Design Method(1/3)
• Top-Down Design
– design form top module to bottom element
Top
Module

Sub Sub
Module Module

Element Element Element Element

4
 Design Method(2/3)
• Bottom-Up Design
– design from element module to top block
Top
Module

Sub Sub
Module Module

Element Element Element Element

5
 Design Method(3/3)
Module module_name(port name);

port declaration

data type declaration

task & function declaration

module functionality

Endmodule
6
 Lexical Convention(1/10)
• Number Specification
– <size>’<base><value>
• size is the size in bits
• base can be b(binary), o(octal), d(decimal), or h(hexadecimal)
• value is any legal number in the selected base, including x and z
• default value is 32 bits decimal number
– Negative: -<size>’<base><value>
– Example
• 8’b1100_0001_1111 Æ 8’b110000011111
• 16’habc Æ 0000 1010 1011 1100
• 12’b0 Æ 0000 0000 0000
• 6’hx Æ xx xxxx 7
• 2’b1101 Æ 2’b01
 Lexical Convention(2/10)
module arithops();
• Operators integer ans, int;
parameter five = 5;
– Arithmetic Operator reg [3:0]rega, regb;
• + add reg [3:0]num;
initial begin
• - subtract rega = 3;
regb = 4’b1010;
synthesis • * multiply int = -3;
tool
doesn’t • / divide end
initial begin
support !! • % modulus #10 ans = five * int; // ans = -15
#10 ans = (int + 5) / 2; // ans = 1
#10 ans = five / int; // ans = -1
#10 num = rega + regb; // num = 1101
#10 num = rega + 1; // num = 0100
Note: verilog automatically perform #10 num = int; // num = 1101
a 2’s complement when a negative #10 num = regb % rega; // num = 1
value is assigned to an unsigned end
variable such as a reg endmodule 8
 Lexical Convention(3/10)
module bitwise();
• Operators reg [3:0]rega, regb, regc;
reg [3:0]num;
– Bit-Wise Operator initial begin
• ~ not rega = 4’b1001;
regb = 4’b1010;
• & and regc = 4’b11x0
end
• | or initial begin
• ^ xor #10 num = rega & 0; // num = 0000
#10 num = rega & regb; // num = 1000
• ~^ xnor #10 num = rega | regb; // num = 1011
#10 num = regb & regc; // num = 10x0
• ^~ xnor #10 num = regb | regc; // num = 1110
end
endmodule

9
 Lexical Convention(4/10)
module logical();
• Operators parameter five = 5;
reg [3:0]rega, regb, regc;
– Logical Operator reg [3:0]ans;
•! not initial begin
rega = 4’b0011;
• && and regb = 4’b10xz;
regc = 4’b0z0x;
• || or end
initial begin
#10 ans = rega && 0; // ans = 0
Note1: if it contains any ones, its #10 ans = rega || 0; // ans = 1
#10 ans = rega && five; // ans = 1
logical value is true. If an operand
contains all zeros, its logical value #10 ans = regb && rega; // ans = 1
is false #10 ans = regc || 0; // ans = x
end
Note2: if it is unknown(contains endmodule
only zeros and/or unknown bits), its
logical value is ambiguous
10
 Lexical Convention(5/10)
module shift();
• Operators reg [7:0]rega;
reg [9:0]num;
– Shift Operator initial
rega = 8’b0000_1100;
• >> shift right initial begin
• << shift left #10 num = rega << 5; // num = 0110000000
#10 num = rega >> 3;// num = 0000000001
end
endmodule

11
 Lexical Convention(6/10)
module relationals();
• Operators reg [3:0]rega, regb, regc;
reg val;
– Relational Operator initial begin
rega = 4’b0011;
• > greater than regb = 4’b1010;
• < less than regc = 4’b0x10;
end
• >= greater than or equal initial begin
#10 val = regc > rega; //val=x
• <= less than or equal #10 val = regb < rega; //val=0
#10 val = regb >= rega; //val=1
#10 val = regb > regc; //val=x
end
endmodule

12
 Lexical Convention(7/10)
module equalities();
• Operators reg [3:0]rega, regb, regc;
reg val;
– Equality Operator initial begin
rega = 4’b0011;
• == logical equality regb = 4’b1010;
• != logical inequality regc = 4’b0x10;
end
initial begin
#10 val = regc > rega; //val=x
#10 val = regb < rega; //val=0
#10 val = regb >= rega; //val=1
#10 val = regb > regc; //val=x
end
endmodule

13
 Lexical Convention(8/10)
• Operators
– Conditional Operator
• <LHS> = <condition> ? <true_expression> : <false_expression>

a 1 module mux(a, b, sel, out);

input a, b, sel;
out
output out;
b 0 assign out = (sel == 1)? a : b;
endmodule

sel
14
 Lexical Convention(9/10)
• Comment
– single-line comments with //
– multiple-line comments with /* … */

15
 Lexical Convention(10/10)
module concatenation();
• Concatenation reg regc, regd;
reg [3:0]rega, regb;
– allows you to select reg [7:0]new;
reg [3:0]out;
bits form different reg [5:0]val;
initial begin
vectors and join them rega = 8’b0000_0011;
regb = 8’b0000_0100;
into a new vector regc = 1’b1;
–{} regd = 1’b0; end
initial begin
#10 new = {rega, regb};
Note1:
// new = 8’b00110100
rega[3:0] #10 out = {4{regc}}; //out=4’b1111
new[7:0] #10 out = {4{regd}}; //out=4’b0000
#10 val = {regc,{2{regc,regd}},regd};
regb[3:0] // val = 6’b110100
end
endmodule 16
Note2: a[4:0] = {a[3:0], 1’b0}; Æ a = a<<1;
 Data Type(1/6)
• 4-Value Logic System in Verilog

‘0’ Zero

‘1’ One

‘x’ Unknown
NOTE: In real hardware, this
node will most be at either 1 or 0
‘z’ High Impedance
0 17
 Data Type(2/6)
• Three Major Data type classes in Verilog
– Nets
• represent physical connection between devices
– Registers
• represent abstract storage elements
– Parameters
• are run-time constants
– Declaration Syntax
• <data_type> [<MSB>:<LSB>] <list_of_identifier>

18
 Data Type(3/6)
• Nets
– wire is the most common net type
a a1

sel
out

b b1

wire
NOTE: Verilog automatically propagates
a new value onto a wire when the drivers
on the wire change value. This means that
whatever value is on the or gate will be
automatically driven onto the wire out 19
 Data Type(4/6)
• Registers
– reg is the most common register type

a a1
reg_a

sel out
reg_sel

reg_b b1
b

NOTE1: a register holds its value until a new value

is assigned to it
NOTE2: apply values to registers form procedural
blocks
20
 Data Type(5/6)
• Vectors
– the wire and register can be represented as a
vector
• wire [7:0]temp1; Æ 8-bit bus
• reg [7:0]temp2;
• Arrays
– <array_name>[<subscript>]
• integer temp1[7:0]; Æ (8x32)bit
• reg [7:0]temp2[0:1023] Æ Memory(1k,1byte)

NOTE: array is not well for the backend verification

21
Data Type(6/6)
module and1(out, in1, in2);
input in1, in2;
output out;
wire out;
assign out = in1 & in2;
endmodule

module and2(out, in1, in2);

input in1, in2;
output out;
reg out;
always@ (in1 or in2)
out = in1 & in2;
endmodule

22
 Data Assignment(1/3)
• Continuous Assignment
– you can model combinational logic with
continuous assignments, instead of using
gates and interconnect wires
– imply that whatever any change on the RHS
of the assignment occurs, it is evaluated and
assigned to the LHS
– assign [#delay] <wire_name> = <expression>
• wire [3:0]a;
assign a = b + c; //continuous assignment

23
 Data Assignment(2/3)
• Procedural Assignment
– assignment to register data types may occur
within always, initial, task and function. These
expressions are controlled by triggers which
cause the assignment to evaluate
• reg CLK;
always #10 CLK = ~CLK; //procedural assignment
• reg a, b;
always@ (b) //procedural assignment with trigger
a = ~b;
– procedural assignment consists blocking & non-
blocking assignment
24
 Data Assignment(3/3)
• Blocking Assignment Æ Sequential !!
always@ (posedge clk)
begin
b = a;
c = b;
end

• Non-Blocking Assignment Æ Parallel !!

always@ (posedge clk)

begin
b <= a;
c <= b;
end
25
 Event Control
• Combinational Circuit
– @(a): act if signal ‘a’ changes
• always@ (a) c = a + 1;
– @(a or b): act if signal ‘a’ or ‘b’ changes
• always@ (a or b) c = a + b;
• Sequential Circuit
– @(posedge clk): act when rising edge of clk
• always@ (posedge clk) c = a + 1;
– @(negedge clk): act when falling edge of clk
• always@ (negedge clk) c = a + 1;
26
 Conditional Description(1/2)
• if and if-else Statements
if (index > 0) // beginning of outer if
if (rega > regb) //beginning of the 1st inner if
result = rega;
else
result = 0; critical path
else
if (index == 0)
begin
…..
$display(“Note : Index is zero”);
result = regb;
end
else
$display(“Note : Index is negative”);

27
 Conditional Description(2/2)
• case Statement
module compute(result,rega,regb,opcode);
input [7:0]rega, regb;
input [2:0]opcode;
output [7:0]result; critical path
reg [7:0]result;

……….
always@ (rega or regb or opcode)
begin
case (opcode)
3’b000 : result = rega + regb;
3’b001 : result = rega – regb;
3’b100 : result = rega / regb;
default : result = 8’bx;
endcase
end
endmodule

28
 Register Description(1/2)
module MUX(out, sel, clk, reset, in1, in2);
• Informal Description
input sel, clk, reset;
– combinational circuit input [7:0]in1, in2;
output [7:0]out;
and memory reg [7:0]out;
element is
always@ (posedge reset or posedge CLK)
combined in one begin
always bolck if(reset==1’b1) out <= 1’b0;
else if(sel==1’b0) out <= in1;
else out <= in2;
end

endmodule

29
 Register Description(2/2)
module MUX(out, sel, clk, reset, in1, in2);
• Normative Description
input sel, clk, reset;
– separate the input [7:0]in1, in2;
output [7:0]out;
combinational and reg [7:0]out;
sequential parts wire c;
// combinational part
assign c = (sel) ? in1 : in2;
//sequential part
always@ (posedge reset or posedge CLK)
begin
if(reset) out <= 1’b0;
else out <= c;
end

endmodule

30
NOTE: it’s the better way
 Synthesizable Verilog Code(1/2)
• Four data type can be synthesized
– input, output, wire, reg
• 1-D data type is convenient for synthesis
– reg [7:0] a;
– reg [7:0]a[3:0];
• Synthesizable Verilog functions
– assign, always block, called sub-module
• Synthesizable register description
– always@ (posedge clk) always@ (negedge clk)
– always@ (posedge clk or posedge reset) if(reset)..else..
– always@ (negedge clk or posedge reset) if(reset)..else..
– always@ (posedge clk or negedge reset) if(~reset)..else..
– always@ (negedge clk or negedge reset) if(~reset)..else.. 31
 Synthesizable Verilog Code(2/2)
• What kind of Verilog code can’t be synthesized?
always@ (posedge clk or negedge clk)

wire [7:0]a;
reg [3:0]b;
assign a[b] = 0;

always@ (posedge clk)

out = out + 1;
always@ (negedge clk)
out = a;

always@ (posedge clk or posedge reset)

if(reset) out = 0;
else out <= out + in;
32
 Simulation Environment(1/5)

endmodule
33
 Simulation Environment(2/5)
MUX.v TEST_MUX.v
module MUX(OUT,CLK,SEL,RESET,IN1,IN2); `timescale 1 ns/10 ps
`include “MUX.v”
input CLK,SEL,RESET,IN1,IN2; module stimulus;
output OUT;
reg CLK,SEL,RESET,IN1,IN2;
reg OUT;
wire C; Your Design!! wire OUT;
Testbench!!
//connect port by ordering
assign C = (SEL) ? IN1 : IN2; MUX t(OUT,CLK,SEL,RESET,IN1,IN2);

always@ (posedge CLK) //connect port by name

begin MUX t(.OUT(OUT),.CLK(CLK),
if(RESET) OUT <= 1’b0; .SEL(SEL),.RESET(RESET),
else OUT <= C; .IN1(IN1),.IN2(IN2));
end
initial begin
endmodule ……..
end
endmodule 34
 Simulation Environment(3/5)
• Clock Generation
– Initial clk = 0;
always #20 clk = ~clk; 20 20
• Display Simulation Result(Texture Format)
– $display(“%t,clk=%d in=%d out=%d\n”,$time clk,in,out);
– $monitor($time,“clk=%d out=%d\n”, clk,out);
– $time: current time
– $finish: finish the simulation
• Dump a FSDB file for debug(debussy)
– $fsdbDumpfile(“file_name.fsdb”);
– $fsdbDumpvars; NOTE: ‘$’ denotes Verilog system
35
tasks and functions
 Simulation Environment(4/5)

Format Specifiers:
-----------------------------------------------------------------------------------------------------
%h %o %d %b %c %s %v %m %t
hex octal decimal binary ASCII string strength module time
-----------------------------------------------------------------------------------------------------
Escaped Literals:
-----------------------------------------------------------------------------------------------------
\t \n \\ \” \<1-3 digit octal number>
tab new line backslash double quote ASCII representation of above
-----------------------------------------------------------------------------------------------------

36
 Simulation Environment(5/5)
• Complier Directive
– `define <macro_neme> <macro_text>
• `define delay #1
and `delay and1(a1, a, sel);
– `include “<file_name>”
• `include “counter.v”
– `timescale <time_unit> / <time_precision>
• `timescale 1ns / 10ps

37
`timescale 1 ns/10 ps
`include “MUX.v”

module stimulus;
reg CLK,SEL,RESET,IN1,IN2;
wire OUT;

parameter cycle = 5;

MUX m(.OUT(OUT),.CLK(CLK),.SEL(SEL),.RESET(RESET),.IN1(IN1),.IN2(IN2));

always #(cycle) CLK = ~CLK;

initial
begin
$fsdbDumpfile(“MUX.fsdb”);
$fsdbDumpvars;
IN1 = 0; IN2 = 1; SEL = 0; RESET = 0; CLK = 0; //time = 0
#(cycle) IN2 = 0; //time = 5
#(cycle) IN2 = 1; SEL = 1; //time =10
#(cycle*2) IN1 = 1; //time =20
$display(“%d”, OUT);
$finish;
End
38
endmodule