FAN4800A

FAN4800A/C, FAN4801/02/02L
PFC/PWM Controller Combination

Features
Description
Pin-to-Pin Compatible with ML4800 and FAN4800

and CM6800 and CM6800A
PWM Configurable for Current-Mode or

Feed-forward Voltage-Mode Operation
Internally Synchronized Leading-Edge PFC and

Trailing-Edge PWM in one IC
The highly integrated FAN4800A/C and FAN4801/02/2L

are specially designed for power supplies that consist of
boost PFC and PWM. They require very few external
components to achieve versatile protections /
compensation. They are available in 16-pin DIP and
SOP packages.
Low Operating Current
The PWM can be used in either current or voltage

mode. In voltage mode, feed-forward from the PFC
output bus can reduce the secondary output ripple.
Innovative Switching-Charge Multiplier Divider
Compared with older productions, ML4800 and

FAN4800, FAN4800A/C and FAN4801/02/02L have
lower operation current that save power consumption in
external devices. FAN4800A/C and FAN4801/1S/2/2L
have accurate 49.9% maximum duty of PWM that
makes the hold-up time longer. Brownout protection and
PFC soft-start functions are not in ML4800 and
FAN4800.
Average-Current-Mode for Input-Current Shaping

PFC Over-Voltage and Under-Voltage Protections
PFC Feedback Open-Loop Protection
Peak Current Limiting for PFC
Cycle-by-Cycle Current Limiting for PWM
Power-On Sequence Control and Soft-Start
To evaluate FAN4800A/C, FAN4801/02/2L for replacing

existing FAN4800 and ML4800 boards, five things must
be completed before the fine-tuning procedure:
Brownout Protection
Interleaved PFC/PWM Switching
FAN4801/02/02L Improve Efficiency at Light Load
fRTCT=4fPFC=4fPWM for FAN4800A and FAN4801
1.
Change RAC resister from the old value to a higher

resister: between 6M to 8M.
2.
Change RT/CT pin from the existing values to

RT=6.8K and CT=1000pF to have fPFC=64KHz,
fPWM=64KHz.
3.
VRMS pin needs to be 1.224V at VIN=85 VAC for

universal input application from line input from
85VAC to 270 VAC. Both poles for the Vrms of
FAN4801/02/02L dont need to substantially slower
than FAN4800; about 5 to 10 times.
4.
At full load, the average VEA needs to ~4.5V and the

ripple on the VEA needs to be less than 400mV.
5.
Soft-Start pin, the soft-start current has been

reduced to half from the FAN4800 capacitor.
fRTCT=4fPFC=2fPWM for FAN4800C and

FAN4802/02L
Applications
Desktop PC Power Supply

Internet Server Power Supply
LCD TV, Monitor Power Supply
UPS
Battery Charger
DC Motor Power Supply
Monitor Power Supply
Related Resources
Telecom System Power Supply
Distributed Power
2008 Fairchild Semiconductor Corporation

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
AN-8027 - FAN480X PFC+PWM Combination

Controller Application
www.fairchildsemi.com
1
FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination
January 2011
Part Number
Operating
Temperature Range
Package
Packing Method
FAN4800ANY
-40C to +105C
16-Pin Dual In-Line Package (DIP)
Tube
FAN4800CNY
-40C to +105C
Tube
FAN4800AMY
-40C to +105C
16-Pin Small Outline Package (SOP)
Tape & Reel
FAN4800CMY
-40C to +105C
Tape & Reel
FAN4801NY
-40C to +105C
Tube
FAN4802NY
-40C to +105C
16-Pin Dual In-Line Package (DIP))
Tube
FAN4802LNY
-40C to +105C
16-Pin Dual In-Line Package (DIP))
Tube
FAN4801MY
-40C to +105C
Tape & Reel
FAN4802MY
-40C to +105C
Tape & Reel
FAN4802LMY
-40C to +105C
Tape & Reel
Part Number
PFC:PWM Frequency Ratio
Brownout / In
Range In / Out
FAN4800ANY
1:1
1.05V / 1.9V
N.A
FAN4800AMY
1:1
1.05V / 1.9V
N.A
FAN4800CNY
1:2
1.05V / 1.9V
N.A
FAN4800CMY
1:2
1.05V / 1.9V
N.A
FAN4801NY
1:1
1.05V / 1.9V
1.95V / 2.45V
FAN4802NY
1:2
1.05V / 1.9V
1.95V / 2.45V
FAN4802LNY
1:2
0.9V / 1.65V
1.95V / 2.45V
FAN4801MY
1:1
1.05V / 1.9V
1.95V / 2.45V
FAN4802MY
1:2
1.05V / 1.9V
1.95V / 2.45V
FAN4802LMY
1:2
0.9V / 1.65V
1.95V / 2.45V

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
Ordering Information
2
IEA
VEA
IAC
FBPFC
ISENSE
VREF
VDD
VRMS
VDD
SS
OPFC
FBPWM
OPWM
RT/CT
GND
RAMP
ILIMIT
VREF
Application Diagram
FAN4800A/C
FAN4801/02/02L
Secondary
Figure 1.

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
Typical Application Current Mode
3
IEA
VEA
IAC
FBPFC
ISENSE
VREF
VDD
VRMS
VDD
SS
OPFC
FBPWM
OPWM
RT/CT
GND
RAMP
ILIMIT
Application Diagram
VREF
FAN4800A/C
FAN4801/02/02L
VREF
Secondary
Figure 2.

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
Typical Application Voltage Mode
4
Figure 3. FAN4800A/C Function Block Diagram
Block Diagram
Figure 4. FAN4801/02/02L Function Block Diagram

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
5
F Fairchild Logo
Z Plant Code
X 1-Digit Year Code
Y 2-Digit Week Code
TT 2-Digit Die-Run Code
T Package Type (M:SOP)
P Y: Green Package
M Manufacture Flow Code
Figure 5. DIP Top Mark
F Fairchild Logo
Z Plant Code
X 1-Digit Year Code
Y 1-Digit Week Code
TT 2-Digit Die-Run Code
T Package Type (M:SOP)
P Y: Green Package
M Manufacture Flow Code
Marking Information
Figure 6. SOP Top Mark

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
6
Figure 7. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
IEA
Output of PFC Current Amplifier. The signal from this pin is compared with an internal
sawtooth to determine the pulse width for PFC gate drive.
IAC
Input AC Current. For normal operation, this input provides current reference for the multiplier.
The suggested maximum IAC is 100A.
ISENSE
VRMS
SS
FBPWM
RT/CT
Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
RAMP
PWM RAMP Input. In current mode, this pin functions as the current sense input; when in
voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp).
ILIMIT
Peak Current Limit Setting for PWM. The peak current limits setting for PWM.
10
GND
11
OPWM
PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally
clamped under 15V to protect the MOSFET.
12
OPFC
PFC Gate Drive. The totem pole output drive for PWM MOSFET. This pin is internally clamped
under 15V to protect the MOSFET.
13
VDD
Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and
9.3V, respectively. The operating current is lower than 10mA.
14
VREF
Reference Voltage. Buffered output for the internal 7.5V reference.
15
FBPFC
16
VEA
PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of
multiplier and PFC ILIMIT comparator.
Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier.
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10A constant
current source. The voltage on FBPWM is clamped by SS during startup. In the event of a
protection condition occurring and/or PWM disabled, the SS pin is quickly discharged.
Pin Configuration
PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.
Ground.
Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input
of PFC error amplifier. This pin is connected to the PFC output through a divider network.
Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.
A compensation network is connected between this pin and ground.

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
7
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
VDD
DC Supply Voltage
VH
SS, FBPWM, RAMP, OPWM, OPFC
-0.3
IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA
-0.3
VL
VVREF
VIEA
Unit
30
30.0
7.0
7.5
VVREF+0.3
-5.0
VREF
IEA
Max.
VN
ISENSE
0.7
IAC
Input AC Current
mA
IREF
VREF Output Current
mA
0.5
IPFC-OUT
Peak PFC OUT Current, Source or Sink
IPWM-OUT
Peak PWM OUT Current, Source or Sink
0.5
PD
Power Dissipation TA < 50C
800
mW
JA
Thermal Resistance (Junction-to-Air)
80.80
C/W
TJ
TSTG
TL
ESD
DIP
104.10
C/W
Operating Junction Temperature
SOP
-40
+125
Storage Temperature Range
-55
+150
+260
4.5
kV
1000
Lead Temperature (Soldering)

Human Body Model,
JESD22-A114
Electrostatic Discharge Capability
Charged Device Model,

JESD22-C101
Absolute Maximum Ratings
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
Min.
Max.
Unit
-40
+105
8
VDD=15V, TA=25C, RT=6.8k, CT=1000pF unless noted operating specifications.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
30
80
2.0
2.6
5.0
mA
11
12
1.9
VDD Section
IDD ST
Startup Current
VDD=VTH-ON-0.1V; OPFC OPWM Open
IDD-OP
Operating Current
VDD=13V; OPFC OPWM Open
VTH-ON
Turn-On Threshold
Voltage
10
Hysteresis
1.5
VDD OVP
27
VTH
VDD-OVP
VDD-OVP
VDD OVP Hysteresis
28
29
V
V
Oscillator
fOSC-RT/CT
RT/CT Frequency
RT=6.8k, CT=1000pF
PFC & PWM Frequency
240
256
268
60
64
67
120
128
134
kHz
fOSC
FAN4800C,FAN4802/02L
PWM Frequency
RT=6.8k, CT=1000pF
fDV
Voltage Stability
11V VDD 22V
fDT
Temperature Stability
-40C ~ +105C
fTV
Total Variation
(PFC and PWM)(3)
Line, Temperature
70
kHz
fRV
Ramp Voltage(3)
Valley to Peak
Discharge Current
VRAMP=0V, VRT/CT=2.5V
IDischarge
58
2.8
kHz
6.5
15
mA
50
75
kHz
600
800
ns
7.5
7.6
30
50
mV
25
mV
0.5
fRANGE
Frequency Range(3)
tPFCD
PFC Dead Time
RT=6.8k, CT=1000pF
400
VVREF
Reference Voltage
IREF=0mA, CREF=0.1F
7.4
VVREF1
Load Regulation of
Reference Voltage
CREF=0.1F, IREF=0mA to 3.5mA

VVDD=14V, Rise/Fall Time > 20s
VVREF2
Line Regulation of
Reference Voltage
CREF=0.1F, VVDD=11V to 22V
Temperature Stability(3)
-40C ~ +105C
VREF
VVREF-DT
VVREF-TV
(3)
Total Variation
(3)
0.4
Line, Load, Temperature
7.35
7.65
25
mV
VVREF-LS
Long-Term Stability
TJ=125C, 0 ~ 1000HRs
IREF-MAX.
Maximum Current
VVREF > 7.35V
IOS
Output Short Circuit(3)
Electrical Characteristics
mA
25
mA
PFC OVP Comparator

VPFC-OVP
VPFC-OVP
Over-Voltage Protection
2.70
2.75
2.80
PFC OVP Hysteresis
200
250
300
mV
0.2
0.3
0.4
Voltage Level on FBPFC

to Enable OPWM During
Startup
2.3
2.4
2.5
Hysteresis
1.15
1.25
1.35
Low-Power Detect Comparator

VEAOFF
VEA Voltage OFF OPFC
VIN OK Comparator
VRD-FBPFC
VRD-FBPFC

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
9
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
2.55
90
mho
Voltage Error Amplifier

FBPFC
Input Voltage Range(3)
Vref
Reference Voltage
AV
(3)
0
at T=25C
2.45
35
42
Transconductance
VNONINV=VINV, VVEA=3.75V at T=25C
50
70
IFBPFC-L
Maximum Source Current
VFBPFC=2V, VVEA=1.5V
40
50
IFBPFC-H
Maximum Sink Current
VFBPFC=3V, VVEA=6V
Gmv
IBS
Open-Loop Gain
2.50
-50
Input Bias Current
-1
VVEA-H
Output High Voltage on

VVEA
5.8
VVEA-L
Output Low Voltage on

VVEA
dB
A
-40
6
0.1
V
0.4
0.7
100
mho
10
mV
7.4
8.0
0.1
0.4
-35
Current Error Amplifier

VISENSE
GmI
Input Voltage Range

(ISENSE Pin)(3)
-1.5
Transconductance
VNONINV=VINV, VIEA=3.75V
78
VOFFSET
Input Offset Voltage
VVEA=0V, IAC Open
-10
VIEA-H
Output High Voltage
VIEA-L
Output Low Voltage
6.8
IL
Source Current
VISENSE=-0.6V, VIEA=1.5V
IH
Sink Current
VISENSE=+0.6V, VIEA=4.0V
AI
Open-Loop Gain(3)
35
88
50
-50
40
50
dB
Electrical Characteristics (Continued)
Tri-Fault Detect
tFBPFC_OPEN
Time to FBPFC Open(3)
VPFC-UVP
PFC Feedback UnderVoltage Protection
VFBPFC=VPFC-UVP to FBPFC OPEN,

470pF from FBPFC to GND
0.4
ms
0.5
0.6
100
Gain Modulator
IAC
GAIN
BW
Vo(gm)
Input for AC Current(3)
GAIN Modulator(4)
Multiplier Linear Range

IAC=17.67A, VRMS=1.080V
VFBPFC=2.25V, at T=25C
7.50
9.00
10.50
IAC=20A, VRMS=1.224V VFBPFC=2.25V,

at T=25C
6.30
7.00
7.70
IAC=25.69A, VRMS=1.585V
3.80
4.20
4.60
IAC=51.62A, VRMS=3.169V
0.95
1.05
1.16
IAC=62.23A, VRMS=3.803V
0.66
0.73
0.80
Bandwidth(3)
IAC=40A
Output Voltage=5.7k
(ISENSE-IOFFSET)(3)
IAC=20A, VRMS=1.224V VFBPFC=2.25V,

at T=25C

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
2
0.74
0.82
kHz
0.90
10
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
-1.25
-1.15
-1.05
PFC ILIMIT Comparator

VPFC-ILIMIT
Peak Current Limit

Threshold Voltage,
Cycle-by-Cycle Limit
IAC=17.67A, VRMS=1.08V
200
Gate Output Clamping

Voltage
VDD=22V
13
VGATE-L
Gate Low Voltage
VDD=15V; IO=100mA
VGATE-H
Gate High Voltage
VDD=13V; IO=100mA
tr
Gate Rising Time
VDD=15V; CL=4.7nF; O/P=2V to 9V
40
70
120
ns
tf
110
ns
Vpk
PFC ILIMIT-Gain Modulator

Output
V
mV
PFC Output Driver

VGATE-CLAMP
15
17
1.5
V
V
Gate Falling Time
VDD=15V; CL=4.7nF; O/P=9V to 2V
40
60
DPFC-MAX
Maximum Duty Cycle
VIEA<1.2V
94
97
DPFC-MIN
Minimum Duty Cycle
VIEA>4.5V
%
0
Brownout
VRMS-UVL
VRMS Threshold Low
VRMS-UVH
VRMS Threshold High
VRMS-UVP
tUVP
Hysteresis
FAN4800A/C, FAN4801/02
1.00
1.05
1.10
FAN4802L
0.85
0.90
0.95
FAN4800A/C, FAN4801/02
1.85
1.90
1.95
FAN4802L
1.60
1.65
1.70
FAN4800A/C, FAN4801/02
750
850
950
mV
FAN4802L
650
750
850
mV
340
410
480
ms
9.5
10.0
10.5
Under-Voltage Protection
Delay Time
Soft-Start
VSS-MAX
Maximum Voltage
ISS
Soft-Start Current
VDD=15V
10
V
A
PWM ILIMIT Comparator

VPWM-ILIMIT
tPD
tPWM-Bnk
Threshold Voltage
0.95
Delay to Output
1.00
1.05
250
Leading-Edge Blanking
Time
V
ns
170
250
350
ns
Range (FAN4801/02/02L)
VRMS-L
RMS AC Voltage Low
When VRMS=1.95V at132VRMS
1.90
1.95
2.00
VRMS-H
RMS AC Voltage High
When VRMS=2.45V at150VRMS
2.40
2.45
2.50
VEA-L
VEA Low
When VVEA=1.95V at 30% Loading,

When VVEA=2.80V at 60% Loading
1.90
1.95
2.00
VEA-H
VEA High
When VVEA=2.45V at 40% Loading,

When VVEA=3.35V at 70% Loading
2.40
2.45
2.50
Two-Level Current
FBPFC Two-Level Current
18
20
22
Itc

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
11
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
13
15
17
1.5
PWM Output Driver

VGATE-CLAMP
Gate Output Clamping Voltage VDD=22V
VGATE-L
Gate Low Voltage
VDD=15V; IO=100mA
VGATE-H
Gate High Voltage
VDD=13V; IO=100mA
tr
Gate Rising Time
VDD=15V; CL=4.7nF
30
60
120
ns
tf
Gate Falling Time
VDD=15V; CL=4.7nF
30
50
110
ns
Maximum Duty Cycle
49.0
49.5
50.0
PWM Comparator Level Shift
1.3
1.5
1.8
DPWM-MAX
VPWM-LS
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
4. Gain=K 5.3 (VRMS2)-1; K=(ISENSE IOFFSET) [IAC (VEA 0.7V)]-1; VEA(MAX.)=5.6V.

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
12
20.0
2.96
18.0
2.94
16.0
2.92
2.90
IDD-OP(uA)
IDD-ST(uA)
14.0
12.0
10.0
8.0
6.0
2.88
2.86
2.84
4.0
2.82
2.0
2.80
0.0
2.78
-40 -25 -10
20
35 50
65 80 95 110 125
-40 -25 -10
Figure 8. IDD-ST vs. Temperature

2.0
11.3
1.9
VTH(V)
VTH-ON (V)
95 110 125
1.8
11.2
11.1
11.0
1.7
1.6
1.5
10.9
1.4
1.3
10.8
-40 -25 -10
20
35
50
65
80
95
-40 -25 -10
110 125
28.04
65.0
28.02
64.9
28.00
FOSC-FAN4801/1S(kHz)
27.96
27.94
27.92
27.90
35
50
65
80
95 110 125
64.7
64.6
64.5
64.4
64.3
27.88
27.86
5
20
35
50
65
80
95
64.2
-40
110 125
Figure 12. VDD-OVP vs. Temperature
-25
-10
20
35
50
65
80
95
110 125
Figure 13. fOSC-FAN4801/1S vs. Temperature

655
129.8
650
129.6
645
129.4
640
tPFCD(ns)
130.0
129.2
129.0
635
630
128.8
625
128.6
620
128.4
-40 -25 -10
20
64.8
27.98
-40 -25 -10
Figure 11. VTH vs. Temperature
Figure 10. VTH-ON vs. Temperature
VDD-OVP(V)
20 35 50 65 80
Figure 9. IDD-OP vs. Temperature
11.4
FOSC-FAN4802/2L(kHz)
Typical Characteristics
615
5
20 35
50 65
80 95 110 125
-40 -25 -10
Figure 14. fOSC-FAN4802/2L vs. Temperature

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
20
35
50
65
80
95 110 125
Figure 15. tPFCD vs. Temperature

13
7.520
7.515
7.510
VVREF1(mV)
VVREF(V)
7.505
7.500
7.495
7.490
4
3
2
7.485
1
7.480
7.475
-40 -25 -10
20 35 50 65 80
-40 -25 -10
95 110 125
0.18
50
65
80
95 110 125
21.0
0.16
0.14
20.5
IREF-MAX.(mA)
VVREF2(mV)
35
21.5
0.20
0.12
0.10
0.08
0.06
20.0
19.5
19.0
0.04
0.02
18.5
0.00
-0.02
18.0
-40 -25 -10
-40 -25 -10
20 35 50 65 80 95 110 125
Figure 18. VVREF2 vs. Temperature

2.742
252.2
2.740
252.0
2.738
2.736
2.734
2.732
50 65 80 95 110 125
251.8
251.6
251.4
251.2
250.8
5
20 35 50 65 80 95 110 125
-40 -25 -10
20 35 50 65 80 95 110 125
Figure 21. VPFC-OVP vs. Temperature
Figure 20. VPFC-OVP vs. Temperature
1.275
2.398
1.270
VRD-FBPFC(V)
2.400
2.396
2.394
2.392
2.390
1.265
1.260
1.255
1.250
1.245
2.388
-40 -25 -10
20 35
251.0
2.730
-40 -25 -10
Figure 19. IREF-MAX. vs. Temperature
VPFC-OVP(mV)
VPFC-OVP(V)
20
Figure 17. VVREF1 vs. Temperature
Figure 16. VVREF vs. Temperature
VRD-FBPFC(V)
1.240
5
20 35 50 65 80 95 110 125
-40 -25 -10
20 35 50 65 80 95 110 125
Figure 23. VRD-FBPFC vs. Temperature
Figure 22. VRD-FBPFC vs. Temperature

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
14
74
2.502
2.500
73
Gmv(umho)
Vref(V)
2.498
2.496
2.494
73
72
2.492
72
2.490
2.488
71
-40 -25 -10
20 35
50 65 80 95 110 125
-40
Figure 24. Vref vs. Temperature

4.5
94
4.0
92
20
35
50
65
80
95
110 125
90
3.0
GmI(umho)
VOFFSET(mV)
-10
Figure 25. GmV vs. Temperature
3.5
2.5
2.0
1.5
88
86
84
82
1.0
80
0.5
0.0
78
-40 -25 -10
20
35
50
65
80
-40 -25 -10
95 110 125
Figure 26. VOFFSET vs. Temperature
20
35
50
65
80
95 110 125
Figure 27. GmI vs. Temperature
7.10
6.1
7.05
6.0
7.00
5.9
Rmul(k)
6.95
GAIN2
-25
6.90
6.85
5.8
5.7
5.6
6.80
5.5
6.75
6.70
5.4
-40 -25 -10
20
35
50
65
80
95 110 125
-40 -25 -10
Figure 28. GAIN2 vs. Temperature
20
35
50
65
80
95 110 125
Figure 29. Rmul vs. Temperature
-1.1775
295
-1.1780
290
-1.1785
285
-1.1790
Vpk(mV)
VPFC-ILIMIT(V)
280
-1.1795
-1.1800
-1.1805
-1.1810
275
270
265
-1.1815
260
-1.1820
255
250
-1.1825
-40 -25 -10
20
-40 -25 -10
35 50 65 80 95 110 125
20
35
50
65
80
95 110 125
Figure 31. Vpk vs. Temperature
Figure 30. VPFC-ILIMIT vs. Temperature

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
15
1.010
10.1
1.009
10.0
9.9
9.8
1.007
ISS(uA)
VPWM-ILIMIT (V)
1.008
1.006
1.005
9.7
9.6
9.5
9.4
1.004
9.3
1.003
9.2
1.002
9.1
-40 -25 -10
-40 -25 -10
20 35 50 65 80 95 110 125
Figure 32. VPWM-ILIMIT vs. Temperature

1.048
867.5
1.047
867.0
1.046
866.5
VRMS-UVP(mV)
VRMS-UVP(V)
1.044
1.043
1.042
1.041
50 65
80 95 110 125
866.0
865.5
865.0
864.5
864.0
863.5
1.040
863.0
1.039
862.5
1.038
862.0
-40 -25 -10
-40 -25 -10
20 35 50 65 80 95 110 125
20 35 50 65 80 95 110 125
Figure 35. VRMS-UVP vs. Temperature
Figure 34. VRMS-UVP vs. Temperature

1.940
2.446
1.939
2.445
2.444
1.938
2.443
1.937
VRMS-H(V)
VRMS-L(V)
20 35
Figure 33. ISS vs. Temperature
1.045
1.936
1.935
1.934
2.442
2.441
2.440
2.439
1.933
2.438
1.932
2.437
2.436
1.931
-40 -25 -10
2.435
20 35 50 65 80 95 110 125
-40 -25 -10
Figure 36. VRMS-L vs. Temperature
20
35 50 65 80 95 110 125
Figure 37. VRMS-H vs. Temperature
1.942
2.436
1.940
2.434
1.938
2.432
VEA-H(V)
VEA-L(V)
1.936
1.934
2.430
2.428
1.932
2.426
1.930
2.424
1.928
-40 -25 -10
-40 -25 -10
20 35 50 65 80 95
20 35 50 65 80 95 110 125
Figure 38. VEA-L vs. Temperature

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
110
125
Figure 39. VEA-H vs. Temperature

16
14.4
14.6
14.3
14.5
14.2
VGATE-CLAMP-PWM(V)
VGATE-CLAMP-PFC(V)
14.7
14.4
14.3
14.2
14.1
14.1
14.0
13.9
13.8
14.0
13.7
13.9
-40 -25 -10
20
35 50
65
80
13.6
95 110 125
-40 -25 -10
Figure 40. VGATE-CLAMP-PFC vs. Temperature
20
35
50
65
80
95 110 125
Figure 41. VGATE-CLAMP-PWM vs. Temperature
96.06
49.80
96.04
49.75
DPWM-MAX(%)
DPFC-MAX(%)
96.02
96.00
95.98
95.96
95.94
49.70
49.65
49.60
49.55
95.92
95.90
49.50
95.88
-40 -25 -10
-40 -25 -10
20
35 50
20 35 50 65 80 95
65 80 95 110 125
Figure 42. DPFC-MAX vs. Temperature
110
125
Figure 43. DPWM-MAX vs. Temperature

1.460
21.0
20.8
1.455
VPWM-LS(V)
20.6
Itc(uA)
20.4
20.2
20.0
1.450
1.445
1.440
19.8
1.435
19.6
19.4
1.430
-40 -25 -10
20 35 50 65 80 95 110 125
-40 -25 -10
Figure 44. Itc vs. Temperature

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
20
35 50
65 80 95 110 125
Figure 45. VPWM-LS vs. Temperature
17
The FAN4800A/C and FAN4801/02/02L consist of an

average current controlled, continuous boost Power
Factor Correction (PFC) front-end and a synchronized
Pulse Width Modulator (PWM) back-end. The PWM can
be used in current or voltage mode. In voltage mode,
feed forward from the PFC output bus can be used to
improve the line regulation of PWM. In either mode, the
PWM stage uses conventional trailing-edge, duty-cycle
modulation. This propriety leading/trailing edge
modulation results in a higher usable PFC error
amplifier bandwidth and can significantly reduce the
size of the PFC DC bus capacitor.
IGAINMOD
VRMS 2
(1)
Note that the output current of the gain modulator is

limited around 159A and the maximum output voltage
of the gain modulator is limited to 159A x 5.7K=0.906V.
This 0.906V also determines the maximum input power.
However, IGAINMOD cannot be measured directly from
ISENSE. ISENSE=IGAINMOD IOFFSET and IOFFSET can only
be measured when VEA is less than 0.5V and IGAINMOD
is 0A. Typical IOFFSET is around 31A ~ 48A.
The synchronization of the PWM with the PFC simplifies

the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor).
The PWM section of the FAN4800A, FAN4801/1S
operates at the same frequency as the PFC; and
FAN4800C, FAN4802/2L operates at double with PFC.
Selecting RAC for IAC Pin

The IAC pin is the input of the gain modulator and also
a current mirror input and requires current input.
Selecting a proper resistor RAC provides a good sine
wave current derived from the line voltage and helps
program the maximum input power and minimum input
line voltage. RAC=VIN peak x 56K. For example, if the
minimum line voltage is 75VAC, the RAC=75 x 1.414 x
56K=6M.
In addition to power factor correction, a number of

protection features are built into this series. They
include soft-start, PFC over-voltage protection, peak
current limiting, brownout protection, duty cycle limiting,
and under-voltage lockout (UVLO).
Current Amplifier Error, IEA
Gain Modulator
The current error amplifiers output controls the PFC

duty cycle to keep the average current through the
boost inductor a linear function of the line voltage. At
the inverting input to the current error amplifier, the
output current of the gain modulator is summed with a
current, which results in a negative voltage being
impressed upon the ISENSE pin.
The gain modulator is the heart of the PFC, as the

circuit block controls the response of the current loop to
line voltage waveform and frequency, RMS line voltage,
and PFC output voltages. There are three inputs to the
gain modulator:
1. A current representing the instantaneous input
voltage (amplitude and wave shape) to the PFC. The
rectified AC input sine wave is converted to a
proportional current via a resistor and is fed into the
gain modulator at IAC. Sampling current in this way
minimizes ground noise, required in high-power,
switching-power conversion environments. The gain
modulator responds linearly to this current.
The negative voltage on ISENSE represents the sum of

all currents flowing in the PFC circuit and is typically
derived from a current sense resistor in series with the
negative terminal of the input bridge rectifier.
The inverting input of the current error amplifier is a
virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC,
an increase in positive current from the gain modulator
causes the output stage to increase its duty cycle until
the voltage on ISENSE is adequately negative to cancel
this increased current. Similarly, if the gain modulators
output decreases, the output duty cycle decreases to
achieve a less negative voltage on the ISENSE pin.
2. A voltage proportional to the long-term RMS AC line

voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at VRMS. The output of the gain
modulator is inversely proportional to VRMS (except
at unusually low values of VRMS, where special gain
contouring takes over to limit power dissipation of the
circuit components under brownout conditions).
PFC Cycle-By-Cycle Current Limiter
3. The output of the voltage error amplifier, VEA. The

gain modulator responds linearly to variations in this
voltage.
As well as being a part of the current feedback loop, the

ISENSE pin is a direct input to the cycle-by-cycle
current limiter for the PFC section. If the input voltage at
this pin is less than -1.15V, the output of the PFC is
disabled until the protection flip-flop is reset by the clock
pulse at the start of the next PFC power cycle.
The output of the gain modulator is a current signal, in

the form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual ground
(negative) input of the current error amplifier. In this way,
the gain modulator forms the reference for the current
error loop and ultimately controls the instantaneous
current draw of the PFC from the power line. The
general form of the output of the gain modulator is:
FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
IAC (VEA 0.7)
Functional Description
18
Error Amplifier Compensation
To improve power supply reliability, reduce system

component count, and simplify compliance to UL 1950
safety standards, the FAN4800A/C, FAN4801/02/02L
includes TriFault Detect. This feature monitors FBPFC
for certain PFC fault conditions.
The PWM loading of the PFC can be modeled as a

negative resistor because an increase in the input
voltage to the PWM causes a decrease in the input
current.
This
response
dictates
the
proper
compensation of the two transconductance error
amplifiers. Figure 46 shows the types of compensation
networks most commonly used for the voltage and
current error amplifiers, along with their respective
return points. The current-loop compensation is
returned to VREF to produce a soft-start characteristic
on the PFC: As the reference voltage increases from
0V, it creates a differentiated voltage on IEA, which
prevents the PFC from immediately demanding a full
duty cycle on its boost converter. Complete design is
referred in application note AN-6078SC.
In a feedback path failure, the output of the PFC could

exceed safe operating limits. With such a failure,
FBPFC exceeds its normal operating area. Should
FBPFC go too LOW, too HIGH, or OPEN, TriFault
Detect senses the error and terminates the PFC output
drive.
TriFault detect is an entirely internal circuit. It requires
no external components to serve its protective function.
PFC Over-Voltage Protection
There is an RC filter between RSENSE and ISENSE pin.

There are two reasons to add a filter at the ISENSE pin:
In the FAN4800A/C, FAN4801/02/02L, the PFC OVP

comparator serves to protect the power circuit from
being subjected to excessive voltages if the load
changes suddenly. A resistor divider from the highvoltage DC output of the PFC is fed to FBPFC. When
the voltage on FBPFC exceeds 2.75V, the PFC output
driver is shut down. The PWM section continues to
operate. The OVP comparator has 250mV of hysteresis
and the PFC does not restart until the voltage at FBPFC
drops below 2.50V. VDD OVP can also serve as a
redundant PFC OVP protection. VDD OVP threshold is
28V with 1V hysteresis.
1. Protection: During startup or inrush current

conditions, there is a large voltage across RSENSE,
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE filter to attenuate
the energy.
2. To reduce L, the boost inductor: The ISENSE filter
also can reduce the boost inductor value since the
ISENSE filter behaves like an integrator before the
ISENSE pin, which is the input of the current error
amplifier, IEA.
The ISENSE filter is an RC filter. The resistor value of
the ISENSE filter is between 100 and 50 because
IOFFSET x RFILTER can generate a negative offset voltage
of IEA. Selecting an RFILTER equal to 50 keeps the
offset of the IEA less than 3mV. Design the pole of
ISENSE filter at fPFC/6, one sixth of the PFC switching
frequency, so the boost inductor can be reduced six
times without disturbing the stability. The capacitor of
the ISENSE filter, CFILTER, is approximately 100nF.
Selecting PFC RSENSE

RSENSE is the sensing resistor of the PFC boost
converter. During the steady state, line input current x
RSENSE equals IGAINMOD x 5.7K.
At full load, the average VEA needs to around 4.5V and
ripple on the VEA needs to be less than 400mV.
Choose the resistance of the sensing resistor:
Rsense
4.5 0.7 5.7K IAC Gain VIN

2 5.6 0.7 Line input Power
TriFault Detect
(2)
where 5.6 is VEA maximum output.
PFC Soft-Start
PFC startup is controlled by VEA level. Before FBPFC
voltage reaches 2.4V, the VEA level is around 2.8V. At
90VAC, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage.
The FAN4800A/C, FAN4801/02 disables PFC as lower
AC input such that the VRMS is less than 1.05V. The
brownout voltage of FAN4802L is lower than
FAN4801/1S/2, such that the VRMS is less than 0.9V.
Figure 46. Compensation Network Connection for the
Voltage and Current Error Amplifiers

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
19
Pulse Width Modulator (PWM)
To improve the efficiency, the system can reduce PFC

switching loss at low line and light load by reducing the
PFC output voltage. The two-level PFC output of
FAN4801/02/02L can be programmable.
The operation of the PWM section is straightforward,

but there are several points that should be noted.
Foremost among these is the inherent synchronization
of PWM with the PFC section of the device, from which
it also derives its basic timing. The PWM is capable of
current-mode or voltage-mode operation. In currentmode applications, the PWM ramp (RAMP) is usually
derived directly from a current sensing resistor or
current transformer in the primary of the output stage. It
is thereby representative of the current flowing in the
converters output stage. ILIMIT, which provides cycle-bycycle current limiting, is typically connected to RAMP in
such applications. For voltage-mode operation and
certain specialized applications, RAMP can be
connected to a separate RC timing network to generate
a voltage ramp against which FBPWM is compared.
Under these conditions, the use of voltage feed-forward
from the PFC bus can assist in line regulation accuracy
and response. As in current-mode operation, the ILIMIT
input is used for output stage over-current protection.
No voltage error amplifier is included in the PWM stage,
as this function is generally performed on the output
side of the PWMs isolation boundary. To facilitate the
design of opto-coupler feedback circuitry, an offset has
been built into the PWMs RAMP input that allows
FBPWM to command a 0% duty cycle for input voltages
below typical 1.5V.
As Figure 47 shows, FAN4801/02/02L detect VEA pin

and VRMS pin to determine the system operates low
line and light load or not. At the second-level PFC, there
is a current of 20A through RF2 from FBPFC pin. So
the second-level PFC output voltage can be calculated
as.
RF 1 RF 2
(2.5V 20uA RF 2 )
(3)
RF 2
For example, if the second-level PFC output voltage is
expected as 300V and normal voltage is 387V,
according to the equation, RF2 is 28k RF1 is 4.3M.
Output
The programmable range of second level PFC output

voltage is 340V ~ 300V.
PWM Cycle-By-Cycle Current Limiter

The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output flip-flop is
reset by the clock pulse at the start of the next PWM
power cycle. When the ILIMIT triggers the cycle-by-cycle
bi-cycle current, it limits the PWM duty cycle mode and
the power dissipation is reduced during the dead-short
condition.
Figure 47. Two-Level PFC Scheme
Oscillator (RT/CT)
The oscillator frequency is determined by the values of
RT and CT, which determine the ramp and off-time of
the oscillator output clock:
VIN OK Comparator
1
fRT / CT
(4)
tRT / CT tDEAD
The dead time of the oscillator is derived from the
following equation:
The VIN OK comparator monitors the DC output of the

PFC and inhibits the PWM if the voltage on FBPFC is
less than its nominal 2.4V. Once the voltage reaches
2.4V, which corresponds to the PFC output capacitor
being charged to its rated boost voltage, the soft-start
begins.
VREF 1
tRT / CT CT RT ln
VREF 3.8
at VREF=7.5V and tRT/CT=CT x RT x 0.56.
PWM Soft-Start (SS)
(5)
PWM startup is controlled by selection of the external

capacitor at soft-start. A current source of 10A
supplies the charging current for the capacitor and
startup of the PWM begins at 1.5V.
The dead time of the oscillator is determined using:

2.8V
CT 360 CT
(6)
7.78mA
The dead time is so small (tRT/CT>>tDEAD) that the
operating frequency can typically be approximated by:
tDEAD
fRT / CT
1
tRT / CT

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
Two-Level PFC Function
(7)
20
Leading/Trailing Modulation
When the PWM section is used in current mode, RAMP

is generally used as the sampling point for a voltage,
representing the current in the primary of the PWMs
output transformer. The voltage is derived either from a
current sensing resistor or a current transformer. In
voltage mode, RAMP is the input for a ramp voltage
generated by a second set of timing components (RRAMP,
CRAMP) that have a minimum value of 0V and a peak
value of approximately 6V. In voltage mode, feed
forward from the PFC output bus is an excellent way to
derive the timing ramp for the PWM stage.
Conventional PWM techniques employ trailing-edge

modulation, in which the switch turns on right after the
trailing edge of the system clock. The error amplifier
output is then compared with the modulating ramp up.
The effective duty cycle of the trailing edge modulation
is determined during the on-time of the switch.
In the case of leading-edge modulation, the switch is
turned off exactly at the leading edge of the system
clock. When the modulating ramp reaches the level of
the error amplifier output voltage, the switch is turned
on. The effective duty-cycle of the leading-edge
modulation is determined during off-time of the switch.
Generating VDD
After turning on the FAN4800A/C, FAN4801/02/02L at
11V, the operating voltage can vary from 9.3V to 28V.
The threshold voltage of the VDD OVP comparator is
28V and its hysteresis is 1V. When VDD reaches 28V,
OPFC is LOW, and the PWM section is not disturbed.
There are two ways to generate VDD: use auxiliary
power supply around 15V or use bootstrap winding to
self-bias the FAN4800A/C, FAN4801/02/02L system.
The bootstrap winding can be taped from the PFC boost
choke or the transformer of the DC-to-DC stage.

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
PWM Control (RAMP)
21
19.68
18.66
16
6.60
6.09
(0.40)
TOP VIEW
0.38 MIN
5.33 MAX
8.13
7.62
3.42
3.17
3.81
2.92
2.54
0.35
0.20
0.58 A
0.35
1.78
1.14
15
0
Physical Dimensions
8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 48. 16-Pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
22
Physical Dimensions (Continued)
Figure 49. 16-Pin Small Outline Package (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
23

FAN4800A/C, FAN4801/02/02L Rev. 1.0.3
24

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FAN4800A/C, FAN4801/02/02L

PFC/PWM Controller Combination

Pin-to-Pin Compatible with ML4800 and FAN4800

PWM Configurable for Current-Mode or

Internally Synchronized Leading-Edge PFC and

The highly integrated FAN4800A/C and FAN4801/02/2L

Low Operating Current

The PWM can be used in either current or voltage

Innovative Switching-Charge Multiplier Divider

Compared with older productions, ML4800 and

Average-Current-Mode for Input-Current Shaping

To evaluate FAN4800A/C, FAN4801/02/2L for replacing

Change RAC resister from the old value to a higher

Change RT/CT pin from the existing values to

VRMS pin needs to be 1.224V at VIN=85 VAC for

At full load, the average VEA needs to ~4.5V and the

Soft-Start pin, the soft-start current has been

fRTCT=4fPFC=2fPWM for FAN4800C and

Desktop PC Power Supply

Telecom System Power Supply

2008 Fairchild Semiconductor Corporation

AN-8027 - FAN480X PFC+PWM Combination

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

16-Pin Dual In-Line Package (DIP)

16-Pin Dual In-Line Package (DIP)

16-Pin Small Outline Package (SOP)

Tape & Reel

16-Pin Small Outline Package (SOP)

Tape & Reel

16-Pin Dual In-Line Package (DIP)

16-Pin Dual In-Line Package (DIP))

16-Pin Dual In-Line Package (DIP))

16-Pin Small Outline Package (SOP)

Tape & Reel

16-Pin Small Outline Package (SOP)

Tape & Reel

16-Pin Small Outline Package (SOP)

Tape & Reel

PFC:PWM Frequency Ratio

2008 Fairchild Semiconductor Corporation

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

2008 Fairchild Semiconductor Corporation

Typical Application Current Mode

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

2008 Fairchild Semiconductor Corporation

Typical Application Voltage Mode

Figure 3. FAN4800A/C Function Block Diagram

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

Figure 4. FAN4801/02/02L Function Block Diagram

Figure 5. DIP Top Mark

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

Figure 6. SOP Top Mark

2008 Fairchild Semiconductor Corporation

Figure 7. Pin Configuration (Top View)

Reference Voltage. Buffered output for the internal 7.5V reference.

FAN4800A/C, FAN4801/02/02L PFC/PWM Controller Combination

2008 Fairchild Semiconductor Corporation

SS, FBPWM, RAMP, OPWM, OPFC

IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA