Institute of Aeronautical Engineering: Mid Semester Test

INSTITUTE OF AERONAUTICAL ENGINEERING
Dundigal, Hyderabad - 500 043

ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE DESCRIPTION
Course Title
Course Code
Academic Year
Regulation
Course Structure
Course
Coordinator
Team Instructors
Branch
I.
II.
Credits
4
Mr. B. Naresh
Mr. D. Loknath Reddy
II - B. Tech -ECE
Course overview
The course will make them learn the basic theory of switching circuits and their
applications in detail. Starting from a problem statement they will learn to design
circuits of logic gates that have a specified relationship between signals at the input
and output terminals. They will be able to design combinational and sequential
circuits .They will learn to design counters, adders, sequence detectors. This course
provides a platform for advanced courses like Computer architecture,
Microprocessors & Microcontrollers and VLSI design. Greater Emphasis is placed on
the use of programmable logic devices and State machines.
Prerequisite(s)
Level
UG
III.
Switching theory and logic design

A30407
2015 2016
R13-JNTUH
Lectures
Tutorials
Practicals
5
1
-
Credits
4
Periods / Week
5
Prerequisites
Logical Arithmetic
Marks Distribution
Sessional Marks
Mid Semester Test

There shall be 2 midterm examinations. Each midterm
examination consists of subjective type and Objective
type tests. The subjective test is for 10 marks,
with duration of 1 hour. Subjective test of each
semester shall contain 4 questions The student has to
answer 2 questions, each carrying 5 marks. The
objective type test is for 10 marks with duration
of 20minutes. It consists of 10 Multiple choice and 10
objective type questions. The student has to answer
all the questions and each carries half mark. First
midterm examination shall be conducted for the first
21/2 unit of syllabus and second midterm examination
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University
End Exam
marks
Total marks
75
100
shall be conducted for the remaining portion.

Five marks are earmarked for assignments.
There shall be two assignments in every theory
course. Marks shall be awarded considering the
average of two assignments in each course reason
whatsoever, will get zero marks(s).the conduct of the
second mid-examination. The total marks secured by
the student in each mid-term examination are
evaluated for 25 marks, and the average of the two
mid-term examinations shall be taken as the final
marks secured by each candidate.
IV.
Evaluation Scheme
Sl.No
1
2
3
4
5
V.
Component
I Mid Examination
I Assignment
II Mid Examination
II Assignment
End Semester Examination
Duration(Hrs)
1hr 20 min
-1hr 20min
-3hr
Marks
20
5
20
5
75
Course Educational Objectives

1. To learn basic for the design of digital circuits and fundamental concepts used in
the design of digital systems.
2. To understand common forms of number representation in digital electronic
circuits and to be able
to convert between different representations.
3. To implement simple logical operations using combinational logic circuits.
4. To Design combinational logic circuits, sequential logic circuits.
5. To impart to student the concepts of sequential circuits, enabling them to analyze
sequential Systems in terms of state machines.
6. To implement synchronous state machines using flip-flops.
VI.
Course Outcomes
1. Understand number systems, binary addition and subtraction, 2s complement

representation and operations with this representation and understand the
different binary codes.
2. Explain switching algebra theorems and apply them for logic functions.
3. Identify the importance of SOP and POS canonical forms in the minimization or
other optimization of Boolean formulas in general and digital circuits.
4. Discuss about digital logic gates and their properties.
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5. Evaluate functions using various types of minimizing algorithms like Boolean

algebra, Karnaugh map or tabulation method.
6. Analyze the design procedures of Combinational logic circuits.
7. Understand bi-stable elements and different types of latches and flip-flops.
8. Analyze the design procedures of small sequential circuits and devices and to
use standard sequential functions /building blocks to build larger more complex
circuits
9. Understand and analyze the design a finite state machine, asm charts...
VII.
How Course Outcomes are assessed

Program Outcomes
PO 1
PO 2
PO 3
PO 4
PO 5
P0 6
PO 7
PO 8
PO 9
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Engineering knowledge: An ability to apply

knowledge of basic sciences, mathematical skills,
engineering and technology to solve complex
electronics
and
communication
engineering
problems (Fundamental Engineering Analysis
Skills).
Problem analysis: An ability to identify,
formulate and analyze engineering problems using
knowledge of Basic Mathematics and Engineering
Sciences (Engineering Problem Solving Skills).
Design/development of solutions: An ability to
provide solution and to design Electronics and
Communication Systems as per social needs
(Social Awareness).
Conduct investigations of complex problems:
An ability to investigate the problems in
Electronics and Communication field and develop
suitable solutions (Creative Skills).
Modern tool usage: An ability to use latest
hardware and software tools to solve complex
engineering problems (Software and Hardware
Interface).
The engineer and society: An ability to apply
knowledge of contemporary issues like health,
Safety and legal which influences engineering
design (Social Awareness).
Environment and sustainability: An ability to
have awareness on society and environment for
sustainable
solutions
to
Electronics
and
Communication Engineering problems (Social
Awareness).
Ethics: An ability to demonstrate understanding of
professional
and
ethical
responsibilities
(Professional Integrity).
Individual and team work: An ability to work
efficiently as an individual and in multidisciplinary
Level
H
Proficiency
assessed by
Lectures,
Assignments,
Exercises.
Hands on
Practice
Sessions.
--
Lab sessions,
Exams
Design
Exercises.
--
Oral
discussions
--
Seminars
Discussions
teams (Team work).

PO
10
PO
11
PO
12
VIII.
Communication: An ability to communicate

effectively and efficiently both in verbal and
written form (Communication Skills).
Life-long learning: An ability to develop
confidence to pursue higher education and for lifelong
learning
(Continuing
Education
Awareness).
Project management and finance: An ability to
design, implement and manage the electronic
projects for real world applications with optimum
financial resources (Practical Engineering
Analysis Skills).
N - None
related
Syllabus:
S - Supportive
S
S
Seminars, Paper
Presentations
Discussions,
Exams
Development
of Mini
Projects
H - Highly
UNIT -I:Number
System
and
Boolean
Algebra
And
Switching
Functions:
Number Systems, Base Conversion Methods, Complements of Numbers, CodesBinary Codes, Binary Coded Decimal Code and its Properties, Unit Distance Codes,
Alpha Numeric Codes, Error Detecting and Correcting Codes.
Boolean Algebra: Basic Theorems and Properties, Switching Functions, Canonical
and Standard Form, Algebraic Simplification of Digital Logic Gates, Properties of
XOR Gates, Universal Gates, Multilevel NAND/NOR realizations.
UNIT II: Minimization and Design of Combinational Circuits:
Introduction, The Minimization with theorem, The Karnaugh Map Method, Five and
Six Variable Maps, Prime and Essential Implications, Dont Care Map Entries, Using
the Maps for Simplifying, Tabular Method, Partially Specified Expressions, Multioutput Minimization, Minimization and Combinational Design, Arithmetic Circuits,
Comparator, Multiplexers, Code Converters, Wired Logic, Tristate Bus System,
Practical Aspects related to Combinational Logic Design, Hazards and Hazard Free
Relations.
UNIT -III: Sequential Machines Fundamentals:
Introduction, Basic Architectural Distinctions between Combinational and Sequential
circuits, The Binary Cell, Fundamentals of Sequential Machine Operation, The FlipFlop, The D-Latch Flip-Flop, The Clocked T Flip-Flop, The Clocked J-K Flip-Flop,
Design of a Clocked Flip-Flop, Conversion from one type of Flip-Flop to another,
Timing and Triggering Consideration, Clock Skew.
UNIT -IV: Sequential Circuit Design and Analysis:
Introduction, State Diagram, Analysis of Synchronous Sequential Circuits,
Approaches to the Design of Synchronous Sequential Finite State Machines, Design
Aspects, State Reduction, Design Steps, Realization using Flip-Flops
Counters - Design of Single mode Counter, Ripple Counter, Ring Counter,
Shift Register, Shift Register Sequences, Ring Counter Using Shift Register.
UNIT -V:
Sequential Circuits: Finite state machine-capabilities and limitations, Mealy and
Moore models-minimization of completely specified and incompletely specified
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sequential machines, Partition techniques and Merger chart methods-concept of

minimal cover table.
Algorithmic State Machines: Salient features of the ASM chart-Simple
examples-System design using data path and control subsystems-control
implementations-examples of Weighing machine and Binary multiplier.
Textbooks:
1. M. Morris Mano, Michael D. Ciletti (2008), Digital Design, 3rd edition, Pearson
Education/PHI, India.
2. Zvi. Kohavi (2004), Switching and Finite Automata Theory, 3rd edition, Tata
McGraw Hill, India
Reference Books:
1. Fredriac J. Hill, Gerald R.Peterson, 3rd edition, Introduction to switching theory and
logic design.
2. Thomas L.Floyd , Pearson 2013, Digital fundamentals A Systems Approach
3. Ye Brian and Holds Worth, Elsevier, Digital logic design
4. John M. Yarbrough, Thomson publications 2006tld syllabus, Digital logic
applications and design.
5. Roth (2004), Fundamentals of Logic Design, 5th edition, Thomson.
6. Comer, 3rd, oxford 2013, Digital Logic and State machine Design
7. Anand Kumar, Switching Theory and Logic Design
IX.
Course Plan
At the end of the course, the students are able to achieve the following course
learning outcomes (CLO):
Lectu Unit
re
NO
No.
Number
systems,
conversion methods
1-3
4-5
6-7
8-10
11-13
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Topics to be covered
base
Course Learning Outcomes Reference

Understand
the
number
systems
conversions.
different
T1 - 1.1 to
and
its
1.5
Complements
of
numbers
Understand the arithmetic operations
codes-binary codes, BCD code
T1 - 1.7
carried by digital systems.
and its properties ,
Unit
distance
code,
Understand
the
different
alphanumeric codes, and error
code representations in digital T1 - 1.7
detecting
and
correcting
systems.
codes.
Basic
theorems
and
its Learn Boolean algebra and
properties,
switching logical operations in Boolean T1 2.1 to
functions,
canonical
and algebra.
2.6
standard form.
Algebraic
simplification
of Apply different logic gates to T1 2.8
digital logic gates, properties functions and simplify them.
of XOR gates.
14-15
16-21
22-23
24-26
27-31
32-33
34-36
37
38-39
40-45
46-49
50-51
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Understand and build the

Universal
gates,
Multilevel
T1- 3.7 to
different functions by using
NAND/NOR realizations.
3.8
universal gates.
Introduction, the minimization
with theorem , The k-map
method, five and six -variable Analyze the redundant terms
T1 - 3.1 to
map Prime and essential and minimize the expression
3.9
implications, Dont care map using K-maps
entries, using K maps for
simplifying
Tabular method, Partially
Identify the redundant terms
T1 - 3.5 to
II specified expressions , multi- and minimize the expression
3.9
output minimization
using tabular method
combinational design,
Apply the logic gates and
T1 4.1 to
arithmetic circuits,
design of combinational
4.9
comparator, multiplexers
circuits
Code convertors, wired logic,
tristate bus system, practical
aspects related to
Design of different
R4 - 6.4.3 ,
combinational logic design,
combinational logic circuits
4.11
hazards and hazard free
relations.
Introduction,
Basic
architectural
distinctions Understand
the
clock
between combinational and dependent circuits and identify T1 5.1
sequential circuits, the binary the
differences
between to 5.2
III cell, the fundamentals of clocked and clock less circuits
sequential machine operation.
flip-flop, D-Latch Flip-flop,
Clocked T Flip-flop, Clocked
JK flip-flop. design of a
Apply and design clock
T1 5.3 to
clocked flip-flop conversion
dependent circuits.
5.5
from one type of flip-flop to
another
Timing and triggering
Understand how the flip-flops
T1 - 5.5
consideration , clock skew
are synchronized.
IV Introduction, State diagrams,
Understand how synchronous T1 - 5.7
Analysis of synchronous
sequential circuit works.
to 5.8
sequential circuit
Approaches to the design of
synchronous sequential finite
Analyze the procedure to
state
machines,
design
T1 - 6.1,
reduce the internal states in
aspects
State
reduction,
6.3
sequential circuits.
IV design steps, realization using
flip-flop.
Ripple counter, Ring counter, Apply the sequential circuits
Shift registers, Shift register and
design
the
different T1 - 6.1 to
sequences, Ring counter using memory devices and counting 6.5
shift register.
circuits.
Finite State machine
Understand the FSM and its R4 - 7.1 to
Capabilities and limitations,
design principles.
7.2
mealy and Moore models.
52-58
V
59-62
Minimization of completely
specified and incompletely
specified sequential machines
partition techniques and
merger chart methods
concept of minimal cover
table.
Salient features of the ASM
Chart- Simple Examplessystem design using data path
and control subsystems
Model an ASM chart and

R4 - 7.5,
describe system design using
7.7
different techniques.
Illustrate control
implementations
control implementations
63-65
Illustrate minimization of
complete and incomplete state R4 - 7.3,
machines and to write a
7.4
minimal cover table
R7
Examples of weighing
Analyze the different
machine and Binary multiplier examples to ASM.
R5 - 18.1
TO 18.3
X:
Mapping course objectives leading to the achievement of the program
outcomes
Course
Objecti
ves
I
II
III
IV
V
VI
PO
1
H
PO
2
PO
3
PO
4
H
Program Out Comes

PO PO
PO
PO
5
6
7
8
H
S
S
S
S
H
H
H
PO
9
PO
10
PO
12
S
S
S
H
H
H
H
H
S = Supportive
PO
11
S
H = Highly Related
XI:
Mapping course learning objectives leading to the achievement of the
program outcomes:
COURSE
OUTCO
MES
1
2
7 | Page
PROGRAM OUTCOMES
PO
1
PO
2
PO
3
P
O
4
PO
5
PO
6
H
H
PO
7
PO
8
PO
9
P
O
10
H
S
P
O
11
PO
12
S
H
S
8
9
H
S
S
H
H
S = Supportive
Prepared By
Date
H = Highly Related
: B.Naresh, Assistant Professor Department of ECE

: 21st may, 2015
HOD,ECE
8 | Page

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INSTITUTE OF AERONAUTICAL ENGINEERING

Dundigal, Hyderabad - 500 043

Switching theory and logic design

Mid Semester Test

shall be conducted for the remaining portion.

Course Educational Objectives

1. Understand number systems, binary addition and subtraction, 2s complement

5. Evaluate functions using various types of minimizing algorithms like Boolean

How Course Outcomes are assessed

Engineering knowledge: An ability to apply

teams (Team work).

Communication: An ability to communicate

sequential machines, Partition techniques and Merger chart methods-concept of

Course Learning Outcomes Reference

Understand and build the

Model an ASM chart and

Program Out Comes

: B.Naresh, Assistant Professor Department of ECE

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