HARDWARE OF THE ORIGINAL IBM

PC MICROCOMPUTER

HARDWARE OF THE
ORIGINAL IBM PC
MICROCOMPUTER

12.1 Architecture of the Original IBM PC

System Processor Board
12.2 System Processor Circuitry
12.3 Wait-State Logic and NMI Circuitry
12.4 Input/Output and Memory Chip-Select
Circuitry
12.5 Memory Circuitry
12.6 Direct Memory Access Circuitry
611 37100 Lecture 12-2

HARDWARE OF THE ORIGINAL IBM

PC MICROCOMPUTER
12.7 Timer Circuitry
12.8 Input/Output Circuitry
12.9 Input/Output Channel Interface

611 37100 Lecture 12-3

12.1 Architecture of the Original IBM

PC System Processor Board
Major functional elements of the PC:
MPU
PIC
DMA
PIT
PPI
ROM
RAM

611 37100 Lecture 12-4

12.1 Architecture of the Original IBM

PC System Processor Board

12.1 Architecture of the Original IBM

PC System Processor Board

PC memory map

PC system peripheral addresses

611 37100 Lecture 12-5

611 37100 Lecture 12-6

12.1 Architecture of the Original IBM

PC System Processor Board

12.1 Architecture of the Original IBM

PC System Processor Board

8255A I/O map

8255A I/O map

611 37100 Lecture 12-7

12.1 Architecture of the Original IBM

PC System Processor Board

611 37100 Lecture 12-8

12.2 System Processor Circuitry

8284A Clock Generator

Interrupt request priority assignment for peripheral devices

Number

Usage

NMI

Parity

Timer

Keyboard

Reserved

Asynchronous Communication (Secondary)

SDLC Communications
BSC (Secondary)

Asynchronous Communication (Primary)

SDLC Communications
BSC (Primary)

Fixed disk

Diskette

Printer

611 37100 Lecture 12-9

8259A PIC

8288 Bus Controller

611 37100 Lecture 12-10

12.2 System Processor Circuitry

12.2 System Processor Circuitry

Clock generator circuitry

Microprocessor, system data bus, and bus controller

Clock generator circuitry serves three functions:

Clock signal generation
Reset signal generation (Power on reset)
Ready signal generation (Bus synchronization)
Three clock output signals of the 8284A:
The oscillator clock (OSC) at 14.31818 MHz
The TTL peripheral clock (PCLK) at 2.385 MHz
The 8088 microprocessor clock (CLK88) at 4.77 MHz
Clock generator circuitry provides synchronization of the
8088s bus operations with its memory and I/O peripherals.
For slow memory or peripherals, synchronization is achieved
by inserting wait states into the bus cycle to extend its
duration.
611 37100 Lecture 12-11

In general, memory and I/O peripherals are

attached to the 8088 microprocessor at the system
bus. However, both the 8259A interrupt controller
and 8087 numeric coprocessor are attached
directly to the local bus.
The 8288 bus controller monitors the codes output
on the 8088s status lines and produces
appropriate system bus control signals.
The 8288 also produces I/O and memory read and
write control signals.

611 37100 Lecture 12-12

12.2 System Processor Circuitry

12.3 Wait-State Logic and NMI Circuitry

Interrupt controller

External hardware interrupt interface is

implemented for the IBM PC with the 8259A
programmable interrupt controller.
The 8259A monitors the state of interrupt request
lines IRQ0 through IRQ7 to determine if any
external device is requesting service.
The operating configuration of the 8259A needs to
be initialized at power-on of the system. This
initialization is achieved by writing to the 8259As
internal registers over the local bus.

611 37100 Lecture 12-13

12.3 Wait-State Logic and NMI Circuitry

Wait-state logic and NMI circuitry

611 37100 Lecture 12-14

12.4 Input/Output and Memory ChipSelect Circuitry

I/O Chip Selects

Wait-state logic circuitry

The wait-state circuitry is used to insert one wait

state into I/O channel, I/O, and DMA bus cycles
Hold/hold acknowledge circuitry
The hold/hold acknowledge circuitry is used to grant
the 8237A DMA controller access to the system bus.
Nonmaskable interrupt circuitry
There are three sources for applying a nonmaskable
interrupt to the 8088 microprocessor:

Memory Chip
Selects

The 8087 numeric coprocessor (N P NPI)

The memory parity check (MPI)
The I/O channel check (PCK)
611 37100 Lecture 12-15

Peripheral/memory chip-select circuitry

611 37100 Lecture 12-16

12.4 Input/Output and Memory ChipSelect Circuitry

12.4 Input/Output and Memory ChipSelect Circuitry

I/O chip selects

The I/O chip select circuitry decodes the I/O address
corresponding to the LSI peripheral devices, such as
the DMA controller, interrupt controller, programmable
interval timer, and programmable peripheral interface
controller.
To access a register within one of the peripheral
devices, an I/O instruction must be executed to read
from or write to the register. The address output on
address line A0 through A9 during the I/O bus cycle is
used to both chip-select the peripheral device and
select the appropriate register.

I/O chip selects

To produce an I/O chip-select signal, address bits XA0
to XA4 are not used and, therefore, the individual I/O
chip select signals produced actually correspond to a
range of addresses.
Address
range

Signal

Function

Conditions

0-1F

DMA CS

DMA controller

Non DMA bus cycle

20-3F

INTR CS

Interrupt controller

Non DMA bus cycle

40-5F

T/C CS

Interval timer

Non DMA bus cycle

60-7F

PPI CS

Parallel Peripheral interface

Non DMA bus cycle

80-9F

WRT DMA PG REG

DMA page register

Non DMA bus cycle, XIOW active

A0-BF

WRT NMI REG

NMI control register

Non DMA bus cycle, XIOW active

Peripheral address decoding

611 37100 Lecture 12-17

611 37100 Lecture 12-18

12.4 Input/Output and Memory ChipSelect Circuitry

12.4 Input/Output and Memory ChipSelect Circuitry

Memory chip selects

The output signals produced for ROM in the circuit are
ROM address select (ROM ADDR SEL) and chip
selects CS0 through CS7. The ROM ADDR SEL signal
has two functions: to enable the ROM chip select
decoder and to control the direction of data transfer
through the ROM data bus transceiver.

Memory chip selects

The chip-select outputs used to control the operation
of RAM are RAM ADDR SEL and ADDR SEL.
The RAS0, RAS1, RAS2, RAS3 signals are used to
refresh the DRAM devices in the RAM array.

Address range

Chip select

F0000-F1FFF

CS0

F2000-F3FFF

CS1

F4000-F5FFF

CS2

F6000-F7FFF

CS3

F8000-F9FFF

CS4

FA000-FBFFF

CS5

FC000-FDFFF

CS6

FE000-FFFFF

CS7

611 37100 Lecture 12-19

Address range

Condition

RAM ADDR SEL

Inactive DACK 0 BRD

00000-0FFFF

RAS0 , CAS0

Active XMEMR or XMEMW

10000-1FFFF

RAS1 , CAS1

Active XMEMR or XMEMW

20000-2FFFF

RAS2 , CAS2

Active XMEMR or XMEMW

30000-3FFFF

RAS3 , CAS3

Active XMEMR or XMEMW

ROM address decoding

Active signal

00000-3FFFF

RAM address decoding

611 37100 Lecture 12-20

12.5 Memory Circuitry

12.5 Memory Circuitry

ROM array circuitry

The system processor board of the PC is equipped
with 48Kbytes of ROM and either 64K or 256Kbytes of
RAM.
Each of the EPROMs is enabled by one of the ROM
chip-select signals, CS2 through CS7, which are
generated by the ROM address decoder.
The address outputs on the lower 13 address lines of
the system address bus, A0 through A12, are used to
select the specific byte of data within an EPROM.
The direction of data transfer through the data bus
transceiver is set by the logic level at its data direction
(DIR) input.

ROM array circuitry

611 37100 Lecture 12-21

Octal buffers

EPROMs

Data bus
transceivers

611 37100 Lecture 12-22

12.5 Memory Circuitry

12.5 Memory Circuitry

RAM array circuitry

In each RAM bank, eight 64K x 1-bit dynamic RAMs
(DRAMs) are used for data storage, and ninth DRAM
is included to hold parity bits for each of the 64K
storage locations.
The 74LS158 data selectors are used to multiplexed
the 16-bit memory address into a byte-wide row
address and byte-wide column address.
Each DRAM device outputs a bit of data held in the
storage location corresponding the selected row and
column address. The byte of data is passed over data
lines MD0 through MD7 to the 74LS245 bus transceiver.
The parity generator/check circuitry is used to
improve the reliability of data storage in the RAM array.

RAM array circuitry

611 37100 Lecture 12-23

Bus transceiver

RAM bank 0

Parity generator/checker
Data
selectors

611 37100 Lecture 12-24

12.5 Memory Circuitry

12.6 Direct Memory Access Circuitry

RAM array circuitry

DMA circuitry
DMA Controller

Hardware Requests

DMA Page Registers

Address Latch

RAM banks 2 and 3

611 37100 Lecture 12-25

12.6 Direct Memory Access Circuitry

611 37100 Lecture 12-26

12.7 Timer Circuitry

Programmable Interval Timer, PIT

DMA circuitry
The DMA capability permits high-speed data transfers
to take place between two sections of memory or an
I/O device and memory.
There are 16 registers within the 8237A DMA
controller that determine how and when the four DMA
channels work. The 8088 communicates with these
registers by executing I/O instructions.
DMA channel 0 is dedicated to RAM refresh and that
channel 2 is used by the floppy disk subsystem.
Use of a DMA channel is initiated by a request from
hardware (DRQ0 through DRQ3).

611 37100 Lecture 12-27

12.7 Timer Circuitry

The timer circuitry controls four basic system functions:
Time-of-day clock.
DRAM refresh
Speaker
Cassette
The programmable interval timer, 8253, provides three
independent, programmable, 16-bit counters for use in the
microcomputer system.
The control registers of the 8253 are located in the range
004016 through 004316 of the PCs I/O address space.
004016
004116
004216
004316

-- Counter 0
-- Counter 1
-- Counter 2
-- Mode Control Register

611 37100 Lecture 12-29

611 37100 Lecture 12-28

12.7 Timer Circuitry

Microprocessor interface and clock inputs

Amplifier Circuit
For Cassette Data Input

Outputs of the PIT

The 8253 output OUT0 is produced by timer 0 and is set at a
regular time interval equal to 54.936 ms. This output is
applied to the timer interrupt request input (IRQ0) of the
8259A interrupt controller, where it represents the time-ofday interrupt.
Timer output OUT1 is generated by timer 1 and also occurs
at a regular interval of 15.12 s. It is used to send request
for service to the 8237A DMA controller and asks it to
perform a refresh operation for the dynamic RAM subsystem.
The output OUT2 is generated by time 2 and is used three
ways in the PC:
It is sent as the signal T/C2 OUT to port C of the 8255A PIC.
It is used as an enable signal for speaker data.
It is used to supply the record tone for the cassette interface.

611 37100 Lecture 12-30

12.8 Input/Output Circuitry

8255A PIC

12.8 Input/Output Circuitry

I/O Channel RAM Switch

Three basic types of functions are performed through

input/output circuitry:
Serial-in Parallel-out Shift Register

Keyboard
Interface Circuitry

For 8088 to input data from the keyboard and output

data to the cassette and speaker.
The 8088 use this interface to read the setting of DIP
switches to determine system configuration information.
Certain I/O ports are used for special functions, such
as clearing the parity check flip-flop and reading the
state of the parity check flip-flop through software.
The I/O circuitry of the PC system processor board is

designed using the 8255-A programmable peripheral

interface (PPI) IC.

Inputting System
Configuration DIP Switch

611 37100 Lecture 12-31

611 37100 Lecture 12-32

12.8 Input/Output Circuitry

12.8 Input/Output Circuitry

8255A programmable peripheral interface

The 8255A PPI has three 8-bit ports for implementing
inputs or outputs. In the PC, ports PA and PC are
configured to operate as inputs, and the port PB is set
up to work as outputs.
The ports PA, PB,and PC reside at the I/O addresses
006016,, 006116, and 006216, respectively.
The operation of the 8255A ports are configurable
under software control. Writing a configuration byte to
the command/mode control register does this. The
command/mode control register is located at address
006316.

8255A programmable peripheral interface

The input port PA is used to both read the
configuration switches of SW1 and communicate with
the keyboard.
Output port PB controls the cassette and speaker. It
also supplies enable signals for RAM parity check, I/O
channel check, and reading of the configuration
switches or keyboard
The input port PC is used to read the I/O channel RAM
switches (SW2), parity check signal, I/O channel check
signal, terminal count status from timer 2, and cassette
data.

611 37100 Lecture 12-33

12.8 Input/Output Circuitry

12.8 Input/Output Circuitry

Inputting system configuration DIP switch settings

EXAMPLE
The system configuration byte read from input port PA is 7D16.
Describe the PC configuration for these switch setting.

Solution:
Use the IN AL, 60H instruction to obtain the data from port PA.
Expressing the switch setting byte in binary form, we get
PA7PA6PA5PA4PA3PA2PA1PA0 = 7D16 = 011111012
We find that
PA0 = 1 indicates that the system has floppy-disk drive(s)
PA1 = 0 indicates that an 8087 is not installed
PA3PA2 = 11 indicates that the memory is 256K
PA5PA4 = 11 indicates a monochrome monitor
PA7PA6 = 01 indicates that the system has two floppy drives.

611 37100 Lecture 12-35

611 37100 Lecture 12-34

Scanning the keyboard

The keyboard of the PC is interfaced to the 8088
through port PA of the 8255A.
The keyboard of the PC generates a keyscan code
whenever one of its keys is depressed. Bits of the
keyscan code are input to the system processor board
in serial form at the KBD DATA pin of the keyboard
connector synchronously with pulses at KBD CLK. The
serial data is applied to the 74LS322 serial-in, parallelout shift register.
In response to the IRQ1 interrupt request, the 8088
initiates a keyscan-code service routine. This routine
reads the keyscan code by inputting the contents of
the shift register.

611 37100 Lecture 12-36

12.8 Input/Output Circuitry

12.9 Input/Output Channel Interface

Port C input and output functions

The five connected I/O channel RAM switches are
used to identify the amount of read/write memory
provided through the I/O channel. The settings of
these switches are read through the 8255A PPI.
The four least significant bit lines of port PC indicate
the status of the I/O channel RAM switches. The four
most significant bit lines are supplied by signals
generated else where on the system processor board.
PC5 through PC7 allow the 8088 to read the state of
the following signals through software:

The input/output channel is the system expansion bus

RAM parity check (PCK)

I/O channel check (I/O CH CK)
Time terminal count (T/C2 OUT)
Cassette interface input (CASS DATA IN)

611 37100 Lecture 12-37

of the IBM personal computer.

The chassis of the PC has five 62-pin I/O channel

card slots. Using these slots, special function adapter

cards can be added to the system to expand its
configuration.
62 signals are provided in each I/O channel slot:
8-bit data bus
20-bit address bus
Six interrupts
Memory and I/O read/write controls
Clock and timing signals
A channel check signal
Power and ground pins

611 37100 Lecture 12-38

12.9 Input/Output Channel Interface

12.9 Input/Output Channel Interface

I/O channel interface

I/O channel interface

Mnemonic
A0 - A19

O
O

ALE

Address latch enable

CLK

Clock

Data lines 0 7

DMA acknowledge 0 3

DRQ1 DRQ3

DMA request 1 3

I/O CH CK

I/O channel check

I/O CH RDY

I/O channel ready

IOR

I/O read command

IOW

I/O write command

DACK0 DACK7

IRQ2 IRQ7

Interrupt request 2 7

MEMR

Memory read command

MEMW

Memory write command

Oscillator

OSC
RESET DRV
T/C

611 37100 Lecture 12-39

Function

Address enable

D0 D7

Name
Address lines 0-19

AEN

Reset
Terminal count

611 37100 Lecture 12-40

O
O