Ian$Chaffin$

ENGS$199$
Final$Report$
$

Flash$Memory:$A$Brief$Introduction$
$

Introduction$
$
$
The$goal$of$this$report$is$to$provide$a$brief$yet$sufficiently$thorough$
explanation$of$Flash$Memory$operation$so$that$a$student$with$some$background$in$
semiconductor$devices$could$read$the$report$and$have$a$good$understanding$of$how$
Flash$works.$It$is$important$that$students$in$the$semiconductor$field$have$an$
understanding$of$Flash$because$its$use$is$widespread.$Memory$is$now$an$
indispensable$part$of$cell$phones,$digital$cameras,$personal$computers,$automotive$
systems$and$many$others.$The$Flash$memory$industry$is$controlled$by$a$few$
semiconductor$superpowers$including,$Samsung,$Toshiba,$Micron$and$Intel.$In$2010,$
Samsung's$quarterly$flash$memory$revenue$was$$1.7$P$$2.1$billion.$Each$company$is$
pushing$towards$higher$density$and$faster$operation.$$An$explanation$of$the$devices$
operation$will$be$given$later$so$as$to$provide$an$understanding$of$the$challenges$
associated$with$making$Flash$smaller$and$faster.$$
$
$History$
$
$
Dr.$Fujio$Masuoka$invented$flash$Memory$while$working$for$Toshiba$in$the$
1980's.$At$first$the$device$was$known$as$simultaneously$erasable$EEPROM$
(Electrically$Erasable$Programmable$Read$Only$Memory).$$However$the$name$flash$
was$used$because$lots$of$memory$could$be$erased$"in$a$flash."$When$NAND$flash$was$
invented$in$1987,$the$name$flash$made$it$into$the$title$of$Dr.$Masuoka's$paper$and$it$
became$a$household$from$then$on$as$NAND$structure$devices$reduced$the$memory$
cell$area$to$achieve$a$lower$cost$per$bit.$These$devices$were$an$important$step$
forward$for$memory$since$they$could$retain$data$even$when$the$power$was$
switched$off,$unlike$the$dynamic$random$access$memory$(DRAM)$chips$that$were$
already$prevalent$in$the$early$1980's.$Despite$facilitating$the$invention$of$flash,$
Toshiba$has$not$been$the$only$contributor.$Intel$was$right$on$their$tale$from$the$
outset$being$the$first$to$commercialize$NOR$flash$in$the$late$1980's.$As$the$century$
turned,$Flash$became$a$staple$in$the$memory$industry$with$companies$like$IBM$
creating$new$applications$for$flash$like$the$USB$drive.$With$more$companies$
developing$flash$devices,$the$size$of$the$devices$followed$closely$with$Moore's$law$of$
scaling.$Figure$1$shows$the$scaling$timeline$from$the$invention$of$flash$to$present.$As$
of$2013,$Samsung$has$mass$produced$128Gb$3Pbit$MLC$NAND$flash$in$10$nm$class$
process$technology.$Many$challenges$arise$when$venturing$past$the$10$nm$mark$for$
flash$memory.$These$will$be$discussed$later,$but$for$now$the$operation$of$flash$
devices$will$be$discussed.$
$
$
$

Figure$1:$NAND$Flash$Device$Scaling$by$Industry$Leader$

$
$
Operation$
$
To$understand$the$method$by$which$a$single$flash$cell$works$it$is$important$to$draw$
some$comparisons$to$the$classic$MOSFET.$For$an$nMOS$transistor$a$voltage$is$
applied$at$the$gate$which$induces$a$flow$of$electrons$from$source$to$drain$in$the$
channel.$In$order$to$obtain$a$functioning$memory$device,$the$charge$that$is$
generated$in$the$device$through$the$gate$voltage$must$be$stored$in$some$capacity.$
This$is$accomplished$through$a$floating$gate$transistor,$in$which$an$additional$gate$
is$electrically$isolated$and$placed$between$the$control$gate$and$the$substrate.$The$
two$devices$are$shown$below$in$figure$2.$
$
$

Figure$2:$MOSFET$and$Floating$Gate$Transistor$Diagrams$$

Charge$is$added$to$the$floating$gate$when$electrons$cross$from$the$channel$to$the$
floating$gate$via$quantum$tunneling.$When$the$floating$gate$is$uncharged$the$cell$is$
given$a$bit$value$of$1$and$when$the$cell$is$charge$it$is$given$a$value$of$0.$The$reason$
being$that$when$there$is$charge$on$the$floating$gate,$it$impedes$the$flow$of$electrons$
in$the$channel$and$thereby$increases$the$threshold$voltage$by$some$VT.$The$
method$used$to$read$a$cell$is$simple.$An$intermediate$voltage$is$applied$to$the$
control$gate$and$the$drain$to$source$current$is$measured.$If$there$is$current$flowing$
then$the$device$is$"ON"$and$there$is$no$charge$on$the$floating$gate.$If$there$is$no$
current$flowing$then$the$device$is$"OFF"$corresponding$to$a$bit$value$of$0$since$the$
floating$gate$is$charged.$The$change$in$the$threshold$voltage$from$the$additional$
charge$on$the$floating$gate$is$given$by$the$following$equation:$
$
!!"
$
(1)$
!!! =
$
!!"
$
$
In$order$to$obtain$an$expression$for$the$charge$on$the$floating$gate$as$a$
function$of$the$voltage$on$the$drain$and$the$floating$gate,$the$device$can$be$modeled$
using$capacitive$coupling.$From$the$simple$charge$expression$Q$=$CV,$each$node$
interface$with$the$floating$gate$can$be$modeled$as$a$capacitor$and$added$together$to$
obtain$an$expression$for$the$charge.$Using$some$algebra,$the$desired$expression$is$
obtained$and$illustrated$in$Figure$3.$
$

Figure$3:$Capacitive$Coupling$Diagram$and$GCR$Derivation$$

$
The$equation$shown$in$Figure$3$is$important$because$it$provides$a$way$of$relating$
the$voltage$on$the$floating$gate$to$the$voltage$on$the$control$gate$via$the$GateP
Coupling$Ratio$(GCR).$Typically$a$GCR$of$more$than$0.6$is$essential$for$satisfactory$
operation.$This$means$that$the$thickness$of$the$blocking$oxide$must$be$at$least$1.67$
times$the$length$of$the$tunnel$oxide.$$
$
So$how$does$charge$build$up$on$the$floating$gate$in$the$first$place?$The$
charge$build$up$is$achieved$through$quantum$tunneling.$In$order$to$program$the$

device$very$quickly$a$specific$type$of$tunneling$know$as$FowlerPNordheim$(FPN)$
tunneling$is$employed,$which$uses$high$voltages$to$cause$electrons$to$tunnel$with$
high$current$density.$The$expression$for$the$current$density$as$a$function$of$electric$
field$of$injection$is$given$below:$$
$
!
$
(2)$
! !
!
!!!! ! = !!!!"#
! !!"# $
$
!/!
!! !
4 2! !!
!! = !
!!!!!! = !
$
8!!! !
3!"
$
Where$h$is$Plancks$constant,$b$is$the$energy$barrier$at$injecting$interface,$Einj$is$the$
electric$field$at$the$injecting$interface,$q$is$the$charge$of$an$electron,$m$is$the$free$
electron$mass,$m*$is$the$effective$mass$of$an$electron$in$SiO2$bandgap$and$$=$h/2.$
The$equation$can$be$rearranged$to$draw$out$the$energy$barrier$term$b.$$
$
!
!!"#
!!!! ! = ! !!
!
!!

!/!

!
!!! !

!!"#

$
Now$the$expression$shows$the$relationship$between$the$energy$barrier$and$the$
injecting$field.$When$Einj$increases$the$current$density$increases,$when$b$increases$
the$current$density$decreases.$As$long$as$the$voltage$drop$across$the$tunnel$oxide$is$
greater$than$b$then$the$cell$will$undergo$FPN$tunneling.$$
$
When$the$device$is$being$programed$the$initial$charge$on$the$floating$gate$is$
zero$and$drain$is$held$at$ground.$As$an$example$the$control$gate$is$held$at$15$V$and$
the$GCR$is$0.6.$At$first$the$electrons$tunnel$across$the$tunnel$oxide$onto$the$floating$
gate.$As$charge$begins$to$build$on$the$floating$gate,$the$voltage$on$the$floating$gate$is$
lowered$by$the$presence$of$negative$charge$according$to$the$following$equation:$$
$
!!"
$
(3)$
!!" ! = !"# !!" +
$
!!
$
As$the$voltage$on$the$floating$gate$is$lowered$the$voltage$difference$between$the$
voltage$on$the$control$gate$and$voltage$on$the$floating$gate$increases.$Because$of$the$
increased$voltage$difference$between$the$control$gate$and$the$floating$gate,$some$
tunneling$begins$to$occur$across$the$thicker$blocking$oxide.$Eventually$enough$
charge$builds$on$the$floating$gate$that$the$two$current$densities$equilibrate.$At$this$
point$the$total$current$tunneling$onto$the$floating$gate$is$equal$to$the$total$current$
tunneling$out.$Thus$the$charge$on$the$floating$gate$saturates$at$the$equilibrium$
value.$Figure$4$illustrates$the$program$process.$
$

Figure$4:$Band$Diagrams$of$the$Program$Process$$

$
$
Erasing$is$almost$identical$to$the$programming$a$cell,$only$a$negative$voltage$
is$applied$to$the$control$gate$instead$of$a$positive$voltage$and$the$process$runs$in$
reverse.$Charge$is$retained$on$the$cell$by$simply$setting$the$control$gate$voltage$to$
zero$so$that$the$electrons$cannot$overcome$the$barrier$of$the$tunnel$oxide.$If$the$
oxides$are$sufficiently$thick$and$there$are$few$defects$then$the$charge$can$remain$on$
the$floating$gate$for$up$to$10$years.$$
$
Multiple$bits$can$be$stored$in$a$single$cell$through$a$type$of$flash$known$as$
MuliPLevel$Cell$(MLC)$flash.$MLC$devices$control$the$amount$of$charge$stored$on$the$
floating$gate$through$specified$control$gate$voltages.$Thus$a$single$cell$can$achieve$
several$different$charge$states,$which$lowers$the$required$number$of$cells$per$data$
volume.$One$of$the$main$challenges$to$MLC$is$read$disturb.$Because$each$charge$
state$is$closer$together$than$before,$applying$an$intermediate$voltage$to$read$a$cell$
can$affect$the$charge$stored$on$an$adjacent$cell.$Also$each$cell$contains$more$data$
and$is$therefore$written$to$and$erased$more$often.$As$electrons$tunnel$with$high$
energy$they$collide$with$the$oxide$lattice$and$cause$defects$that$degrade$the$oxide.$
Eventually$the$oxide$wears$down$and$the$device$no$longer$functions$properly.$MLC$
can$typically$handle$around$10,000$program/erase$cycles$while$singlePlevel$cell$
(SLC)$can$handle$100,000$cycles.$Because$MLC$is$much$cheaper$to$produce,$many$
algorithmic$solutions$have$been$devised$to$increase$the$number$of$available$cycles.$
$
Conclusion3
3
$
Because$of$the$high$density$capabilities$of$flash$it$will$continue$to$be$
enhanced$in$the$years$to$come.$However$as$devices$get$smaller,$some$barriers$to$
scaling$arise$as$well.$When$tunnel$oxides$drop$below$10$nm,$the$devices$fall$prey$to$
direct$tunneling$and$trap$assisted$tunneling$that$cut$retention$from$years$to$days.$
New$methods$for$better$retention$will$have$to$be$developed$to$produce$reliable$
single$digit$nanometer$flash$memory$technologies.$

References$
$
Brewer,$Joe,$and$Manzur$Gill.$Nonvolatile*Memory*Technologies*with*Emphasis*on*
Flash:*A*Comprehensive*Guide*to*Understanding*and*Using*NVM*Devices.$
Hoboken,$NJ:$Wiley,$2008.$Print.$
Koh,$Yohwan.$"NAND$Flash$Scaling$Beyond$20nm."$2009*IEEE*International*Memory*
Workshop$(2009):$n.$pag.$Web.$
Zhao,$Chun,$Ce$Zhao,$Stephen$Taylor,$and$Paul$Chalker.$"Review$on$NonPVolatile$
Memory$with$HighPk$Dielectrics:$Flash$for$Generation$Beyond$32$Nm."$
Materials$7.7$(2014):$5117P145.$Web.$
Figures$
$
https://en.wikipedia.org/wiki/File:NAND_scaling_timeline.png*
*
All*other*figures*were*designed*by*the*author.*
$