Report on the Intermittent Fault Emulator

equipment
Preparted by: No Fault Found Project Team

www.through-life-engineering-services.org

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Document History
Version
1

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Author
Samir Khan

Comments
Initial release by Cranfield University

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Tests carried out on the Intermittent Fault Emulator

Dates: 04/08/14
Reliability evaluation involves the study of failures and errors. The destructive nature of
a hard faults and long error latencies make it difficult to identify the causes of failures in
the operational environment. It is particularly hard to recreate a fault scenario for a
intermittent faults in systems.
To identify and understand potential failures, Copernicus Technology Ltd is using an
experiment-based approach for emulate faults signals. Such an approach can be applied
not only during the conception and design phases, but also during the prototype and
operational phases.
Within the experiment-based approach, consideration is given to the characteristic of
faults which could range from being intermittent to regular, with varying sizes and
behavioural patterns. Such specific mechanisms (or tools) can be used to inject faults,
create failures or errors, and monitor their effects on components.
Test plan CTL-229-01-TP2 (See Appendix A for full details)
The plan comprised of 10 design requirements:
1. Connection with avionics diagnostic equipment-under-test
2. 256 outputs emulating the LRUs
3. Ability to modify data bus/nodal configuration
4. Generation of fault patterns within 15 minutes
5. Specify the number of faults generation within a particular duration
6. Fault generation on Individual channel
7. Control fault behaviour on Individual conductive paths
8. Selection of Individual fault duration
9. Ability to produce a burst of faults
10. Ability to generation at least four bursts
Figure 1 illustrates the fault emulation environment, which consists of a power supply, a
PC, the fault emulator, and the output analyzer.

Figure 1. The basic components of the fault emulation environment

The power supply inputs the voltage required to produce the fault which passes through
the fault emulator system. Here, depending on the pattern set out by the designer, the
emulator will execute the commands to produce the behavioural pattern. This pattern is
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produced offline; on a separate computer system which can support various types of
faults lengths and (at the moment) five states. The output can be monitored by any data
analysis device.
The software: Most of the specifications in the plan are closely associated to the
software that has been designed to produce the fault pattern. Upon testing, it was able to
produce the expected output behaviours on various paths, timed bursts, and timely
pattern generation.
The software GUI and the user interaction allow the ability to create random faults,
single faults and to import/export fault profiles. The interface is simple and can be
carried out with minimal training.
The hardware: the experimental setup of the fault emulation can be seen in Figure 2.

Figure 2. The Intermittent fault emulation setup

The output results were tested using the following two test equipment:
1. Digital storage oscilloscope PDS8202T
2. Digital Multimeter 34410A Agilent
3. PicoScope 3205 MSO
Both test equipment seem to pickup the emulated faults and match the initial
specification expressed to the test personnel. The oscilloscope and PicoScope were also
able to capture more details and compare the size of the fault. This coincided with the
pattern specified in the software program.

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Figures 3, 4 and5 demonstrates the outputs captured using the picoscope. When
describing the output voltage, the rise time is taken from a 10% and 90% of the step
height. This is appropriate for the current application.

Figure 3. Burst of faults being picked up by the picoscope

Figure 4. Burst slowed down

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Figure 5. A 100ns trigger

During testing, it was noted that other channels within the same segment were being
influenced by secondary effects of the triggered channel. Details of the modifications
that followed and results are attached in Appendix B. Reducing the logic voltage to
around 4.4V seems to have reduced the noise to an acceptable level. Further noise
reduction on the channels can be achieved by reducing the power source for the
switching devices.

Figure 6. A 2.5uS fault and the noise appearing on nearby channels.

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Proposed software recommendations:

1. Ability to produce varied amplitude sizes
2. Generation of random faults according to a probability distribution
3. Pictorial generation of the fault patterns
Proposed hardware recommendations:
1. Rigorous testing on other test equipment available in the market
2. Generation of internal power input signal
3. Momentary intermittent fault patterns may suffer from some induction coupling
effects/energy from near by conductive paths. Use of FPGAs may overcome this
issue.

Conclusion
The emulator is able to meet the requirements of the test plan (CTL-229-01-TP2) provided to
the group.

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APPENDIX A
TEST PLAN: CTL-229-01-TP2 IFE Functionality & Performance

See attached document

APPENDIX B
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IFE Event Secondary Effect Checks and Corrective Action

Introduction
During Test Plan 2, it was found that there were secondary effects on the IFE channels
during a commanded trigger. In certain conditions an un-commanded trigger would
appear on a channel within a segment that was having a commanded channel being
triggered. The un-commanded trigger was found to be completely in phase with the
commanded trigger but was only around 400ns compared with say a 2us
commanded trigger. It was also found that the un-commanded triggers were on all 7
of the other channels within the 8-channel segment that was being legitimately
triggered. However, it was found that there was complete segment separation with
no un-commanded triggers in the other 7 segments from a commanded trigger
regardless of the duration or type of the commanded trigger. During investigations it
was found that within a triggered segment, the un-commanded channels were
experiencing levels of signal input on the ADG451 pins 1,16,9,8 at approx
800milliVolts, which at these levels should not cause the LC2MOS logic to trigger.

From the datasheet for the ADG451 the isolation and crosstalk at the frequencies of operation for the IFE suggest that
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there should not be any issues on channel separate within the device or indeed out
with the device.
However, despite this, the noise was causing un-commanded triggers.

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Modifications to the IFE were trialled to see if the noise within the segment could be
reduced while a segments channel was being triggered. This included reducing the
pull-down resistors to 10kOhms and adding capacitance to the input lines of 22pF
(the latter was due to the fact that the un-commanded effects significantly reduced
when probing the device which in turn has a capacitance effect). However, during the
in-depth investigation it was found that the logic voltage being supplied to IFE PCB
was a little high at 5.19v; in reducing this voltage to a more acceptable level of 5v,
the effect on the input was that it reduced significantly the trigger noise on the inputs
to ADG451, and that in some cases the spurious un-commanded triggers
disappeared. Despite a great deal of trial modifications carried out, it seemed that
the most effective solution was to reduce the logic voltage VL input to the trigger
switches (ADG451).
This following test process was broken down into 9 steps and was designed to
determine the levels of VL that would eliminate the un-commanded triggers within
the segment, firmware effects and noise limits, and all without affecting overall
performance of IFE.

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Step 1 - Action

Result

Firmware switching all command lines at once

Event set as 2s on channel 15 (Blue)
Secondary channel monitoring channel 16 (Red)
Test circuits stimulated voltage set to 5V across 68
Power supply VL input 5.14V

Fail 800ns event observed on

secondary channel

Step 2 - Action

Result

All as Step 1
Power supply VL input 4.29V

Pass - with noise max 490mV

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Step 3 - Action

Result

Step 2 repeated with same environment but with a

variance on the IFE input voltage to ascertain the cut off
limits.
Power supply VL input 4.40V

Pass - with noise

Power supply VL input 4.50V

Fail

Power supply VL input 4.45V

Fail

Power supply VL input 4.42V

Pass - with noise

Power supply VL input 4.35V

Pass - with noise

Power supply VL input 4.20V

Pass - with noise

Power supply VL input 4.00V

Pass - with noise

Step 3 showed that with VL reduced to below 4.35v that the un-commanded triggers
were eliminated. A Key Performance Check (KPC)1 was carried out at this stage could
still be carried out without any effect in performance; this was confirmed as a PASS.

The Key Performance Check consisted of commanded triggers at 100ns, 2us and 4us on 2
channels within each segment while monitoring a channel within the same segment. Traces
of the triggered channel and the monitored channel for each duration were taken and
analysed for performance derogation and un-commanded triggers.
1

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Step 4 - Action

Result

All as per Step 1 but:

Power supply VL input 4.45V
Firmware using sequential command switching2

Pass - with noise

Power supply VL input 4.50V

Pass - with noise

Power supply VL input 4.60V

Fail

Power supply VL input 4.55V

Pass - with noise

Power supply VL input 4.57V

Pass - with noise

Power supply VL input 4.58V

Pass - with noise

Power supply VL input 4.59V

Pass - with noise

Power supply VL input 4.60V

Fail

Power supply VL input 4.40V

Pass - with noise

Power supply VL input 4.00V

Pass - with noise

Step 4 showed that VL tolerance could be increased by over 0.2v with a pass.
However, while the noise profile reduced a little in amplitude, and did not cause uncommanded triggers, the noise profile increase in size.

Noise levels were seen to be at their highest when commanding all 4 commanded input
lines on the ADG451. Firmware was altered to reduce the noise by sequencing the command
lines.
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Step 5 - Action

Result

Test Circuit stimulated voltage set to 3.20V

Pass - with noise (same level as

above)

Test Circuit stimulated voltage set to 1.60V

Pass - with noise (same level as

above)

Step 5 was introduced to see if the simulated voltage was having an adverse effect on
the noise being generated on the input to ADG451. It was concluded that the test
circuit stimulated voltage had no effect on the noise being generated, and that the
noise is likely to be as a result of circuitry between the ADG451 and ADG714
components.

Step 6 - Action

Result

Test Circuit stimulated voltage set to 5.0V

Power supply VL input 4.40V
Channel 16 Triggered
Firmware at simultaneous command switching

Pass - with noise (preamble noise

reduced)

Step 6 showed that with the firmware back to commanding all the command lines
simultaneously, and VL reduced to a 4.40v that un-commanded triggers are
eliminated and that the noise profile significantly reduced.

Step 7 - Action

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Result

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As Step 6 but the secondary channels monitored 14,

13, 12, 11, 10, 9, 8, 32, 33, 65, 49, 48

Pass - with noise (same level as

above)

Step 7 was to see if the noise levels on the channel outputs reduced across the
segment and other segments on the IFE PCB. It was concluded that the noise was a
result of the trigger and this was having an effect on the power supply levels and
causing a ripple on all channel regardless of the segment.

Step 8 - Action

Result

Replace load resistor changed to 39

Pass - with noise (same level as

above)

Step 8 was to ensure that the load on the channel did not have an effect on the noise
on un-commanded channels. It was concluded that the load had no effect.

Step 8 - Action

Result

Load resistor changed back to 68

Pass - with noise (same level as
Test Circuit stimulated voltage set to 5.0V
above)
Power supply VL input 4.40V
Firmware set to simultaneous triggering of cmd-lines
Triggered event at 100ns

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Step 9 shows that performance is not degraded and that the fastest trigger profile
can be attained, without any un-commanded triggers on channels within the same
segment.
Conclusion
Overall it was found that reducing VL was the most effective solution to eliminating
un-commanded triggers within the segment. Modifications to circuit design did have
an effect but overall without significantly more investigation and possibly
modification to the IFE PCB, hardware changes at this stage are neither cost/time
effective. However, if the noise levels need to be reduced more for any reason, then
it would be recommended that more investigation into circuit design, especially
between ADG451 and ADG714 is carried out.
The recommendation for a solution for the un-commanded triggers within a segment
is to reduce VL to 4.35v.

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Disclaimer:
All the analysis and conclusions shown in this report are based on the information
collected during the meetings and interviews carried out with the organisation.

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