Circuitos Digitales

Compuertas Lgicas
Bsicas
Prof. Ing. Oscar Casimiro

F.I.E.E

UNMSM

Sem. 2011-I
Facultad de Ingeniera Electrnica
y Elctrica - FIEE

Summary
The Inverter

The inverter performs the Boolean NOT operation. When the

input is LOW, the output is HIGH; when the input is HIGH,
the output is LOW.
Input

Output

A
X
LOW (0) HIGH (1)
HIGH (1) LOW(0)

The NOT operation (complement) is shown with an overbar.

Thus, the Boolean expression for an inverter is X = A.
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Summary
The Inverter

Example waveforms:
A
X
A group of inverters can be used to form the 1s complement
of a binary number:
Binary number

UNMSM

1
0
0
1s complement

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Summary
The AND Gate

A
B

&

The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is
Inputs Output
A

0
0
1
1

0
1
0
1

0
0
0
1

The AND operation is usually shown with a dot between the

variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB.
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Summary
The AND Gate

A
B

A
B

&

Example waveforms:
A
B
X
The AND operation is used in computer programming as a
selective mask. If you want to retain certain bits of a binary
number but reset the other bits to 0, you could set a mask with
1s in the position of the retained bits.
If the binary number 10100011 is ANDed with
the mask 00001111, what is the result? 00000011
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Summary
The AND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count down mode. XLA1 is a logic analyzer with the
output of the AND gate connected to first (upper) line of the
analyzer. What signal do you expect to on this line?

The output (line 1) will be

HIGH only when all of the
inputs are HIGH.

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Summary
The OR Gate

A
B

A
B

The OR gate produces a HIGH output if any input is HIGH;

if all inputs are LOW, the output is LOW. For a 2-input gate,
the truth table is
Inputs Output
A

0
0
1
1

0
1
0
1

0
1
1
1

The OR operation is shown with a plus sign (+) between the

variables. Thus, the OR operation is written as X = A + B.
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Summary
The OR Gate

A
B

A
B

Example waveforms:
A
B
X
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.
ASCII letters have a 1 in the bit 5 position for lower case letters
and a 0 in this position for capitals. (Bit positions are numbered
from right to left starting with 0.) What will be the result if you
OR an ASCII letter with the 8-bit mask 00100000?
The resulting letter will be lower case.
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Summary
The OR Gate
A Multisim circuit is shown. XWG1 is a word generator set
to count down. XLA1 is a logic analyzer with the output
connected to first (top) line of the analyzer. The three 2-input OR gates act
as a single 4-input gate. What signal do you expect on the output line?
The output (line 1) will be
HIGH if any input is HIGH;
otherwise it will be LOW.

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Summary
The NAND Gate

&

The NAND gate produces a LOW output when all inputs

are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is
Inputs Output
A

0
0
1
1

0
1
0
1

1
1
1
0

The NAND operation is shown with a dot between the

variables and an overbar covering them. Thus, the NAND
operation is written as X = A .B (Alternatively, X = AB.)
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Summary
The NAND Gate

A
B

&

Example waveforms:
A
B
X
The NAND gate is particularly useful because it is a
universal gate all other basic gates can be constructed
from NAND gates.
How would you connect a 2-input NAND gate
to form a basic inverter?
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Summary
The NAND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count up mode. A four-channel oscilloscope monitors the
inputs and output. What output signal do you expect to see?

The output (channel D) will be

LOW only when all of the
inputs are HIGH.

Inputs

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Summary
The NOR Gate

A
B

A
B

The NOR gate produces a LOW output if any input is

HIGH; if all inputs are HIGH, the output is LOW. For a
2-input gate, the truth table is
Inputs

Output

0
0
1
1

0
1
0
1

1
0
0
0

The NOR operation is shown with a plus sign (+) between

the variables and an overbar covering them. Thus, the NOR
operation is written as X = A + B.
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Summary
The NOR Gate

A
B

A
B

Example waveforms:
A
B
X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V

When is the LED is ON for the circuit shown?

The LED will be on when any of
the four inputs are HIGH.
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A
B
C
D

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330

Summary
The XOR Gate

A
B

A
B

=1

The XOR gate produces a HIGH output only when both

inputs are at opposite logic levels. The truth table is
Inputs

Output

0
0
1
1

0
1
0
1

0
1
1
0

The XOR operation is written as X = AB + AB.

Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.
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Summary
The XOR Gate

A
B

A
B

=1

Example waveforms:
A
B
X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?
There is no change in the output.

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Summary
The XNOR Gate

A
B

A
B

=1

The XNOR gate produces a HIGH output only when both

inputs are at the same logic level. The truth table is
Inputs

Output

0
0
1
1

0
1
0
1

1
0
0
1

The XNOR operation shown as X = AB + AB. Alternatively,

the XNOR operation can be shown with a circled dot
between the variables. Thus, it can be shown as X = A . B.
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Summary
The XNOR Gate

A
B

A
B

=1

Example waveforms:
A
B
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
If the A waveform is inverted but B remains the same, how is
the output affected?
The output will be inverted.

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Summary
Fixed Function Logic
Two major fixed function logic families are TTL and CMOS.
A third technology is BiCMOS, which combines the first
two. Packaging for fixed function logic is shown.
0.335 0.334 in.
14 13 12 11 10

0.740 0.770 in.

14 13 12 11 10 9

0.228 0.244 in.

7
1

Pin no.1
identifiers

0.250 0.010 in.

1

Lead no.1
identifier

14
1

14
1

DIP package

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SOIC package

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Summary
Fixed Function Logic
Some common gate configurations are shown.
VCC

VCC

14 13 12 11 10 9

7
GND

VCC

14 13 12 11 10 9

'00

7
GND

7
GND

14 13 12 11 10 9

7
GND

14 13 12 11 10 9

'27

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7
GND

7
GND

'30

7
GND

7
GND

7
GND

14 13 12 11 10 9

7
GND

'21
VCC

14 13 12 11 10

VCC

14 13 12 11 10

'08

VCC

14 13 12 11 10 9

14 13 12 11 10 9

'20

VCC

'11

VCC

VCC

'10

'04

VCC

14 13 12 11 10 9

VCC

14 13 12 11 10

' 02

VCC

'32

7
GND

14 13 12 11 10 9

'86

Facultad de Ingeniera Electrnica y Elctrica - FIEE

7
GND

Summary
Fixed Function Logic
Logic symbols show the gates and associated pin numbers.
VCC
(14)
(1)

(3)

(2)
(4)

(6)

(5)
(9)

(8)

(10)
(12)

(11)

(13)

(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)

&

(3)
(6)
(8)
(11)

(7)
GND

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Facultad de Ingeniera Electrnica y Elctrica - FIEE

Summary
Fixed Function Logic
Data sheets include limits and conditions set by the
manufacturer as well as DC and AC characteristics. For
example, some maximum ratings for a 74HC00A are:
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
0.5 to + 7.0 V
V
V in
DC InputVoltage (Referenced to GND)
0.5 to VCC +0.5 V V
V out DC Output Voltage (Referenced to GND)
0.5 to VCC +0.5 V V
I in
DC Input Current, per pin
20
mA
Iout
DC Output Current, per pin
25
mA
ICC
DC Supply Current, VCC and GND pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
750
mW
500
SOIC Package
TSSOP Package
450
Tstg
Storage Temperature
65 to + 150
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
C
260
Plastic DIP, SOIC, or TSSOP Package
300
Ceramic DIP
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Summary
Programmable Logic
A Programmable Logic Device (PLD) can be programmed
to implement logic. There are various technologies
available for PLDs. Many use an internal array of AND
gates to form logic terms. Many PLDs can be programmed
multiple times.
A
A
B
B

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SRAM
cell

SRAM
cell

SRAM
cell

SRAM
cell

SRAM
cell

SRAM
cell

SRAM
cell

SRAM
cell

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X = AB

Summary
Programmable Logic
In general, the required logic for a PLD is developed with
the aid of a computer. The logic can be entered using a
Hardware Description Language (HDL) such as VHDL.
Logic can be specified to the HDL as a text file, a
schematic diagram, or a state diagram.
A text entry for a programming a PLD in VHDL as a 2-input
NAND gate is shown for reference in the following slide. In
this case, the inputs and outputs are first specified. Then the
signals are described. Although you are probably not familiar
with VHDL, you can see that the program is simple to read.

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Summary
Programmable Logic
entity NandGate is
port(A, B: in bit;
LED: out bit);
end entity NandGate;
architecture GateBehavior of NandGate is
signal A, B: bit;
begin
X <= A nand B;
LED <= X;
end architecture GateBehavior;
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Selected Key Terms

Inverter A logic circuit that inverts or complements its
inputs.
Truth table A table showing the inputs and corresponding
output(s) of a logic circuit.
Timing A diagram of waveforms showing the proper time
diagram relationship of all of the waveforms.
Boolean The mathematics of logic circuits.
algebra
AND gate A logic gate that produces a HIGH output only
when all of its inputs are HIGH.
Glossary FIEE - 2010

Selected Key Terms

OR gate A logic gate that produces a HIGH output when
one or more inputs are HIGH.
NAND gate A logic gate that produces a LOW output only
when all of its inputs are HIGH.
NOR gate A logic gate that produces a LOW output when one
or more inputs are HIGH.
Exclusive-OR A logic gate that produces a HIGH output only
gate when its two inputs are at opposite levels.
Exclusive-NOR A logic gate that produces a LOW output only
gate when its two inputs are at opposite levels.
Glossary FIEE - 2010