Singulani IPFA 2013 Final

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Stress Evolution on Tungsten Thin-Film of an Open Through Silicon Via Technology

Anderson P. Singulania,b , Hajdin Cerica,b , and Erasmus Langerb .


a

Institute for Microelectronics, TU Wien


Christian Doppler Laboratory for Reliability Issues in Microelectronics
at Institute for Microelectronics Vienna, Austria
Guhausstrae, 27-29
Tel.: +43 1 58801-36027 / FAX.: +43-1-58801-36099
{singulani|ceric|[email protected]}

We have studied the stress evolution of the Tungsten film of a particular open TSV technology during a processing thermal cycle.
The work describes a simulation scheme that conjugates a thin-film model for stress with the traditional mechanical finite element
method approach, resulting in a good agreement with experimental data.
Category: Advanced interconnects and BEOL reliability and Failure
Mechanisms.
Preferred presentation mode: Oral

Corresponding Author:
Anderson Singulani [email protected]
Tel.: +43 1 58801-36027

I.
INT RODUCT ION
We investigated in this work an open TSV technology for
3D integration based on Tungsten, which was presented for the
first time in 2010 [1]. Since then several papers have been
published about its mechanical [2-4] and electrical properties
[2] and, so far, the structure has proved itself reliable and
stable. But the stress development on metal layer remains
unclear and such description is necessary to predict failure
scenarios. Furthermore, direct measurement of the stress in this
TSV is rather challenging and during device processing some
plasticity on the thin-film metal layer (Tungsten) is expected
due to the temperature variations as high as 500C. Our goal is
to provide means to comprehend the deformat ion in the
tungsten layer of this open TSV technology and to evaluate its
impact on device mechanical stability during processing.
Therefore, we propose in this work a simu lation scheme based
on Finite Element Method (FEM ) to model the vias metal
plasticity and to understand the stress behavior.
II. PROBLEM DESCRIPT ION
The presented integration technology uses wafer bonding
and TSVs in order to integrate low output sensors with their
associated analog amplification and s ignal processing circuitry
(Fig. 1). Metallization and SiO2 passivation are deposited
conformally on the TSV surfaces following the Si etch process.
More processing details can be found in the work of J. Kraft et
al. [4].
C. Krauss et al. performed X-Ray Diffraction (XRD) stress
measurements on the metal layers of this structure [3], but the
probe into tungsten is troublesome due to the via cylindrical
geometry (Fig. 2a). Then, a full p late sample with an identical
layer profile is used to support stress characterization (Fig. 2b).
Our strategy is to establish, from those measurements on the
full plate, a FEM model that can be used for evaluating the
stress on TSVs metal during processing.
Krauss put the sample in a thermal cycle up to 500C on a
rate of 1C/ min and recorded the measured stress for each step.
We inferred fro m those data also fro m other experiences on
thin-film modeling [5-7] that the stress behavior can be
exp lained by the dislocation glide mechanism on low temperature plasticity according to the equation 1[5].
[

)]

(1)

Where is the stress on the thin-film, M f is the biaxial


modulus of the material, the difference between the
coefficients of thermal expansion of the film and the substrate,
TR the temperature rate, s the Schmid factor, F is the
activation energy and is the critical shear stress. To obtain the
parameters values, we fitted the experimental data with
equation 1 (Fig. 3) using a meta-heuristically technique known
as Genetic Algorithm (GA). The obtained values are in table I.
T able I Dislocation glide parameter

We set two thermo-mechanical FEM simu lations, one for


the full-p late sample and another for the TSV itself. For both,
the equation 1 describes only the tungsten deformation while
the remaining materials are considered under a thermo-elastic
approach. The purpose of the full-plate simulation is to validate
the coupling between the plastic and thermo-elastic model, and
also the parameters from table I. The experience acquired
through it regarding assumptions, numerical issues, meshing ,
and physical interpretation is then carried over to the TSV
simulation.
III.

SIMULAT ION SET UP

The full plate simulation was set with symmetric boundary


conditions, with the purpose to obtain the configuration as
close as possible fro m a measurement targeted on the sample
center. The initial stress on tungsten was taken from the
experimental data. The computed stress evolution follows very
closely the measured values and it is only slightly different
fro m the GA fitted curve (Fig. 4). Such deviation can be
justified by the elastic influence of the oxide and the silicon on
the metal. This result supports our decision to adopt the model
of equation 1, the parameter values obtained from the fitting
process (table I), and finally, the coupling scheme between
plastic and thermo-elastic models in the FEM simulation.
To simulate the TSV, an axisy mmetric condition was
assumed. The stress evolution in the TSV top has a distinct
behavior for the two different in-plane directions, unlike the
full plate case (Fig. 5). We reason that the thermal stress on the
cylindrical-shape TSV superposes the expected stress
evolution, leading to a fast decline on phi-direction and a quasiconstant progression on z-direction. Hence, the Von Mises
stress has an assorted behavior, following the stress in z for the
heating branch and the stress in phi for the cooling, moreover
the Von Mises magnitude never surpass the initial value, which
can be used as estimation for the maximu m stress during the
thermal cycle.
IV. CONCLUSION
In this paper we investigated the stress development on the
metal layer of an open TSV during a thermal cycle. We
established a methodology to include low-temperature plastic
deformation by dislocation glide in a FEM simulation.
Additionally, we provided means to obtain the model
parameters and determined them for the tungsten. The
simulated results are compatible with the experiments and
support our approach to the problem. The stress on TSV
follows a particular evolution due to the influence of the
geometry deformation under temperature variation. The Von
Mises stress development was exposed and the use of the initial
value as maximu m estimat ion was advised based on the
simulated results. This information is vital for the proper
evaluation of mechanical stability on the device.
A CKNOWLEDGMENT

Parameters
Mf (GPa)

F (J)

(GPa)

555.85

2.8592e-19

0.2119

1.9655

We would like to thanks Sara Carn iello fro m AMS A.G.,


and Christopher Krauss and his colleagues on IM2NP for the
measurement data and fruitful discussions . This work was
partly supported by the European Union project COCOA.

Figure 4 Stress evolution on the T ungsten according to the FEM


simulation. Slightly difference to the fitted curve is due to the influence of the
elastic behavior of the oxide and silicon on the structure.
Figure 1 - Schematic cross section of the open TSV technology used in this
work.

Figure 5 Stress development on the T SV. T he original tendency for stress


decline on z-direction is contra balanced by the increase stress due to the
thermal expansion, creating a plateau on the elastic region (0-400C). On the
other hand, on phi-direction the stress decline is reinforced, creating a fast
decrease (almost elastic) in this direction.

REFERENCES
Figure 2 (A) T SV sample (B) Full plate sample. Cylindrical geometry
prevents the XRD measurement to reach regions deeper than 10m from the
top. A full plate sample with same composition and layer thickness is used as
an alternative for the measurement.

[1]

[2]

[3]

[4]

[5]

[6]
Figure 3 Fitting result using Genetic Algorithm. T he differential form of
the equation 1 hinders a more traditional approach (derivative based methods),
thus meta-heuristically methods is an appropriate choice considering computing
cost and result quality.

[7]

J. Kraft, F. Schrank, J. T eva, J. Siegert, G. Koppitsch, C. Cassidy et al,


3D Sensor application with open through silicon via technology, IEEE
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