DDR Basics Frescale

July, 2009
DDR Basics, Register Configurations &

Pitfalls
Mazyar Razzaz,
Applications Engineer
TM
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or
service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.
Agenda
Basic
DDR SDRAM
Memory Organization & Operation

Read and write timing
Power
Features & Capabilities
Power
QUICC DDR Controllers
Initialization & Register Configurations
Power
Pitfalls / Debug Tips
Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks
of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.
TM
Basic DDR SDRAM

Memory Organization & Operation
TM
Single Transistor Memory Cell
Column (bit) line

Row (word) line
1 => Vcc
0 => Gnd
D
precharged to Vcc/2
Cbit
Ccol
Vcc/2
TM
Column (bit) line

Row (word) line
1 => Vcc
0 => Gnd
precharged to Vcc/2
Cbit
Storage
Capacitor
Ccol
Vcc/2
TM

Access
Transistor
Row (word) line
1 => Vcc
0 => Gnd
D
precharged to Vcc/2
Cbit
Storage
Capacitor
Column (bit) line
Ccol
Vcc/2
TM

Access
Transistor
Row (word) line
1 => Vcc
0 => Gnd
D
precharged to Vcc/2
Cbit
Storage
Capacitor
Column (bit) line
Ccol
Parasitic Line
Capacitance
Vcc/2
TM
Memory Arrays
ROW ADDRESS DECODER
B0
B1
B2
B3
B4
B5
B6
B7
W0
W1
W2
SENSE AMPS & WRITE DRIVERS

COLUMN ADDRESS DECODER
TM
Memory Arrays
B0
B1
B2
B3
B4
B5
B6
B7
ROW ADDRESS DECODER
W0
W1
W2

TM
Memory Arrays
B0
B1
B2
B3
B4
B5
B6
B7
ROW ADDRESS DECODER
W0
W1
W2

TM
10
Internal Memory Banks

Multiple
Multiple
arrays organized into banks

banks per memory device
DDR1 4 banks, 2 bank address (BA) bits

DDR2 & DDR3 4 or 8 banks, 2 or 3 bank address (BA) bits
Can have one active row in each bank at any given time
Concurrency
Can be opening or precharging a row in one bank while accessing another bank
May
be referred to as internal, logical or sub- banks

Bank 0
Bank 1
Bank 2
Bank 3
Row 0
Row 1
Row 2
Row 3
Row
Row
Buffers
TM
11
Memory Access
Bank 0
requested row is ACTIVATED

and made accessible through
the banks row buffer.
Row
Row
Row
Row
Row
Bank 1
Bank 2
Bank 3
0
1
2
3
Row
Buffers
and/or WRITE are

issued to the active row.
READs
Row
Row
Row
Row
Row
0
1
2
3
Row
Buffers
The
row is PRECHARGED and

is no longer accessible through
the banks row buffer.
Row
Row
Row
Row
Row
0
1
2
3
Row
Buffers
TM
12
Example DDR2 SDRAM

Infineon
HYB18T256800AF or
Micron MT47H32M8
32M
x 8 (8M x 8 x 4 banks)
256 Mb total
13-bit row address
8K rows
10-bit column address
1K bits/row (8K total when you take
into account the x8 width)
2-bit bank address
TM
13
Example DDR2 DIMM

Infineon
HYS72T3200HU or
Micron MT9HTF3272A
/CSn
ODTn
32M x 8
A[12:0]
DQ[7:0]
BA[1:0]
DQS
/DQS
/RAS
MDQ[0:7], MDQS0, MDM0

DM
/CAS
/WE
each 32M x 8 memory

devices
32M x 72 overall
256 MB total
Single rank
9 byte lanes
MDQ[24:31 MDQS3, MDM3

CKE
CK
/CK

ODT
/CS
32M x 8
A[12:0]
DQ[7:0]
BA[1:0]
DQS
/DQS
/RAS
ECC[0:7], MDQS8, MDM8
DM
/CAS
/WE
CKE
CK
/CK
ODT
/CS
TM
14
DDR1/DDR2/DDR3 Basic Command Summary
Command
/CS
/RAS
/CAS
/WE
ADDR
NOP
NOP
ACTIVE
BA, Row
READ
BA, Col
WRITE
BA, Col
PRECHARGE
BA
PRECHARGE ALL
A[10]
REFRESH
LOAD MODE REGISTER
Bank,
OpCode
TM
15
DDR2-533 Read Timing Example

Mem Clk
Tck = 3.75 ns
READ
ACTIVE
Trcd (ACTTORW ) = 4 clk
READ
Tccd = 2 clk
PRECHARGE
Trtp (RD_TO_PRE) = 2 clk
Trp (PRETOACT) = 4 clk
/CS
/RAS
/CAS
/WE
Address
BA, ROW
BA, COL
BA, COL
BA
CASLAT = 4 clk
DQS
DQ
D0
D1
D2
D3
D0
D1
D2
D3
TM
16
DDR2-533 Write Timing Example

Mem Clk
Tck = 3.75 ns
ACTIVE
PRECHARGE
WRITE
Trcd (ACTTORW ) = 4 clk
/CS
/RAS
/CAS
/WE
Address
BA, ROW
BA, COL
BA
WR_LAT = CASL + AL -1 = 3 clk
Twr (WRREC) = 4 clk
DQS
DQ
D0
D1
D2
D3
DM
TM
17
DDR1/DDR2/DDR3 Comparison
Feature
DDR1
DDR2
DDR3
Package
TSOP
BGA only
BGA only
Voltages
2.5V Core, 2.5V I/O
1.8V Core, 1.8V I/O
1.5V Core, 1.5V I/O
Densities
64Mb-1Gb
256Mb-4Gb
256Mb-8Gb
Internal Banks
4 or 8
Prefetch (min WRITE burst)
266-400 Mbps
400800 Mbps
8001600 Mbps
2, 2.5, 3 Clk
3, 4, 5 + AL Clk
5, 6, 7+ AL Clk
READ Latency - 1
CAS write Latancy
SSTL_2
SSTL_18
SSTL_15
Termination
Parallel termination to
VTT for all signals
On-die for data group.

VTT termination for
address, command, and
control
On-die termination
for data, address,
command, and
control
Data Strobes
Single Ended
Single or Differential
Differential
Data Rate
CAS / READ Latency
WRITE Latency
I/O Signaling
TM
18
PowerQUICC DDR Controllers

Features & Capabilities
TM
19
DDR1/DDR2/DDR3 Controller Features & Capabilities

Supports
most JEDEC standard x8, x16, x32 DDR1 & 2 & 3 devices
Memory device densities from 64Mb through 4Gb
Data rates up to: 333 Mb/s for DDR1, 800 Mb/s for DDR2 and DDR3
Devices with 12-16 row address bits, 8-11 column address bits, 2-3
logical bank address bits
Data mask signals for sub-doubleword writes
Up to four physical banks (chip selects)
Physical bank sizes up to 4GB, total memory up to 16GB per
controller
Physical bank interleaving between 2 or 4 chip selects
Memory controller interleaving when more than 2 controllers are
available
Unbuffered or registered DIMMs
TM
20
DDR1/DDR2/DDR3 Controller Features & Capabilities (cont.)

Up
to 32 open pages
Open row table

Amount of time rows stay open is programmable
Auto-precharge,
globally or by chip select
Self-refresh
Up
to 8 posted refreshes
Automatic or software controlled memory device initialization
ECC: 1-bit error correction, 2-bit error detection, detection of all
errors within a nibble
ECC error injection
Read-modify-write for sub-doubleword writes when using ECC
Automatic data initialization for ECC
Dynamic power management
TM
21
DDR2/DDR3 Controller additional Features & Capabilities

Partial
array self refresh

Address & command parity for Registered DIMM
Independent driver impedance setting for data, address/command,
and clock
Mirrored DIMM supported
Automatic CPO (operational)
Write-leveling for DDR3
Automatic ZQ calibration for DDR3
Fixed or On-the-fly Burst chop mode for DDR3
Asynchronous RESET for DDR3
TM
22
Fly By Routing Topology

Introduction
of Fly-by architecture
Address, command, control & clocks

Improved signal integrityenabling higher speeds
On module termination
Matched tree routing of clk command and ctrl
DDR2 DIMM
Controller
Fly by routing of clk, command and ctrl
DDR3 DIMM
VTT
Controller
TM
23
Fly By Routing Improved SI
DDR2 Matched tree routing
DDR3 Fly by routing
TM
24
What is write leveling

During a write cycle, the skew between the clock and strobes are
increased with the fly-by topology. The write leveling will delay the strobe
(and the corresponding data lane) for each byte lane to
reduce/compensate for this delay.
TM
25
Read Adjustment
Automatic CAS to preamble
calibration
Data strobe to data skew
adjustment
Address,
Command
& Clock Bus
Freescale
Chip
Data Lanes
Instead of JEDECs MPR method, Freescale controllers use a proprietary method of read
adjust method. Auto CPO will provide the expected arrival time of preamble for each strobe line
of each byte lane during the read cycle to adjust for the delays cased by the fly-by topology.
TM
26
Write Adjustment
Write leveling used to add delay
to each strobe/data line.
Address,
Command
& Clock Bus
Freescale
Chip
Data Lanes
Write leveling sequence during the initialization process will determine the
appropriate delays to each strobe/data byte lane and add this delay for every write
cycle.
TM
27

Initialization and Register Configurations
TM
28
DDR3 Initialization Flow

Power-up
DRAMs
Initialized
Mode Register
Commands Issued
DDR3s
Conduct
Precharge
ZQ
Calibration
ZQCL Issued (512 clocks)

Also DLL lock time is occurring
Chip selects
enabled and
DDR clocks
begin
Write
Leveling
CKE = HIGH
Read
Adjust
Asserted at
least 200us
DDR
Reset
Need at
least 500us
from reset
deassertion
to the
controller
being
enabled.
Timed loop
may be
needed.
DDR
CTRL
INIT
Stable
CLKS
Controller
Started
MEM_EN =1
Automatically handled
By the controller
Automatic CAS-to-Preamble
(aka Read Leveling).
Plus Data-to-Strobe adjustment
Init
Complete
Ready for User accesses
TM
29
DDR2 Initialization Flow

Power-up
DDR
CTRL
INIT
Chip selects
enabled and
DDR clocks
begin
Stable
CLKS
CKE = HIGH
Issued by controller
DRAMs
Initialized
Mode Registers Programmed

Issued by controller
Read
DQStDLL
Adjust Wait
Adjust
tDLL = 512 clocks
Read
Init
DQS
Calibration
Complete
Adjust
200 us
Controller
Started
Precharge
All
Ready for User accesses
MEM_EN =1
TM
30
Register configuration
Two
general type of registers to be configured in the memory

controller
First register type are set to the DRAM related parameter values,
that are provided via SPD or DRAM datasheet
Second register type are the Non-SPD values that are set based on
customers application. For example:
On-die-termination (ODT) settings for DRAM and controller

Driver impedance setting for DRAM and controller
Clock adjust, write data delay, Cast to Preamble Override (CPO)
2T or 3T timing
Burst type selection (fixed or on-fly burst chop mode)
Write-leveling start value (WRLVL_START)
TM
31
What Can We Adjust to Optimize the Timing?

1)
CLK_ADJUST
2) WR_DATA_DELAY
3) CPO
4) 2T_EN, 3T_EN
5) WRLVL_EN
6) Burst chop mode
TM
32
CLK_ADJUST & WR_DATA_DELAY

Internal Clock
MemClk (CLK_ADJUST = 0)
CLK_ADJUST = 1/2
MemClk (CLK_ADJUST = 1/2)
Cmd/Addr Bus
WRITE
WR_LAT = (CASL + AL -1 ) = 3
DQS (WR_DATA_DELAY = 0)
DQ (WR_DATA_DELAY = 0)
Tdqss = 1/4 cycle
WR_DATA_DELAY = 1/2
DQS (WR_DATA_DELAY = 1/2)

DQ (WR_DATA_DELAY = 1/2)
TM
33
Pitfalls / Debug Tips - Clock Adjust

Addr/Cmd
are always launched from the same location, memory clock is

shifted with DDR_SDRAM_CLK_CNTL[CLK_ADJUST]
Used to meet setup/hold for Addr/Cmd
Use
eye.
a scope to verify that clock is centered inside of the Addr/Cmd valid
Look at heavily loaded signal (/RAS, /CAS, /WE, Addr, BA)

Look at lightly loaded signal (/CS, ODT, CKE)
TM
34
Eye Diagrams
TM
35
Eye Diagrams
TM
36
Eye Diagrams
TM
37
Eye Diagrams
TM
38
Eye Diagrams
TM
39
Pitfalls / Debug Tips Write Data Delay

Controlled
Used
to meet tDQSS timing requirements
In addition to compensating for CLK_ADJUST setting
Verify
via TIMING_CFG_2[WR_DATA_DELAY]
using a scope
Must be measured after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] has

been optimized
Erroneous
values may cause failures on writes to DRAM
TM
40
Pitfalls / Debug Tips - CAS to Preamble

Set
Use
via TIMING_CFG_2[CPO]
application note AN2583 section 4.2 to calculate
Must
be calculated after DDR_SDRAM_CLK_CNTL[CLK_ADJUST]

has been optimized
Use the center value if more than one valid CPO available.
TM
41
2T/3T Timing
Puts
Addr/Cmd signals on the bus for 2 or 3 clock cycles instead of 1

Does not affect Control signals
When
to use?
Two dual-rank unbuffered DIMMs

36 loads on Addr/Cmd lines
Typically
not required for:
One dual-rank unbuffered DIMM

18 loads on Addr/Cmd lines
When
not to use?
Registered DIMMs
TM
42

Pitfalls / Debug Tips
TM
43
Pitfalls / Debug Tips - DDR Type POR Configuration
TM
44
Pitfalls / Debug Tips - ECC and DDR Error Registers

ECC
should be enabled if possible
DDR_SDRAM_CFG[ECC_EN] enables ECC

DDR_SDRAM_CFG_2[D_INIT] initializes data and ECC in DRAM
If ECC cannot be enabled, it may be more difficult to detect DDR
generated errors
ERR_DETECT
register should be checked for DDR errors
ACE Automatic calibration error

MBE Multi-bit ECC error
SBE Single-bit ECC error
MSE Memory select error
TM
45
Pitfalls / Debug Tips - CAS Latency / Write Latency / Additive Latency

Program
write latency based on DRAM type
DDR1 -> Write latency = 1 DRAM cycle

DDR2 -> Write latency = (Read latency 1) DRAM cycles
DDR3 -> Write latency = CWL
Programming
CAS latency too high can degrade performance
Check DRAM datasheet based on frequency used and specific DRAM

device
When
ODT is used, other rules must be followed to allow ODT to

assert early enough
DDR2: Write latency + additive latency >= 3 cycles
DDR3: TIMING_CFG_5 [WODT_ON], [WODT_OFF] = WL-1 cycles for
fixed or fly-by burst chop
TM
46
Pitfalls / Debug Tips - DDR Mode Registers

Values
programmed into DDR mode registers must match DDR

controller configuration registers
CAS latency
Burst length
Write recovery
Not a straight decode in Mode Register
Active powerdown exit time

Additive latency
Differential DQS enable
DLL
reset and OCD calibration fields are controlled automatically by

the DDR controller
TM
47
*Pitfalls / Debug Tips - Programming twtr, trrd, and trtp

Use
caution when calculating:
TIMING_CFG_1[WRTORD] (twtr)
TIMING_CFG_1[ACTTOACT] (trrd)
TIMING_CFG_2[RD_TO_PRE] (trtp)
DDR2: Minimum value for each parameter is 2 DRAM clocks

DDR3: Minimum value for each parameter is 4 DRAM clocks
TM
48
Pitfalls / Debug Tips - 200 us Delay

200
s for DDR2 and 512 us for DDR3 must pass between stable
clocks and CKE assertion
Clocks
are stable after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is

programmed and any chip select has been enabled via
CSn_CONFIG[CS_n_EN]
CKE
is asserted after DDR_SDRAM_CFG[MEM_EN] is set
Software
must provide delay between these 2 steps
TM
49
References
TM
50
Useful References
Books:
DRAM Circuit Design: A Tutorial, Brent Keeth and R. Jacob Baker, IEEE Press, 2001
Freescale AppNotes:
AN2582 Hardware and Layout Design Considerations for DDR Memory Interfaces
AN2910 Hardware and Layout Design Considerations for DDR2 Memory Interfaces
AN2583 Programming the PowerQUICC III / PowerQUICC II Pro DDR SDRAM Controller
AN3369 PowerQUICC DDR2 SDRAM Controller Register Setting Considerations
Micron AppNotes:
TN-46-05 General DDR SDRAM Functionality
TN-47-02 DDR2 Offers New Features and Functionality
TN-41-02 DDR3 ZQ calibration
JEDEC
Specs:
JESD79E Double Data Rate (DDR) SDRAM Specification

JESD79-2B DDR2 SDRAM Specification
JESD79-3A DDR3 SDRAM Specification
TM
51
Q&A
Thank
you for attending this presentation. Well now take a few

moments for the audiences questions and then well begin the
question and answer session.
TM
52
TM

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What are the basic components of a DDR SDRAM memory cell?

What are the basic components of a DDR SDRAM memory cell?

How does a DDR SDRAM memory cell store a bit of data?

How does a DDR SDRAM memory cell store a bit of data?

July, 2009

DDR Basics, Register Configurations &

Memory Organization & Operation

Features & Capabilities

QUICC DDR Controllers

Initialization & Register Configurations

QUICC DDR Controllers

QUICC DDR Controllers

Pitfalls / Debug Tips

Basic DDR SDRAM

Single Transistor Memory Cell

Column (bit) line

Single Transistor Memory Cell

Column (bit) line

Single Transistor Memory Cell

Row (word) line

Column (bit) line

Single Transistor Memory Cell

Row (word) line

Column (bit) line

ROW ADDRESS DECODER

SENSE AMPS & WRITE DRIVERS

ROW ADDRESS DECODER

SENSE AMPS & WRITE DRIVERS

ROW ADDRESS DECODER

SENSE AMPS & WRITE DRIVERS

Internal Memory Banks

arrays organized into banks

DDR1 4 banks, 2 bank address (BA) bits

be referred to as internal, logical or sub- banks

requested row is ACTIVATED

and/or WRITE are

row is PRECHARGED and

Example DDR2 SDRAM

Example DDR2 DIMM

MDQ[0:7], MDQS0, MDM0

MDQ[16:23], MDQS2, MDM2

each 32M x 8 memory

MDQ[24:31 MDQS3, MDM3

MDQ[40:47], MDQS5, MDM5

MDQ[56:31], MDQS7, MDM7

ECC[0:7], MDQS8, MDM8

DDR1/DDR2/DDR3 Basic Command Summary

LOAD MODE REGISTER

DDR2-533 Read Timing Example

Trtp (RD_TO_PRE) = 2 clk

Trp (PRETOACT) = 4 clk

DDR2-533 Write Timing Example

WR_LAT = CASL + AL -1 = 3 clk

Twr (WRREC) = 4 clk

2.5V Core, 2.5V I/O

1.8V Core, 1.8V I/O

1.5V Core, 1.5V I/O

Prefetch (min WRITE burst)

CAS write Latancy

On-die for data group.