Bulit in Self Test
Bulit in Self Test
BIST II
CMPE 646
Test Set L
CUT
LFSR
X4
X3
X2
P(X)=X4+X+1
1
N=4
L=5
k=4
U M B C
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AR
TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
E1
1
0
0
0
1
E2
0
1
1
1
1
E3
0
1
0
1
1
E4
0
0
1
0
0
Parity
1
0
0
0
1
YLAND BA
L
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AR
TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
M3
M2
M4
This scheme is equivalent k single input SAs but with the input stream
shifted in time, M(X) = M0(X) + XM1(X) + ... + XkMk(X).
The error polynomial of the four outputs is E(X) = E1(X) + XE2(X) + X2E3(X) +
X3E4(X), which is divided by the P(X) yeilding a remainder of X3 + X + 1.
1000
0110
Error Responses
LFSR
0101
0110
1110
10100110
Note that the aliasing probability of the MISR is still 2-N for an N-stage SA.
When the number of outputs, k, of the CUT is > N, parity/MUX can be used.
YLAND BA
L
U M B C
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RE COUNT
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IVERSITY O
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AR
TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
Fault Coverage
PR tests generated according to previous methods are usually long and result
in unacceptable fault coverage:
FC
100%
Test pattern
U M B C
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TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
More 1s
U M B C
MO
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Y
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TI
1966
More 0s
UMBC
000111
xx1011
xx1011
010000
100000
6 patterns (of 32 exhaustive patterns) give 100%
Note 1s and 0s do not occur uniformly.
5
(12/11/06)
BIST II
CMPE 646
U M B C
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UN
RE COUNT
Y
IVERSITY O
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AR
TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
BIST Architectures
The LFSR and SA can be on-chip or off-chip, and as indicated, logic BIST typically combines PR testing with scan and boundry-scan.
L
F
S
R
PIs
Run BIST
M
I
S
R
CUT
Test Control
ROM
POs
Signature
compared
Autonomous Test
LFSR
Subcircuit
G1
M
U
X
M
U
X
MUX
Subcircuit
G2
MUX
MISR
YLAND BA
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Y
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AR
TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
BIST Architectures
Circular BIST: For register-based architectures, self-test shift registers(STSR).
STSR
Dj
STSR
Combo
Sj-1
Combo
0
1
N/T
Z
STSR
N/T
0 Dj
1 Si-1 + Dj
Combo
FF
FF
Combo
Combo
STSR
STSR
SE
D Q
Qj
Sj
R
Mode
Normal
Test
Three phases to the test: Initialization: all STSR and FFs. Test mode: all STSR
act as LFSR and MISR. Response Eval: STSRs are compared with fault-free
value.
YLAND BA
L
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Y
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AR
TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
BIST Architectures
BILBO (Built-In Logic Blocks Observer): BIST + Scan Path.
Combines TPG and response compression in a single unit (designed for busoriented systems).
It uses existing FFs on-chip for PR TPG and SA.
out1
out2
outn
C1
C2
Scan-in
D Q
D Q
scan/LFSR
C1 and C2 configure as a shift register for scan (00), an LFSR (00), MISR (10)
a Normal (11).
YLAND BA
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TI
1966
UMBC
(12/11/06)
BIST II
CMPE 646
BIST Architectures
BILBO test senario:
Reg 1
LFSR
Combo-1
Combo-1
Reg 2
BILBO
Combo-2
Combo-2
Reg 3
MISR
Normal
Test mode
Each combo block is tested one at a time. For testing Combo-1, Reg 1 configured as PRTPG (LFSR) and Reg 2 configured as MISR.
So testing Combo-1 involves configuring BILBO as a MISR.
Afterwards, testing Combo-2 involves configuring BILBO as an LFSR.
YLAND BA
L
U M B C
MO
UN
RE COUNT
Y
IVERSITY O
F
AR
TI
1966
UMBC
10
(12/11/06)
BIST II
CMPE 646
BIST Architectures
Random Test Socket: Combines scan and BIST.
All PIs are connected to the taps of LFSR #1 and all POs to the MISR.
FFs are scannable and form a Shift Register (SR).
SI is driven by LFSR #2 while SO is connected to the SSA.
PO
MISR
CUT
SI
SR
Clk
SO
SE
Test Controller
SSA
LFSR #2
LFSR #1
PI
Called "test per scan" instead of "test per clk" since shifting is necessary.
Note, LFSR 1 and 2 can be combined as well as the MISR and SSA.
Adv: low-cost ATPG, Disadv: overhead and long test times.
YLAND BA
L
U M B C
MO
UN
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Y
IVERSITY O
F
AR
TI
1966
UMBC
11
(12/11/06)
BIST II
CMPE 646
BIST Architectures
STUMPS: Self-Test Using MISR and Parallel Shift reg. sequence generator.
Originally proposed to reduce overhead of LFSR/MISR for application
to testing multi-chip boards, each of which has only the SRs.
Can also be used on a single chip with multiple scan chains.
Combo logic
not shown
Parallel LFSR
XOR Cloud
SO1
SO3
MISR
SI4
SR4
SO2
SI3
SR3
SI2
SR2
SR1
SI1
Parallel LFSR
SO4
In order to break linear dependency,
Phase shifters (XOR gates) added.
U M B C
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UN
RE COUNT
Y
IVERSITY O
F
AR
TI
1966
UMBC
12
(12/11/06)