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Bulit in Self Test

The document discusses various techniques for built-in self-test (BIST) architectures, including space compaction methods for handling multiple outputs, handling random pattern resistant faults, and different BIST circuit implementations. Specific techniques described include multiplexing outputs, Bellmac signature analysis, parallel signature analysis, weighted pseudorandom pattern generation, and architectures using linear feedback shift registers (LFSRs), multiple input signature registers (MISRs), and scan chains like BILBO, random test sockets, and STUMPS.

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Rao
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48 views12 pages

Bulit in Self Test

The document discusses various techniques for built-in self-test (BIST) architectures, including space compaction methods for handling multiple outputs, handling random pattern resistant faults, and different BIST circuit implementations. Specific techniques described include multiplexing outputs, Bellmac signature analysis, parallel signature analysis, weighted pseudorandom pattern generation, and architectures using linear feedback shift registers (LFSRs), multiple input signature registers (MISRs), and scan chains like BILBO, random test sockets, and STUMPS.

Uploaded by

Rao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Design Verification and Test

BIST II

CMPE 646

Space Compaction Multiple Outputs


We need to treat the general case of a k-output circuit.

Test Set L

CUT

LFSR

There are several possibilities:


Multiplex the k outputs of the CUT.
M1
M2
M3
M4

X4

X3

X2

P(X)=X4+X+1
1
N=4
L=5
k=4

The multiplexer compacts the responses of each PO one at a time.


k times slower but the 2-N aliasing probability is reduced when multiple
POs are tested independently.
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VLSI Design Verification and Test

BIST II

CMPE 646

Space Compaction Multiple Outputs


Bellmac uses both parity and signature analysis compaction.
M1
M(X) = M1+M2+M3+M4
M2
LFSR
M3
M4
parity tree

For example, given the error responses:


Patterns
T1
T2
T3
T4
T5

E1
1
0
0
0
1

E2
0
1
1
1
1

E3
0
1
0
1
1

E4
0
0
1
0
0

Parity
1
0
0
0
1

The "parity" polynomial, X4 + 1, is then feed to the LFSR, which is divided by


P(X) = X4 + X + 1.
This yields a remainder of R(X) = X.

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VLSI Design Verification and Test

BIST II

CMPE 646

Space Compaction Multiple Outputs


Parallel Signature Analysis (Multiple Input Signature Register or MISR).
M1

M3

M2

M4

This scheme is equivalent k single input SAs but with the input stream
shifted in time, M(X) = M0(X) + XM1(X) + ... + XkMk(X).
The error polynomial of the four outputs is E(X) = E1(X) + XE2(X) + X2E3(X) +
X3E4(X), which is divided by the P(X) yeilding a remainder of X3 + X + 1.
1000
0110
Error Responses
LFSR
0101
0110
1110
10100110
Note that the aliasing probability of the MISR is still 2-N for an N-stage SA.
When the number of outputs, k, of the CUT is > N, parity/MUX can be used.
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VLSI Design Verification and Test

BIST II

CMPE 646

Random Pattern Resistant Faults


The effectiveness of any test can be measured by:
Its fault coverage
Its length
Its hardware requirements
Its data storage requirements

Fault Coverage

PR tests generated according to previous methods are usually long and result
in unacceptable fault coverage:
FC
100%

100 200 300 400 500 600 700 800

Test pattern

Saturation follows the rapid increase in fault coverage.


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VLSI Design Verification and Test

BIST II

CMPE 646

Random Pattern Resistant Faults


FC represents the hard-to-detect faults by random patterns (RPR).
The fault coverage can be improved by reducing the aliasing probability.
However, the main source of difficulty is that some faults are detected by
only a couple, possibly one, patterns.
The root of the problem: Under PR pattern generation, all FFs have equal probability of generating a 1 or 0.
However, detection probabilities for faults in gates do not follow this distribution, e.g., only 1 pattern detects an SA0 on an input to a 6-input NOR.
1101
1011
0111

More 1s

Minimal SAF tests


0010
0100
1000
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More 0s

UMBC

000111
xx1011
xx1011
010000
100000
6 patterns (of 32 exhaustive patterns) give 100%
Note 1s and 0s do not occur uniformly.
5

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VLSI Design Verification and Test

BIST II

CMPE 646

Random Pattern Resistant Faults


Weighted PR TPG assigns weights to the PIs, the probability that 1 should be
assigned to a PI.
Weight assignment can be based on circuit structure analysis or fault
detection probabilities.
Although coverage is improved, there are still hard-to-detect faults.
This results from fan-out, e.g., an input common to the AND and OR
gate is assigned a weight that favors one over the other.
Multiple weights is a solution but adds hardware.
Other solutions: test point insertion, reseeding the LFSR and multiple polynomial LFSRs add hardware, impact performance and/or require long tests.
Mixed-mode approach uses deterministic patterns stored in ROM or via bitfixing/flipping from LFSR patterns for RPR faults.
No good solutions, deterministic patterns are typically applied via scan path.
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VLSI Design Verification and Test

BIST II

CMPE 646

BIST Architectures
The LFSR and SA can be on-chip or off-chip, and as indicated, logic BIST typically combines PR testing with scan and boundry-scan.
L
F
S
R

PIs

Run BIST

M
I
S
R

CUT

Test Control

ROM

POs

Signature
compared

Autonomous Test
LFSR
Subcircuit
G1

M
U
X

M
U
X

MUX

Subcircuit
G2
MUX

Circuit is partitioned using


MUXs or sensitization method.
Each is tested independently
using the same LFSR and MISR.

MISR
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VLSI Design Verification and Test

BIST II

CMPE 646

BIST Architectures
Circular BIST: For register-based architectures, self-test shift registers(STSR).
STSR

Dj

STSR

Combo

Sj-1

Combo

0
1
N/T
Z

STSR

N/T
0 Dj
1 Si-1 + Dj

Combo
FF

FF

Combo

Combo

STSR

STSR

SE
D Q

Qj
Sj

R
Mode
Normal
Test

Text shows another version.


MISR using all STSR has
characteristic polynomial 1 + XN

Three phases to the test: Initialization: all STSR and FFs. Test mode: all STSR
act as LFSR and MISR. Response Eval: STSRs are compared with fault-free
value.
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VLSI Design Verification and Test

BIST II

CMPE 646

BIST Architectures
BILBO (Built-In Logic Blocks Observer): BIST + Scan Path.
Combines TPG and response compression in a single unit (designed for busoriented systems).
It uses existing FFs on-chip for PR TPG and SA.
out1
out2
outn
C1
C2
Scan-in

D Q

D Q

scan/LFSR

C1 and C2 configure as a shift register for scan (00), an LFSR (00), MISR (10)
a Normal (11).
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VLSI Design Verification and Test

BIST II

CMPE 646

BIST Architectures
BILBO test senario:
Reg 1

LFSR

Combo-1

Combo-1

Reg 2

BILBO

Combo-2

Combo-2

Reg 3

MISR

Normal

Test mode

MISR for Combo-1 test

LFSR for Combo-2 test

Each combo block is tested one at a time. For testing Combo-1, Reg 1 configured as PRTPG (LFSR) and Reg 2 configured as MISR.
So testing Combo-1 involves configuring BILBO as a MISR.
Afterwards, testing Combo-2 involves configuring BILBO as an LFSR.

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10

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VLSI Design Verification and Test

BIST II

CMPE 646

BIST Architectures
Random Test Socket: Combines scan and BIST.
All PIs are connected to the taps of LFSR #1 and all POs to the MISR.
FFs are scannable and form a Shift Register (SR).
SI is driven by LFSR #2 while SO is connected to the SSA.
PO
MISR

CUT

SI
SR
Clk

1) Load SR with pattern from LFSR #2

SO
SE

Test Controller

2) Apply pattern using LFSR #1 to PIs.


3) Clock to latch response in SRs.
4) Capture results in MISR (SE = 0).
5) Scan out SR into SSA.

SSA

LFSR #2

LFSR #1

PI

(Steps 1 and 5 can be overlapped).

Called "test per scan" instead of "test per clk" since shifting is necessary.
Note, LFSR 1 and 2 can be combined as well as the MISR and SSA.
Adv: low-cost ATPG, Disadv: overhead and long test times.
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11

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VLSI Design Verification and Test

BIST II

CMPE 646

BIST Architectures
STUMPS: Self-Test Using MISR and Parallel Shift reg. sequence generator.
Originally proposed to reduce overhead of LFSR/MISR for application
to testing multi-chip boards, each of which has only the SRs.
Can also be used on a single chip with multiple scan chains.
Combo logic
not shown

Parallel LFSR

SRs loaded using a


Shift Reg Sequence Generator (SRSG)

XOR Cloud

SO1

SO3
MISR

SI4
SR4

SO2

SI3
SR3

SI2
SR2

SR1

SI1

Parallel LFSR

SO4
In order to break linear dependency,
Phase shifters (XOR gates) added.

Inputs to all scan chains provided by multiple-output LFSR.


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