TESTPAPER I

Duration : 30 min

Marks : 25
Q1 to Q5 carry one mark each

1.

If one of the input to an ______ gate is inverted then it becomes an INHIBITOR.

(A) AND

2.

(B) NAND

4.

(B) A

(C) 0

(D) 1

Which one of the following is equivalent to OR-AND realization?

(A) NAND-NOR realization

(B) NAND-NAND realization

(C) NOR-NOR realization

(D) None of these

Which of the following gates is a series circuit gate?

(A) AND gate

5.

(D) XOR

[(A + AB)(A + AB)][(CD + CD) + (C D)] =

(A) B

3.

(C) NOR

(B) OR gate

(C) XOR gate

(D) XNOR gate

(C) 13

(D) None of these

The maxterm designator of the term, with D as MSB

A + B + C + D is
(A) 10

(B) 05

Q6 to Q13 carry two mark each

6.

7.

The Boolean expression for shaded area in the Venn diagram is

(A) (x + y) + xyz

(B) x + z + (x + y + z)

(C) (x + z) + (x + y + z)

(D) (x + y) + (x + y + z)

The floating point binary number is given as

S

10010001

10001110001000000000000

Find the binary value of given number.

8.

9.

(A) 1100011000110000000

(B) -1100011000110000000

(C) -110001110001000000

(D) 1100011100010000000

For the following K-map, POS form equation is

(A) M(1, 3, 4, 6, 9, 11, 12, 14)

(B) M(0, 2, 5, 7, 8, 10, 11, 15)

(C) M(1, 3, 4, 7, 8, 10, 11, 15)

(D) M(0, 2, 4, 7, 9, 11, 12, 14)

How many minimum NAND gates are required to implement following Boolean function?
y = (A + B) (A + C)
(A) 5

10.

(D) 8

(B) NAND

(C) XOR

(D) XNOR

(C) A + B

(D) B + C

Simplify this expression AB + (B + C)A + B(B + C)

(A) B + AC

12.

(C) 7

(NOR).(XOR).(NAND) =
(A) NOR

11.

(B) 6

(B) A + BC

The single-precision floating point binary number of the binary no. 111111011100000 is

13.

(A)

10001101

11111011100000000000000

(B)

10001001

11111101110000000000000

(C)

10110101

11111011100100000000000

(D)

11001010

11011001110010000000000

A = x y z + x y z + x y z + x y z To implement the above Boolean expression, minimum no. of gates required

are
(A) 1

(B) 2

(C) 3

(D) 4

Q14(a) to Q14(b) carry two mark each

Linked Answer Questions
14(a).The 10s complement of a no. is (47480)10 Find the no. in decimal equivalent.
(A) 525320

(B) 37480

(C) 47380

(D) 63620

(C) (134570)8

(D) None of these

14(b).The octal equivalent of the answer of part a is

(A) (146450)8

(B) (131450)8

TESTPAPER II
Duration : 30 min

Marks : 25
Q1 to Q5 carry one mark each

1.

Each gate in the circuit below has t PLH = 4ns and tPHL = 4ns. If a positive going pulse is applied to the input, how
long will it take the output pulse to appear?
(A) 16 ns

2.

(B) 8 ns
(B) 63%

5.

(C) 25%

(D) 50%

(C) PMOS

(D) CMOS

Which of the following logic family has maximum fan-in?

(A) TTL

4.

(D) 2 ns

Propagation delay is the time taken between ________ of peak points on the input and output transistors.
(A) 37%

3.

(C) 4 ns

(B) DTL

The main advantages of TTL with totem pole output as compared to other TTL is
(A) higher fan-in and higher fan-out

(B) higher noise margin and low cost

(C) fast switching and low power dissipation

(D) None of these

In high-speed TTL, basic problem is

(A) increase in power dissipation

(B) increase in propagation delay

(C) high speed power product

(D) none of these

Q6 to Q13 carry two marks each

6.

Statement 1: Totem pole outputs of TTL can be connected together.

Statement 2: Level shifting circuits are not required for interfacing between ECL and TTL
(A) 1-True; 2-True

7.

(B) 1-False; 2-False

(D) 1-False; 2-True

Determine the maximum value of pull up resistance for an open collector TTL gate to active a fan out of 10
given that IOH = 40mA. The leakage current flowing through the collector of TTL output transistor is 50 mA and
VOH(min) = 2.4V
(A) 11.11 k

8.

(C) 1-True; 2-False

(B) 11.11

(C) 3.5 k

(D) 5.8 k

Consider the transmission gate of fig. below. The control voltage is V(0) = -5V and V(1) = +5V. A sinusoid of
peak voltage 5V is applied at the input. Given that VT = 0V.
The entire sinusoid will get through the gate if,
(A) C = V(0)

9.

(B) C = V(1)

(D) None of these

For the CMOS circuit, determine the output for inputs of 1V and 9V, Given |V T| = 2.3V
(A) 2V; 8V

10.

(C) C = VT

(B) 1V; 9V

(C) 0V; 10V

Match the following

Output type

Function

(1) totem-pole output

(a) makes possible wired-AND connection

(2) open-collector output

(b) decreases speed-power product

(3) tri-state output

(c) suitable for bus operation

(d) increases noise immunity

(A) d

(D) 10V; 0V

11.

(B) b

(C) a

(D) a

State whether if the following statements are true.

(i) The n-channel MOS gates usually employ positive logic
(ii) The p-channel MOS gates usually employ negative logic
(A) (i)-True, (ii)-False

12.

(B) (i)-False, (ii)-True

(C) (i)-True, (ii)-True

(D) (i)-False,(ii)-False

Consider the following statements.

S1 : ECL circuits generate noise spikes during state transitions.
S2 : CMOS switching speed increases with operating frequency and decreases with supply voltage.
Choose the correct options using the codes given below:-

13.

(A) S1 True, S2 True

(B) S1 True, S2 False

(C) S1 False, S2 True

(D) S1 False, S2 False

Whenever new information is entered in a memory location previous data is erased. This happens in _____
(A) RAM

(B) CAM

(C) SAM

(D) Both(A) and (B)

Q14(a) & (b) carry two marks each

Linked Answer Questions
14(a).For low power schottkey TTL, the parameters and their values are specified. Calculate the propagation delay,
power dissipation, and the fan out.
Parameter

Value

VCC

5V

ICH

1.6 mA

ICL

2.8 mA

Voll (min)

2.7 V

VoL (min)

0.4V

ViH (max)

2.0V

ViL (max)

0.8V

IoH (max)

4.0mA

IoL (max)

8.0mA

IiH (max)

0.02mA

IiL(max)

0.4mA

TPLH

10 ns

TPHL

10 ns

(A) 10 ns, 2.75 mW, 20

(B) 10 s, 2.75 W, 10

(C) 20 ns, 11 mW, 10

14(b).For the above calculate the figure of merit and noise margin high and low.
(A) 27.5 mW/ns, 0.4V, 0.7V

(B) 27.5 mW/ns, 1.1V, 0.4V

(C) 27.5 mW/ns, 0.7V, 0.4V

(D) 27.5 mW/ns, 1.1V, 0.7V

(D) 20 s, 11W, 20

TESTPAPER III
Duration : 30 min

Marks : 25
Q1 to Q5 carry one mark each

1.

2.

In three-bit subtractor, the difference is _____ where x, y, z are inputs of the subtractor.
(A) D = x y z + x y z + x y z + x y z

(B) D = x y z + x y z + x y z + x y z

(C) D = x y z + x y z + x y z + x y z

(D) None of these

The final step in designing the combinational circuit is

(A) to draw the truth table
(B) to minimize the Boolean function for each output obtained
(C) to determine the input and output variables
(D) to draw the minimized logic diagram

3.

For a 4-variable K-map, the total number of logic expression that can be obtained are
(A) 3

4.

(C) 216

(B) 16

Match List-I with List-II and select the correct answer by using codes given below.
List I

5.

(D) 8

List II

(a)

Multiplexer

1.

Sequential memory

(b)

De-Multiplexer

2.

Converts decimal number of binary

(c)

Encoder

3.

Data selector

4.

Routes out many data output with single

input.

(A) a 2, b 1, c 4

(B) a 1, b 2, c - 3

(C) a - 4, b 3, c 1

(D) a 3, b 4, c 2

A combinational circuit is one in which the output depends on the

(A) input combination and the previous output
(B) present output and the previous output
(C) input combination at that time
(D) input combination at that time and the previous input combination.
Q6 to Q13 carry two mark each

6.

To implement Full adder using 8 : 1 MUX, the no. of 8 : 1 MUX required are
(A) 1

7.

(C) 3

(D) 4

Borrow (B) of full subtractor is represented by following logic function, where X is MSB input bit and Z is LSB
input bit.
(A) (X Y)Z+XY

8.

(B) 2

(B) Y(X Y)Z+XY

(C) Y(X Y)Z+XY

(D) (X Y)Z+XY

Consider the following logic diagram,

To represent above logic diagram using NAND gates only, how many minimum NAND gates are required?
(Assuming both inverted / non inverted inputs are available)
(A) 3

(B) 4

(C) 5

(D) 6

9.

Draw the k-map for the following equations f = f1 + f2

f1 = (A B)C
f2 = (A e B)C

10.

11.

12.

(A)

(B)

(C)

(D)

The logic circuit shown converts y1 y2 into

(A) Gray code

(B) excess-3 code

(C) BCD

(D) Error detecting code

The following K-map implement

(A) BCD to Decimal Decoder

(B) Decimal to BCD Encoder

(C) 1 of 10 Decoder

(D) Choice (A) and (C) both

The circuit shown in figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with
Z = RQ + PR+ QP

The circuit acts as a

13.

(A) 4 bit adder giving P + Q

(B) 4 bit subtractor giving P Q

(C) 4 bit subtractor giving Q P

(D) 4 bit adder giving P + Q + R

The circuit given in figure is to be used to implement the function Z = f(A, B) = A + B

What values should be selected for I and J?
(A) I = 0, J = B

(B) I = 1, J = B

(C) I = B, J = 1

(D) I = B , J = 0

Q14(a) & (b) carry two marks each

Linked answer Questions
The figure shows a 2-decade BCD to binary converter.
14(a).The output of IC1 for an input of 29 will be,
(A) 01111

(B) 1011101

(C) 0010101

(D) 0011111

(C) 0010101

(D) 0011111

14(b).For the above part(a), the full binary output is,

(A) 0011101

(B) 1011101

TESTPAPER IV
Duration : 30 min

Marks : 25
Q1 to Q5 carry one mark each

1.

For a divide by 4 counter, the present input P is equal to _____

(A) 16

2.

(D) 4

(B) JQ + KQ

(C) JQ + KQ

(D) JQ + KQ

(C) Master-slave J-K F/F

(D) T F/F

D flip flop is formed by combining the inputs of

(A) J-K F/F

4.

(C) 8

The characteristic equation for J-K flip flop is

(A) JQ + KQ

3.

(B) 12

(B) S-R flip flop

Consider the following diagram

For the proper functioning of F/F, the present and clear inputs must be
(A) logic 0

5.

(B) logic 1

(C) not connected

(D) tied together

The output of D-F/F depends upon

(A) the data available on D input line

(B) clock signal

(C) State of input line on the triggering edge of clock

(D) none of the above

Q6 to Q13 carry two marks each

6.

Suppose propagation delay time of flip flop is 0.2 nsec and it is followed by 2 decoders with a propagation delay
time of 0.1 nsec each.
The time required for data input to settle before the triggering edge of clock is 2 nsec and the time for which
data remains stable is just 1 nsec. Then maximum operating frequency of flip flop will be _____
(A) 294 MHz

7.

(B) 400 MHz

(C) 450 MHz

(D) 434 MHz

Statement 1: Synchronous counter is less likely to end up in erroneous state than asynchronous counter.
Statement 2: Synchronous counter consumes less power than asynchronous counter.
Choose the correct option:

8.

(A) 1 True, 2-True

(B) 1 True, 2 False

(C) 1 False, 2 True

(D) 1 False, 2 False

Practically Flip-Flops can be designed using

(1) NAND gates

(2) NOR gates

(3) AND-OR gates

(4) AND-NOT gates

Choose the correct option :

(A) 1 True, 2 True, 3 True, 4 - True
(B) 1 True, 2 False, 3 False, 4 True
(C) 1 False, 2 True, 3 True, 4 False
(D) 1 True, 2 True, 3 False, 4 False
9.

10.

In clocked SR flip-flop, if clock is not present at the instant S = 0 and R = 1, then

(A) Flip-flop will be reset

(B) Flip-flop will have complementary output

(C) Flip-flop will have prohibited input condition

(D) Flip-flop will be in its previous state

Counter shown below is supplied with a constant clock frequency of f c, then output Q0 Q1Q 2 will have frequency
of

(A) fc/3
11.

(B) fc/6

(C) fc/8

(D) Insufficient Data

(C) 5

(D) 4

Following state diagram shows clocked sequential circuit:

How many states the sequential circuit has?
(A) 6

12.

(B) 7

Figure below shows D type Flip-Flops connected as shift register, then outputs Q D, QC, QB, QA are given by:
(i)

0001

0011

(iii) 1 1 1 0

0010

0001

1111

0100

1000

0111

0001

0100

0011

(A) i and ii only

13.

(ii)

(B) ii and iii only

(C) i, ii and iii

(D) None of these

Maximum propagation delay for a synchronous counter and an asynchronous counter, each with 4 flip-flops is
____ and _____ respectively. The propagation delay of one flip-flop is 20 nsec.
(A) 29 nsec, 20 nsec

(B) 20 nsec, 80 nsec

(C) 80 nsec, 80 nsec

(D) 80 nsec, 20 nsec

Q14(a) & (b) carry two marks each

Linked Answer Questions
14(a).How many flip-flops are required to build a binary counter circuit to count from 0 to 2048?
(A) 10

(B) 9

(C) 11

(D) 8

14(b).For the above part(a), what is the frequency of the output of last FF for an input clock frequency of 6 MHZ?
(A) 4.883 kHz

(B) 3 kHz

(C) 6 MHz

(D) 5 kHz

TESTPAPER V
Duration : 30 min

Marks : 25
Q1 to Q5 carry one mark each

1.

2.

The magnitude of analog equivalent voltage in R-2R ladder network changes if the converter is operated at very
high frequency, close to maximum operating frequency. The change will be ______
(A) increase in magnitude

(B) decrease in magnitude

(C) constant magnitude

(D) cannot be determined

For a 10-bit resistor divider network, the LSB has a weight of _____
(A) 0.7957 10-3

3.

4.

(C) 0.9775 10-3

(D) None of these

The amount of time required to settle to a particular desired accuracy of a D/A converter is
(A) D/A settling time

(B) D/A speed

(C) D/A monotonicity

(D) D/A oscillation time

For a digital input of 1000, the analog output is 4 mV, then the maximum full scale output voltage for this D/A
converter will be ______
(A) 7.5 mV

5.

(B) 0.56 10-3

(B) 11 mV

(C) 8 mV

(D) 15 mV

Statement 1: In flash A/D converters, the number of comparators decreases with increases in number of bits.
Statement 2: The dual slope A/D converter consists of integrator, comparator and binary counter.
(A) 1-True; 2-True

(B) 1-False; 2-True

(C) 1-True; 2-False

(D) 1-False; 2-False

Q6 to Q13 carry two marks each

6.

In weighted resistor D/A network, which is 4 bit uses 1 k resistor for 2 nd LSB, then the resistor value at MSB
will be_______
(A) 0.1 k

7.

(D) None of these

(B) 10.62ns

(C) 5.31 ns

(D) 5.31 s

(B) 25%

(C) 10%

(D) 5%

(B) 10

(C) 11

(D) 9

For the weighted resistor network shown determine VA, assuming 0 = 0V and 1 = +5V
(A) 50V

12.

(C) 12

What will be the number of bits required at the input of a converter if it is necessary to resolve voltages to 6 mV
and the ladder has +12V full scale?
(A) 8

11.

(B) 11

In the circuit shown, the input bits 0 and 1 are represented by 0 and 5V resp. The OP-amp is ideal, but all the
resistances and the 5V inputs have tolerance of 10%. The specification for the tolerance of DAC is
(A) 35%

10.

(D) None of these

Determine the aperture time for 2 kHz signal using a 4 bit ADC where input sine wave amplitude equals the
maximum input for ADC.
(A) 2.66 s

9.

(C) 1.0 k

How many bits are required at the input of D/A ladder converter so as to get resolution of 2 mV with full scale
output voltage of 5V?
(A) 8

8.

(B) 0.25 k

(B) 3.33V

(C) 6.25V

(D) 5V

Statement 1: The dynamic memories have lower packing density than static memories.
Statement 2: Dark current is the phenomenon related to static memories.
(A) 1-True; 2-True

13.

Match the List-I with List-II

(B) 1-True; 2-False

(C) 1-False; 2-True

(D) 1-False; 2-False

List I

List II

(a)

Flash converter

1.

Requires digital to analog converter

(b)

Dual slope converter

2.

Requires a very complex hardware

(c)

Successive
converter

3.

Minimizes the effect of power supply

interference

4.

It is a tracking A/D converter

(A) a-2; b-3; c-4

approximation

(B) a-4; b-3; c-1

(C) a-3; b-4; c-1

(D) a-4; b-2; c-1

Q14(a) & (b) carry two marks each

Linked Answer Questions
14(a).For a binary weighted D/A converter shown determine R f assuming the output voltage due to offset as -2V
(A) 500

(B) 1000

(C) 1500

(D) 5 kV

14(b).For the above determine the output voltage for the combination shown.
(A) -5.4375V

(B) -0.8125V

(C) -1.4375V

(D) None of the above

TESTPAPER VI
Duration : 30 min

Marks : 25
Q1 to Q5 carry one mark each

1.

2.

In 8085, microprocessor identifies the opcode fetch by

(A)

IO/ M = 0

S0 = 0

S1 = 0

(B)

IO/ M = 0

S0 = 0

S1 = 1

(C)

IO/ M = 0

S0 = 1

S1 = 0

(D)

IO/ M = 0

S0 = 1

S1 = 1

The instruction XCHG exchanges the contents of ____ register pair with the contents of ____ register pair.
(A) BC and DE

3.

(B) BC and HL

(C) DE and HL

(D) PC and HL

After CPI instruction is executed, if carry flag is set and zero flag is reset, then
(A) Data is less than accumulator content
(B) Data is greater than accumulator content
(C) Data is equal to accumulator content
(D) None of the above

4.

5.

In memory mapped I/O of 8085, the space provided by memory and I/O device is
(A) 28 and 216

(B) 216 and 28

(C) 215 and 215

(D) 216 to be shared between memory and I/O

Program counter is also called as memory pointer because

(A) It points to the memory location from where program starts
(B) It points to the memory location where program ends
(C) It points to the memory location of current instruction
(D) It points to the memory location of next instruction
Q6 to Q13 carry two marks each

6.

It is necessary to multiply numbers 0A H by 0B H and store the result in A. The numbers are available in
registers B and C respectively. A part of 8085 program for this purpose is given.
MVI A, 00H
Loop:

_______
_______
_______
HLT
END

The sequence of instructions to complete the program would be

(A)

(C)

7.

JNZ LOOP

(B)

ADDB

ADD B

DCR C

DCR C

JNZ LOOP

DCR C

(D)

ADD B

JNZ LOOP

JNZ LOOP

ADD B

DCR C

In case of CMOS devices, if inputs is allowed to float then

8.

(A) by default it is considered as logic 0

(B) by default it is considered logic 1

(C) IC will get damaged

(D) it will not affect IC operation

After the execution of instruction RIM, the accumulator contains 6DH. Then which of the following statements
is correct?
1. Data is available on SID pin
2. Interrupt enable flip flop is set
3. RST 6.5 and RST 5.5 are masked
4. RST 7.5 is masked
(A) None of above

9.

(B) 2 and 4

(C) 1 only

(D) 1, 2 and 3

Consider the assembly language program

MVI B, 87 H
MOV A, B
START:

JMP NEXT
MVI B, 00H
XRA B
OUT PORT1
HLT

NEXT:

XRA B
JP START
OUT PORT 2
HLT

The execution of the above program will result in

(A) An output of 87H at PORT 1
(B) An output of 87H at PORT 2
(C) Infinite looping of program execution with accumulator data remaining at 00H
(D) Infinite looping of program execution with accumulator data alternating between 00H and 87H
10.

Statement 1: In DAA instruction, if lower nibble of accumulator is greater than 9 or the auxiliary flag is set, then
6 is added to higher nibble.
Statement 2: In DAA instruction, if higher nibble of accumulator is less than 9 or carry flag is set then 6 is added
to higher nibble

11.

(A) 1-True; 2-True

(B) 1-True; 2-False

(C) 1-False; 2-True

(D) 1-False; 2-False

Match the following

Instruction
(i)

Addressing Modes

LDA 2050 H

(a)

direct

(ii) MOV B, A

(b)

indirect

(iii) MOV B, M

(c)

register

ii

iii

(A)

(B)

(C)

(D)

12.

If the operating frequency of 8085 is 2 MHz, find the time required to execute MOV A, M.
(A) 4 s

13.

(B) 3.5 s

(C) 3 s

(D) 4.5 s

(C) 2

(D) 1

The no. of times the loop will be executed is,

LXI

B, 0007 H

LOOP

DCX

MOV

A, B

ORA

JZ

LOOP

(A) 7

(B) 6

Q14(a) & (b) carry two marks each

Common Data Questions:
Consider the following program:
LXI H, 2070H
MVI B, 05H
MVI A, 01H
STORE: MOV M, A
INR A
INX H
DCR B
JNZ STORE
HLT
14(a).Specify the contents of memory location of 2070H after execution of the above program:
(A) 00 H

(B) 01 H

(C) 02 H

(D) 03 H

14(b).Specify the contents of memory location of 2074H after execution of the above program:
(A) 03 H

(B) 04 H

(C) 05 H

(D) 06 H