Leda

DFT Rules Guide

Version J-2014.12
December 2014
Comments?
E-mail your comments about this manual to
[email protected].

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Contents

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How Rules Are Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typographical and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Leda Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Synopsys Web Site . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7
7
7
8
8
8
9
9

Chapter 1
DFT Coding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the DFT Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limitations of DFT Policy with Respect to RTL DRC . . . . . . . . . . . . . . . . . . .
Data Capture Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFT_003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11
11
12
13
14
14

Message: Avoid using both positive-edge and negative-edge triggered flip-flops in your
design

TEST_972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Message: Clock affects both clock and data inputs of flipflops

TEST_973 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Message: Clock affects both clock and data inputs of latches

TEST_974 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Message: Latch enabled by a clock feeds latches enabled by the same clock

TEST_975 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Message: Latch enabled by a clock affects data input of flipflops clocked by the trailing edge
of the same clock

TEST_978 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Message: Latch data gates clocks of flipflops. Combination of latch data and clock signal to
clock a flipflop is not allowed

TEST_979 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Message: Latch data gates clocks enabling latches. Combination of latch data and clock
signal to clock a latch is not allowed

TEST_980 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Message: Flipflop data gates clocks to flipflops. Combination of flipflop data and clock
signal to clock a flipflop is not allowed

Contents

TEST_981 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Message: Flipflop data gates clocks enabling latches. Combination of flipflop data and clock
signal to clock a latch is not allowed

TEST_994 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Message: Clock affects multiple clock or async ports of register

Fault Coverage Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DFT_006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Message: Multiple clocks in the unit

DFT_008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Message: Tri-state is detected

DFT_009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Message: Register all outputs from the block for improved coverage: %s

TEST_960 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Message: Avoid asynchronous feedback loops

TEST_970 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Message: Clock affects data inputs of flipflops

TEST_971 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Message: Clock affects data inputs of latches

TEST_976 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Message: Latches capture only when more than one clock is on

TEST_977 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Message: Flipflops capture only when more than one clock is on

Informational Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DFT_017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Message: Synchronous reset/set/load <%item> detected

DFT_019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Message: Asynchronous reset/set/load <%item> detected

DFT_021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Message: Latch inferred

DFT_022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Message: Incomplete case statement

Scan Insertion Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DFT_002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Message: Internally generated clock detected

TEST_953 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Message: Flipflops with clocks tied to a signal that is not driven by Test Clock. Flipflops'
clock signal is not reached by any Test Clock

TEST_954 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Message: Latches with clocks tied to a signal that is not driven by Test Clock. Latch clock
signal is not reached by any Test Clock

TEST_963 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Message: Flipflops have clocks with no off-state controllability. Test Clock reaches flipflops
but does not control them at beginning of cycle

Contents

TEST_964 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Message: Latches have clocks with no off-state controllability. Test Clock reaches latches
but does not control them at beginning of cycle

TEST_965 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Message: Latches not holding data in off-state. Test Clock reaches latch but does not hold
data in them at beginning of cycle

TEST_966 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Message: Flipflops have no asynch controllability. No Test Asynch reaches flipflop's async
control pin

TEST_967 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Message: Latches have no asynch controllability. No Test Asynch reaches latches async
control pin

TEST_968 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Message: Flipflops have asynchs that cannot be disabled. Test Asynch reaches flipflops but
cannot disable their asynch controls

TEST_969 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Message: Latches have asynchs that cannot be disabled. Test Asynch reaches latches but
cannot disable their asynch controls

Contents

Preface

Preface
About This Manual
This book contains reference information for prepackaged rules that come with the Leda
Checker tool. This information mirrors the information available in the HTML-based
help files that you access directly from the Leda Checker tools Error Report. The
purpose of this book is to provide a reference that you can view online or print out so
that you can review available prepackaged rules and decide which ones you want to use
before running the Checker tool on your HDL source files. On the other hand, the
HTML-based help system is designed to provide random access to this same
information from the Checker Error Report, so that you can quickly access more
information about a specific rule that was violated, including in some cases, circuit
diagrams and valid and invalid examples of Verilog or VHDL code.
This book is intended for use by hardware design and quality assurance engineers who
are already familiar with VHDL or Verilog.

How Rules Are Organized

Rules are organized into major categories called policies, which have multiple rulesets.
Each ruleset can contain multiple rules. You use the prepackaged rules to check your
VHDL or Verilog source code for compliance with various standards and compatibility
with downstream tools in the design and verification flow. Some rules apply just to
Verilog or VHDL and some apply to both HDLs. The documentation for each rule, both
in the HTML-based help system and in this manual clearly labels which languages each
rule applies to.
Note

There is a separate book for each policy (set of prepackaged rules) that Leda
supports.

Preface

Related Documents
This manual is part of the Leda document set. To see a complete listing or to navigate to
another online document in the set, refer to the Leda Document Navigator.

Manual Overview
This manual contains the following chapters and appendixes:
Preface

Describes the manual and lists the typographical

conventions and symbols used in it; explains how to get
technical assistance.

Chapter 1
DFT Coding Rules

Detailed reference information for all rules in the Leda

DFT coding rules policy.

Typographical and Symbol Conventions

The following conventions are used throughout this document:
Table 1: Documentation Conventions
Convention

Description and Example

Represents the UNIX prompt.

Bold

User input (text entered by the user).

% cd $LMC_HOME/hdl

Monospace

System-generated text (prompts, messages, files, reports).

No Mismatches: 66 Vectors processed: 66 Possible"

Italic or Italic

Variables for which you supply a specific value. As a command

line example:
% setenv LMC_HOME prod_dir

In body text:
In the previous example, prod_dir is the directory where your
product must be installed.
| (Vertical rule)

Choice among alternatives, as in the following syntax example:

-effort_level low | medium | high

[ ] (Square brackets)

Enclose optional parameters:

pin1 [pin2 ... pinN]

In this example, you must enter at least one pin name (pin1), but
others are optional ([pin2 pinN]).

Preface

Table 1: Documentation Conventions (Continued)

Convention
TopMenu > SubMenu

Description and Example

Pulldown menu paths, such as:
File > Save As

Getting Leda Help

For help with Leda, send a detailed explanation of the problem, including contact
information, to [email protected].

The Synopsys Web Site

General information about Synopsys and its products is available at this URL:
http://www.synopsys.com

Preface

10

Chapter 1: DFT Coding Rules

1
DFT Coding Rules
Introduction
This chapter provides detailed reference information for the Design For Test (DFT)
policy for the Leda Checker tool. This set of rules checks for test design rule violations
within your RTL-level design. Most of the DFT rules have both flip-flop versions
(check on flip-flop) and latch versions (check on latch). The DFT rules are used to check
for design errors that can prevent scan insertion and data capture or reduce fault
coverage.
Note

There are more DFT rules in the DFT ruleset for the Design policy.
Most of the DFT rules are extracted from the set of rules used by the Synopsys RTL
DRC tool. Therefore, each DFT rule label in the Leda Checker tool exactly matches the
corresponding rule label prefixed with TEST in the RTL DRC tool. If you need more
detailed information on these DFT rules, see the RTL DRC help. Run dc_shell, and at
the prompt type:
% help TEST-rulenumber

For information about differences between the Leda DFT policy and the RTL DRC
checker, see Using the DFT Policy on page 12.
The Leda DFT rules are grouped into the following rulesets, each of which impose
constraints on different aspects of the applicable language:
Data Capture Ruleset on page 14
Fault Coverage Ruleset on page 30
Informational Ruleset on page 42
Scan Insertion Ruleset on page 46

11

Chapter 1: DFT Coding Rules

Using the DFT Policy

Because the Leda DFT rules are based on RTL DRC checks, you must enter some
information about the test clocks when you use some rules of this policy. The Leda
Checker prompts for information about test clocks when you select some DFT rules
among TEST_953, TEST_954, TEST_966, TEST_967, TEST_970, TEST_971,
TEST_972, TEST_973. In batch mode, you must use the following options described in
Table 2.
Table 2: Leda Batch DFT Options
Batch DFT Options

Description

-test_asynch <RST>

This is the same as set_signal_type test_asynch

<RST> in the RTL DRC. This command specifies that
the signal <RST> is active on 1 and has a hold value of
0 during the scan shift phase.

-test_asynch_inverted <RST>

This is the same as set_signal_type

test_asynch_inverted <RST> in the RTL DRC This
command specifies that the signal <RST> is active on
0 and has a hold value of 1 during the scan shift phase.

-test_clk_falling <CLK>

This is the same as create_test_clk <CLK> -w {N1

N1-N2} in the RTL DRC (where N1 and N2 are
positive integers and N 1> N2). This command
specifies the test clock signal <CLK> and states that
the first edge is the falling edge

-test_clk_rising <CLK>

This is the same as create_test_clk <CLK> -w {N1

N1+N2} in the RTL DRC (where N1 and N2 are
positive integers). This specifies the test clock signal
<CLK> and states that the first edge is the rising edge.

Note

In Leda, -test_clk_rising and -test_clk_falling are of the

same functionality, and will be consolidated into one option -test_clk in
the future. Also, -test_asynch and -test_asynch_inverted are
the same functionality, and will be consolidated into one option
-test_asynch in the future.

12

Chapter 1: DFT Coding Rules

Limitations of DFT Policy with Respect to RTL DRC

In Leda's DFT checks, no delay is taken into account; it is always assumed that the test
clock period is 100 ns and the strobe point occurs at 95 ns (default RTL DRC values).
Leda also assumes that all test clock events occur before this strobe point.
The following RTL DRC commands (used to define the test protocol) are ignored by the
Leda Checker tool, since no signal value propagation is performed.
set_test_hold
set_test_initial
set_test_assume
set_test_isolate
The Checker tool also ignores the scan style. Leda only checks rules that are checkable using
the LSSD (Level Sensitive Scan Design). This may lead to some differences between the Leda
tests and the RTL DRC. In general, Ledas tests are more conservative.

13

Chapter 1: DFT Coding Rules

Data Capture Ruleset

The following rules are from the data capture ruleset:

DFT_003
Message: Avoid using both positive-edge and negative-edge
triggered flip-flops in your design
Description

This rule checks whether both rising and falling edge clocks exist
within the design.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Warning

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

14

Chapter 1: DFT Coding Rules

Example
The following example of invalid Verilog code exhibits this problem:
module DFT_003 (Clk, Reset, Din, Dout);
input Clk, Reset, Din;
output Dout;
reg Dout, Dout_temp;
always @(posedge Clk) // Posedege clock
begin
if (!Reset)
Dout_temp<= 0;
else
Dout_temp <= Din;
end
always @(negedge Clk)
begin
if (!Reset)
Dout <= 0;
else
Dout <= Dout_temp;
end
endmodule

// DFT_003 flags here

Violations
14: always @(negedge Clk)
^
DFT_003.v:14: DATA_C> [WARNING] DFT_003: Avoid using both positive-edge
and negative-edge triggered flip-flops in your design

15

Chapter 1: DFT Coding Rules

TEST_972
Message: Clock affects both clock and data inputs of
flipflops
Description

This rule checks if a clock signal drives both the data input and the
clock pin of a flip-flop.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_972 ();
reg D, CP , CD, Q;
GTECH_FD2 U0 (.D(CP), .CP(CP), .CD(CD), .Q(Q));
endmodule

// TEST_972 flags here

Violations
3: GTECH_FD2 U0 (.D(CP), .CP(CP), .CD(CD), .Q(Q));
^
TEST_972.v:3: DATA_C> [ERROR] TEST_972: Clock affects both clock and
data inputs of flipflops

16

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

D
Clk

FF

Ck

TEST-972

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

17

Chapter 1: DFT Coding Rules

TEST_973
Message: Clock affects both clock and data inputs of latches
Description

This rule checks if a clock signal drives both the data input and the
clock pin of a latch.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_973 (D, CP, CD, Q);
input D, CP, CD;
output reg Q;
GTECH_LD3 U0 (.D(CP), .G(CP), .CD(CD), .Q(Q));
endmodule

// TEST_973 flags here

Violations
4:

GTECH_LD3 U0 (.D(CP), .G(CP), .CD(CD), .Q(Q));

^
TEST_973.v:4: DATA_C> [ERROR] TEST_973: Clock affects both clock and
data inputs of latches

18

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

Clk

Latch

Ck

TEST-973

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

19

Chapter 1: DFT Coding Rules

TEST_974
Message: Latch enabled by a clock feeds latches enabled by
the same clock
Description

The rule detects if a latch output enabled by a given clock affects the
data input of latches using the same clock.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_974 (D, CP, CD, Q);
input D, CP, CD;
output reg Q;
reg Q_tmp;
GTECH_LD3 U0 (.D(D), .G(CP), .CD(CD), .Q(Q_tmp));
GTECH_LD3 U1 (.D(Q_tmp), .G(CP), .CD(CD), .Q(Q)); // TEST_974 flags here
endmodule

Violations
6:

GTECH_LD3 U1 (.D(Q_tmp), .G(CP), .CD(CD), .Q(Q));

^
TEST_974.v:6: DATA_C> [ERROR] TEST_974: Latch enabled by a clock feeds
latches enabled by the same clock

20

Chapter 1: DFT Coding Rules

Example
The following circuit diagram illustrates the problem:

C
k

D
C
k

L
atch

C
lk

L
atch

TE
ST-974

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

21

Chapter 1: DFT Coding Rules

TEST_975
Message: Latch enabled by a clock affects data input of
flipflops clocked by the trailing edge of the same clock
Description

The rule detects if a latch output enabled by a given clock affects the
data input of flip-flops using the trailing edge of the same clock.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_975 (D, CP, CD, Q);
input D, CP, CD;
output reg Q;
reg Q_tmp;
GTECH_LD3 U0 (.D(D), .G(CP), .CD(CD), .Q(Q_tmp));
always @ (negedge CP)
Q <= Q_tmp;
// TEST_975 flags here
endmodule

Violations
7:

Q <= Q_tmp;
^
TEST_975.v:7: DATA_C> [ERROR] TEST_975: Latch enabled by a clock affects
data input of flipflops clocked by the trailing edge of the same clock

22

Chapter 1: DFT Coding Rules

Example
The following circuit diagram illustrates the problem:

C
lk

C
k

L
atch

FF

C
k

TE
ST-975

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

23

Chapter 1: DFT Coding Rules

TEST_978
Message: Latch data gates clocks of flipflops. Combination
of latch data and clock signal to clock a flipflop is not
allowed
Description

This rule detects if a signal used to clock a flip-flop is a combination

of a latch output and a given clock where the latch and the flip-flop
are within the same clock domain.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

C
lk

C
k

L
atch

FF

C
k

TE
ST-978

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

24

Chapter 1: DFT Coding Rules

TEST_979
Message: Latch data gates clocks enabling latches.
Combination of latch data and clock signal to clock a latch
is not allowed
Description

This rule detects if a signal used to enable a latch is a combination of

a latch output and a given clock, and the two latches are within the
same clock domain.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

C
k

D
C
k

L
atch

C
lk

L
atch

TE
ST-979

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

25

Chapter 1: DFT Coding Rules

TEST_980
Message: Flipflop data gates clocks to flipflops. Combination
of flipflop data and clock signal to clock a flipflop is not
allowed
Description

This rule detects if a signal used to clock a flip-flop is a combination

of a flip-flop output and a given clock and the two flip-flops are
within the same clock domain.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

D
C
lk

FF

FF

C
k

C
k

TE
ST-980

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

26

Chapter 1: DFT Coding Rules

TEST_981
Message: Flipflop data gates clocks enabling latches.
Combination of flipflop data and clock signal to clock a latch
is not allowed
Description

This rule detects if a signal used to enable a latch is a combination of

a flip-flop output and a given clock and the latch and flip-flop are
within the same clock domain.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

C
lk

FF

D
C
k

C
k

L
atch

TE
ST-981

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

27

Chapter 1: DFT Coding Rules

TEST_994
Message: Clock affects multiple clock or async ports of
register
Description

This rule detects if a clock feeds into a clock pin and a asynchronous
control of a given register.

Policy

DFT

Ruleset

DATA_CAPTURE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_994 (D, CP, CD, Q);
input D, CP, CD;
output reg Q;
GTECH_FD2 U0 (.D(D), .CP(CP), .CD(CP), .Q(Q));
endmodule

// TEST_994 flags here

Violations
4:

GTECH_FD2 U0 (.D(D), .CP(CP), .CD(CP), .Q(Q));

^
TEST_994.v:4: DATA_C> [ERROR] TEST_994: Clock affects multiple clock or
async ports of register

28

Chapter 1: DFT Coding Rules

Example
The following circuit diagram illustrates the problem:

FF

Ck

Clk

TEST-994

29

Chapter 1: DFT Coding Rules

Fault Coverage Ruleset

The following rules are from the fault coverage ruleset. For information on differences
between Leda DFT checks and RTL DRC checks, see Using the DFT Policy on
page 12.

DFT_006
Message: Multiple clocks in the unit
Description

None

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Block-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

30

Chapter 1: DFT Coding Rules

Example
The following example of invalid Verilog code exhibits this problem:
module DFT_006 (D, CP1, CP2, CD, Q1, Q2);
input D, CP1, CP2, CD;
output reg Q1, Q2;
reg Q_tmp;
wire CP_gate;
always @ (posedge CP1 or negedge CD)
if(CD)
Q1 <= 0;
else
Q1 <= D;
always @ (posedge CP2 or negedge CD)
if(CD)
Q2 <= 0;
else
Q2 <= D;
endmodule

// DFT_006 flags here

Violations
12:

always @ (posedge CP2 or negedge CD)

^^^^^^^
DFT_006.v:12: FAULT_> [ERROR] DFT_006: 2 clocks in a block

31

Chapter 1: DFT Coding Rules

DFT_008
Message: Tri-state is detected
Description

None

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Block-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.
Example
The following example of invalid Verilog code exhibits this problem:
module DFT_008 ();
wire tristate, En;
assign tristate = En ? 0 : 1'bZ;
endmodule

// DFT_008 flags here

Violations
3:

assign tristate = En ? 0 : 1'bZ;

^
DFT_008.v:3: FAULT_> [ERROR] DFT_008: Tri-state is detected

32

Chapter 1: DFT Coding Rules

DFT_009
Message: Register all outputs from the block for improved
coverage: %s
Description

This rule only checks at the architecture/module level. There is a

similar rule in the Leda general coding guidelines policy that you can
use to check the entire design.
This rule only works if you specify the top level of the design using
the -top switch.
%s is the name of hierarchical register.

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.
Example
The following example of invalid Verilog code exhibits this problem:
module DFT_009 (din, dout);
input din;
output dout;
assign dout = din;
endmodule

// DFT_009 flags here

Violations
3: output dout;
^
DFT_009.v:3: FAULT_> [ERROR] DFT_009: Register all outputs from the
block for improved coverage: DFT_009.dout

33

Chapter 1: DFT Coding Rules

TEST_960
Message: Avoid asynchronous feedback loops
Description

This rule checks for combinatorial asynchronous path loops.

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

34

Chapter 1: DFT Coding Rules

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_960 ( CLK , RST , DATA_IN , AUX , DATA_OUT );
input CLK;
input RST;
input DATA_IN;
input [2:0] AUX;
output DATA_OUT;
reg FF_DATA_IN;
reg FF_DATA_OUT;
wire AND1 ,AND2;
wire OR1;
always @(posedge CLK or negedge RST)
if(!RST)
FF_DATA_IN <= 1'b0;
else
FF_DATA_IN <= DATA_IN;
assign OR1 = AUX[2] | AUX[1] | AUX[0] | AND2 | FF_DATA_IN ;
// TEST_960 flags in the above line

assign AND2 = OR1 & AND1;

assign AND1 = AUX[2] & AUX[0] ;
always @(posedge CLK or negedge RST)
if(!RST)
FF_DATA_OUT <= 1'b0;
else
FF_DATA_OUT <= OR1;
endmodule

Violations
21: assign OR1 = AUX[2] | AUX[1] | AUX[0] | AND2 | FF_DATA_IN ;
^
TEST_960.v:21: FAULT_> [ERROR] TEST_960: Avoid asynchronous feedback
loops

35

Chapter 1: DFT Coding Rules

TEST_970
Message: Clock affects data inputs of flipflops
Description

This rule checks if a clock interacts with the data input of a flip-flop.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_970 (D1, D2, CP1, CP2, CD1, CD2, Q1, Q2);
input D1, D2, CP1, CP2, CD1, CD2;
output reg Q1 , Q2;
GTECH_FD2 U0 (.CP(CP1), .D(D1), .CD(CD1), .Q(Q1));
GTECH_FD2 U1 (.CP(CP2), .D(CP1), .CD(CD2), .Q(Q2));// TEST_970 flags here

endmodule

Violations
6:

GTECH_FD2 U1 (.CP(CP2), .D(CP1), .CD(CD2), .Q(Q2));

^
TEST_970.v:6: FAULT_> [ERROR] TEST_970: Clock affects data inputs of
flipflops

36

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

Clk2

FF

Ck

Clk1

TEST-970

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

37

Chapter 1: DFT Coding Rules

TEST_971
Message: Clock affects data inputs of latches
Description

This rule checks if a clock interacts with the data input of a latch.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
module TEST_971_fail (D1, D2, CP1, CP2, CD1, CD2, Q1, Q2);
input D1, D2, CP1, CP2, CD1, CD2;
output reg Q1 , Q2;
GTECH_LD3 U0 (.G(CP1), .D(D1), .CD(CD1), .Q(Q1));
GTECH_LD3 U1 (.G(CP2), .D(CP1), .CD(CD2), .Q(Q2)); // TEST_971 flags here

endmodule

Violations
6:

GTECH_LD3 U1 (.G(CP2), .D(CP1), .CD(CD2), .Q(Q2));

^
TEST_971.v:6: FAULT_> [ERROR] TEST_971: Clock affects data inputs of
latches

38

Chapter 1: DFT Coding Rules

Example
The following circuit diagram illustrates the problem:

Ck

Clk1

Latch

Clk2

TEST-971

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

39

Chapter 1: DFT Coding Rules

TEST_976
Message: Latches capture only when more than one clock is
on
Description

This rule checks if a latch can be used as a part of a scan chain. If so,
a latch having multiple clocks to enable data must be able to capture
data with one clock active and all others off.

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

D
Latch

C lk 2
C lk 1

Ck

L o g ic m u st b e a c o m b in a tio n o f g a te s
re sp e c tin g th e fo llo w in g ru le s :
- C lo c k a n d d a ta a re A N D e d
- T w o c lo c k s a re O R e d
T E S T -9 7 6

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

40

Chapter 1: DFT Coding Rules

TEST_977
Message: Flipflops capture only when more than one clock
is on
Description

This rule checks if a flip-flop can be used as a part of a scan chain. If

so, a flip-flop having multiple clocks to clock data must be able to
capture data with one clock active and all others off.

Policy

DFT

Ruleset

FAULT_COVERAGE

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

FF

Clk2
Clk1

Ck

TEST-977

41

Chapter 1: DFT Coding Rules

Informational Ruleset
The following rules are from the informational ruleset:

DFT_017
Message: Synchronous reset/set/load <%item> detected
Description

None

Policy

DFT

Ruleset

INFORMATIONAL

Language

VHDL/Verilog

Type

Block-level

Severity

Warning

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.
Example
The following example of invalid Verilog code exhibits this problem:
module DFT_017 (SyncRst, B, Clk, C);
input SyncRst;
input B;
input Clk;
output C;
reg C;
always @ (posedge Clk)
begin
if (SyncRst == 1)
C <= 0;
end
endmodule

// DFT_017 flags here

Violations
9:

if (SyncRst == 1)
^^^^^^^
DFT_017.v:9: INFORM> [WARNING] DFT_017: Synchronous reset/set/load
SyncRst detected

42

Chapter 1: DFT Coding Rules

DFT_019
Message: Asynchronous reset/set/load <%item> detected
Description

None.

Policy

DFT

Ruleset

INFORMATIONAL

Language

VHDL/Verilog

Type

Block-level

Severity

Note

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

43

Chapter 1: DFT Coding Rules

DFT_021
Message: Latch inferred
Description

This rule only checks at the architecture/module level. There is a

similar rule in the Leda general coding guidelines policy that you can
use to check the entire design.

Policy

DFT

Ruleset

INFORMATIONAL

Language

VHDL/Verilog

Type

Block-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.
Example
The following example of invalid Verilog code exhibits this problem:
module DFT_021 (B, Clk, C);
input B;
input Clk;
output C;
reg C;
always @ (Clk)
begin
if (B)
C <= B;
end
endmodule

// DFT_021 flags here

Violations
9:

C <= B;
^
DFT_021.v:9: INFORM> [ERROR] DFT_021: Latch inferred for C

44

Chapter 1: DFT Coding Rules

DFT_022
Message: Incomplete case statement
Description

This rule fires if all the alternatives of the case statement are not
covered and if there is no default clause.

Policy

DFT

Ruleset

INFORMATIONAL

Language

Verilog

Type

Block-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.
Example
The following examples show valid and invalid coding styles:
module DFT_022 (gate, q);
input [1:0] gate;
output q;
reg q;
always @gate begin // DFT_022:Incomplete case statement
case (gate)
// DFT_022 flags here
2'b00: q = 1'b0;
2'b10: q = 1'b1;
endcase
end
endmodule

Violations
7:

case (gate)
^^^^
DFT_022.v:7: INFORM> [ERROR] DFT_022: Incomplete case statement

45

Chapter 1: DFT Coding Rules

Scan Insertion Ruleset

The following rules are from the scan insertion ruleset:
For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

DFT_002
Message: Internally generated clock detected
Description

This rule verifies that all clocks are controllable from the top level of
the design and not internally generated via a sequential block.
Rationale: internally generated clocks may not be controllable from
the boundary of the chip. This reduces test coverage.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.
Example
The following examples show valid and invalid coding styles:
module DFT_002 ();
reg Clk, Din, Dout;
always @ (posedge Clk)
Dout <= Din;
endmodule

// DFT_002 flags here

Violations
2:

reg Clk, Din, Dout;

^
DFT_002.v:2: SCAN_I> [ERROR] DFT_002: Internally generated clock
detected

46

Chapter 1: DFT Coding Rules

TEST_953
Message: Flipflops with clocks tied to a signal that is not
driven by Test Clock. Flipflops' clock signal is not reached
by any Test Clock
Description

This rule checks whether the flip-flop clock is uncontrollable. That

case occurs when the test clock does not reach any signal which
drives the clock input pins of flip-flops.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12 .

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_953 (TstClk, Din, Dout);
input TstClk;
input Din;
wire Clk; // Not driven by Test Clock
output reg Dout;
reg Dout1;
always @ (posedge Clk)
Dout <= Din;
// TEST_953 flags here
always @ (posedge TstClk)
Dout1 <= Din;
endmodule

Violations
8:

Dout <= Din;

^
TEST_953.v:8: SCAN_I> [ERROR] TEST_953: Flipflops with clocks tied to a
signal that is not driven by Test Clock. Flipflops' clock signal is not
reached by any Test Clock

47

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

D
Test_C
k

FF

C
k
C
P
TEST-953

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

48

Chapter 1: DFT Coding Rules

TEST_954
Message: Latches with clocks tied to a signal that is not
driven by Test Clock. Latch clock signal is not reached by
any Test Clock
Description

This rule checks whether the latch clock is uncontrollable. That case
occurs when the test clock does not reach any signal which drives the
clock input pins of latches.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_954 (TstClk, Din, Dout);
input TstClk;
input Din;
wire Clk; // Not driven by Test Clock
output reg Dout;
reg Dout1;
GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));
// TEST_954 flags here
GTECH_LD1 U1 (.D(Din), .G(TstClk), .Q(Dout1));
endmodule

Violations
8:

GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));

^
TEST_954.v:8: SCAN_I> [ERROR] TEST_954: Latches with clocks tied to a
signal that is not driven by Test Clock. Latch clock signal is not
reached by any Test Clock

49

Chapter 1: DFT Coding Rules

D
Test_C
k
C
k

L
atch

Example
The following circuit diagram illustrates the problem:

EN
TEST-954

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

50

Chapter 1: DFT Coding Rules

TEST_963
Message: Flipflops have clocks with no off-state
controllability. Test Clock reaches flipflops but does not
control them at beginning of cycle
Description

This rule detects if the test clock reaches flip-flops but the flip-flop
clocks cannot change state as result of test clock toggling.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_963 (TstClk, Din, Dout);
input TstClk;
input Din;
wire Clk;
output reg Dout;
reg Dout1;
assign Clk = TstClk | Dout;
GTECH_FD1 U0 (.D(Din), .CP(Clk), .Q(Dout));
GTECH_FD1 U1 (.D(Din), .CP(TstClk), .Q(Dout1));
endmodule

// TEST_963 flags here

Violations
8:

GTECH_FD1 U0 (.D(Din), .CP(Clk), .Q(Dout));

^
TEST_963.v:8: SCAN_I> [ERROR] TEST_963: Flipflops have clocks with no
off-state controllability. Test Clock reaches flipflops but does not
control them at beginning of cycle

51

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

FF

FF

Test_Ck
CP
TEST-963

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

52

Chapter 1: DFT Coding Rules

TEST_964
Message: Latches have clocks with no off-state
controllability. Test Clock reaches latches but does not
control them at beginning of cycle
Description

This rule detects if the test clock reaches latches but the latch clocks
cannot change state as result of test clock toggling.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_964 (TstClk, Din, Dout);
input TstClk;
input Din;
wire Clk;
output reg Dout;
reg Dout1;
assign Clk = TstClk | Dout;
GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));
GTECH_LD1 U1 (.D(Din), .G(TstClk), .Q(Dout1));
endmodule

// TEST_964 flags here

Violations
8:

GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));

^
TEST_964.v:8: SCAN_I> [ERROR] TEST_964: Latches have clocks with no offstate controllability. Test Clock reaches latches but does not control
them at beginning of cycle

53

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

FF

Q
Latch

Test_Ck
EN
TEST-964

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

54

Chapter 1: DFT Coding Rules

TEST_965
Message: Latches not holding data in off-state. Test Clock
reaches latch but does not hold data in them at beginning of
cycle
Description

This rule detects if the test clock does not hold data at the beginning
of the test clock cycle.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_965 (TstClk, Din, Dout);
input TstClk;
input Din;
wire Clk;
output reg Dout;
reg Dout1;
assign Clk = ~TstClk;
GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));
GTECH_LD1 U1 (.D(Din), .G(TstClk), .Q(Dout1));
endmodule

// TEST_965 flags here

Violations
8:

GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));

^
TEST_965.v:8: SCAN_I> [ERROR] TEST_965: Latches not holding data in offstate. Test Clock reaches latch
but does not hold data at beginning of
cycle

55

Chapter 1: DFT Coding Rules

T
e
s
t
_
C
k

E
N
T
E
S
T
9
6
5

D
T
e
s
t
_
C
k

L
a
t
c
h

L
a
t
c
h

The following circuit diagram illustrates the problem:

E
N
T
E
S
T
9
6
5

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

56

Chapter 1: DFT Coding Rules

TEST_966
Message: Flipflops have no asynch controllability. No Test
Asynch reaches flipflop's async control pin
Description

This rule checks whether the flip-flop asynchronous control signal is

uncontrollable. That case occurs when the test asynch does not reach
any signal which drives the asynchronous control input pins of flipflops.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following circuit diagram illustrates the problem:

Rst
D
Test_Async

FF

TEST-966

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

57

Chapter 1: DFT Coding Rules

TEST_967
Message: Latches have no asynch controllability. No Test
Asynch reaches latches async control pin
Description

This rule detects if the latch asynchronous control signal is

uncontrollable. That case occurs when the test asynch does not reach
any signal which drives the asynchronous control input pins of
latches.
For this rule to work, you must specify a test clock. For more
information, see Using the DFT Policy on page 12.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_967 (TstClk, Din, Dout, TstRst);
input TstClk, TstRst;
input Din;
wire Clk;
output reg Dout;
reg Dout1;
assign Clk = TstClk | Dout;
GTECH_LD3 U0 (.D(Din), .CD(),
.G(TstClk), .Q(Dout)); // TEST_967 flags here
GTECH_LD3 U1 (.D(Din), .CD(TstRst), .G(TstClk), .Q(Dout1));

endmodule

Violations
8:

GTECH_LD3 U0 (.D(Din), .CD(),

.G(TstClk), .Q(Dout));
^
TEST_967.v:8: SCAN_I> [ERROR] TEST_967: Latches have no asynch
controllability. No Test Asynch reaches latches async control pin

58

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

Rst
Q
Latch

D
Test_Async

TEST-967

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

59

Chapter 1: DFT Coding Rules

TEST_968
Message: Flipflops have asynchs that cannot be disabled.
Test Asynch reaches flipflops but cannot disable their
asynch controls
Description

This rule detects if the test asynch reaches flip-flops but cannot
disable their async controls.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_968 (TstClk, Din, Dout, TstRst);
input TstClk, TstRst;
input Din;
wire Clk;
output reg Dout;
reg Dout1;
wire RstOred, Rst;
assign RstOred = TstRst | Rst;
GTECH_FD2 U0 (.D(Din), .CD(RstOred), .CP(TstClk), .Q(Dout));
// TEST_968 flags in the above line
GTECH_FD2 U1 (.D(Din), .CD(TstRst), .CP(TstClk), .Q(Dout1));

endmodule

Violations
9:

GTECH_FD2 U0 (.D(Din), .CD(RstOred), .CP(TstClk), .Q(Dout));

^
TEST_968.v:9: SCAN_I> [ERROR] TEST_968: Flipflops have asynchs that
cannot be disabled. Test Asynch reaches flipflops but cannot disable
their asynch controls

60

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

Test_Async
D
Test_Async must disable
the asynchronous pin of the
flipflop

FF

TEST-968

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

61

Chapter 1: DFT Coding Rules

TEST_969
Message: Latches have asynchs that cannot be disabled.
Test Asynch reaches latches but cannot disable their
asynch controls
Description

This rule detects if the Test_async reaches latches but cannot disable
their async controls.

Policy

DFT

Ruleset

SCAN_INSERTION

Language

VHDL/Verilog

Type

Chip-level

Severity

Error

Example
The following examples show valid and invalid coding styles:
module TEST_969 (TstClk, Din, Dout, TstRst);
input TstClk, TstRst;
input Din;
wire Clk;
output reg Dout;
reg Dout1;
wire RstOred, Rst;
assign RstOred = TstRst | Rst;
GTECH_LD3 U0 (.D(Din), .CD(RstOred), .G(TstClk), .Q(Dout));
// TEST_969 flags in the above line
GTECH_LD3 U1 (.D(Din), .CD(TstRst), .G(TstClk), .Q(Dout1));

endmodule

Violations
9:

GTECH_LD3 U0 (.D(Din), .CD(RstOred), .G(TstClk), .Q(Dout));

^
TEST_969.v:9: SCAN_I> [ERROR] TEST_969: Latches have asynchs that cannot
be disabled. Test Asynch reaches latches but cannot disable their
asynch controls

62

Chapter 1: DFT Coding Rules

The following circuit diagram illustrates the problem:

Test_Async

Test_Async must disable

the asynchronous pin of the
latch

Q
Latch

TEST-969

For information on differences between Leda DFT checks and RTL DRC checks, see
Using the DFT Policy on page 12.

63

Chapter 1: DFT Coding Rules

64