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Verilog For Finite State Machines

This document discusses best practices for implementing finite state machines (FSMs) in Verilog. It recommends using a register to store the current state and an always block triggered on the positive edge of a clock signal to update the state. A next state function defined with an always @(*) block combines the current state and inputs to determine the next state. Finally, an output function specifies the outputs for each state using case statements. Examples are provided to demonstrate Moore and Mealy FSM implementations.

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Er Pradip Patel
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231 views8 pages

Verilog For Finite State Machines

This document discusses best practices for implementing finite state machines (FSMs) in Verilog. It recommends using a register to store the current state and an always block triggered on the positive edge of a clock signal to update the state. A next state function defined with an always @(*) block combines the current state and inputs to determine the next state. Finally, an output function specifies the outputs for each state using case statements. Examples are provided to demonstrate Moore and Mealy FSM implementations.

Uploaded by

Er Pradip Patel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog for Finite State Machines

Strongly recommended style for FSMs


Works for both Mealy and Moore FSMs
You can break the rules

But you have to live with the consequences

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

Mealy and Moore machines


inputs

Moore

combinational
logic for
next state

logic for
outputs

reg

outputs

state feedback

Mealy
inputs

logic for
outputs
combinational
logic for
next state

outputs

reg

state feedback

Spring 2010

state feedback

CSE370 - XIV - Finite State Machines I

Constructing State Machines in Verilog

We need register to hold


the current state

always @(posedge clk) block

We need next state function

Where do we go from each state given the inputs


state by state case analysis

next state determined by current state and inputs

We need the output function

State by state analysis


Moore: output determined by current state only
Mealy: output determined by current state and inputs

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

State Register

Declare two values

state : current state output of state register


nxtState : next state input to state register
We rely on next state function to give us nxtState

Declare symbols for states with state assignment


localparam IDLE=0, WAITFORB=1,
DONE=2, ERROR=3;
reg [1:0] state,
// Current state
nxtState; // Next state

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

State Register

Simple code for register

Define reset state


Otherwise, just move to nxtState on clock edge
localparam IDLE=0, WAITFORB=1,
DONE=2, ERROR=3;
reg [1:0] state,
// Current state
nxtState; // Next state
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
// Initial state
end else begin
state <= nxtState;
end
end

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

Next State Function

Combinational logic function

Inputs : state, inputs


Output : nxtState

We could use assign statements


We will use an always @(*) block instead

Allows us to use more complex statements


if
case

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

always @(*) Block

Used for combinational logic functions


Is always active like assign statements
Assignment ( = ) used to assign function value
Output can be assigned more than once

e.g. multiple if statements


The last one counts

All outputs must be assigned at least once

No matter how ifs and cases are executed


Otherwise function is undefined
Use default assignments to help you

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

Next State Function

Describe what happens in each state


Case statement is natural for this
always @(*) begin
nxtState = state; // Default next state: dont move
case (state)
IDLE : begin
if (B) nxtState = ERROR;
else if (A) nxtState = WAITFORB;
end
WAITFORB : begin
if (B) nxtState = DONE;
end
DONE : begin
end
ERROR : begin
end
endcase
end

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

Output Function

Describe the output of each state

always @(*) begin


nxtState = state; // Default next state: stay where we are
out = 0;
// Default output
case (state)
IDLE : begin
if (B) nxtState = ERROR;
else if (A) nxtState = WAITFORB;
end
WAITFORB : begin
if (B) nxtState = DONE;
end
DONE : begin
out = 1;
end
ERROR : begin
end
endcase
end

Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

Example #2 : Edge Detector (Moore)


0
1

B/0
0
reset

A/0

localparam A=0, B=1, C=2, D=4, E=5;


reg [2:0] state,
// Current state
nxtState; // Next state

D/1
0

1
C/0

E/1

always @(posedge clk) begin


if (reset) begin
state <= A;
// Initial state
end else begin
state <= nxtState;
end
end
Sprint 2010

CSE370 - XV - Verilog for Finite State Machines

10

Example #2 : Edge Detector (Moore)


always @(*) begin
nxtState = state;
out = 0;
case (state)
A : if (in) nxtState = C;
else
nxtState = B;
B : if (in) nxtState = D;
C : if (~in) nxtState = E;
D : begin
out = 1;
if (in) nxtState = C;
else
nxtState = E;
end
E : begin
out = 1;
if (in) nxtState = D;
else
nxtState = B;
end
default : begin
out = 1bX;
nxtState = 3bX;
end
endcase
end
Sprint 2010

0
1

B/0
0
reset

D/1
1

A/0

1
C/0

E/1

11

CSE370 - XV - Verilog for Finite State Machines

Example #2 : Edge Detector (Moore)

Using state assignment for output

Only works for Moore FSM


0

always @(*) begin


nxtState = state;
out = state[2];
case (state)
A : if (in) nxtState = C;
else
nxtState = B;
B : if (in) nxtState = D;
C : if (~in) nxtState = E;
D : if (in) nxtState = C;
else
nxtState = E;
E : if (in) nxtState = D;
else
nxtState = B;
default : nxtState = 3bX;
endcase
end

Sprint 2010

B/0
reset

A/0

CSE370 - XV - Verilog for Finite State Machines

D/1
0

1
C/0

E/1

12

Example #2 : Edge Detector (Mealy)

0/0
B
0/0

reset/0

0/1

1/1

1/0

localparam A=0, B=1, C=2;


reg [1:0] state,
// Current state
nxtState; // Next state

C
1/0

always @(posedge clk) begin


if (reset) begin
state <= A;
// Initial state
end else begin
state <= nxtState;
end
end
Sprint 2010

13

CSE370 - XV - Verilog for Finite State Machines

Example #2 : Edge Detector (Moore)

Output depends on state and input


always @(*) begin
nxtState = state;
out = 0;
case (state)
A : if (in) nxtState = C;
else
nxtState = B;
B : if (in) begin
out = 1;
nxtState = C;
end
C : if (~in) begin
out = 1;
nxtState = B;
end
default : begin
out = 1bX;
nxtState = 3bX;
end
endcase
end

Sprint 2010

0/0
B
0/0
reset/0

CSE370 - XV - Verilog for Finite State Machines

0/1

1/1

1/0
C
1/0

14

Summary

Please use standard FSM Verilog style shown here

always @(posedge clk) block

Do not be beguiled into thinking this is programming C!

Use only for registers with simple logic


e.g. shifter, counter, enabled register, etc.

Miscellaneous combinational logic

assign statements (always safe)


always @(*) block (be very careful)

Think of this as a complex assign statement

Sprint 2010

Fine to have more than one


CSE370 - XV - Verilog for Finite State Machines

15

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