Formality Ultra WP

White Paper
ECO Implementation and

Verification Using Formality Ultra
November 2013
Author
David Low
Formality CAE,
Synopsys Inc.
Formality Ultra is an extension to the Formality equivalence-checking solution. This article describes how
Formality Ultra can be used to aid in the analysis, modification, and verification of a design that requires
an ECO change. An example detailing the ECO flow using Formality Ultra is shown.
Interactive Solution for ECO Implementation and Verification

During the design process, functional changes (ECO) may be made to the RTL after the physical
implementation has started. Corresponding functional modifications are also required of the postimplementation netlist. Since an ECO may come late in the design cycle, it is common to bypass the
regular synthesis flow and manually implement the functional changes directly to the post-implementation
netlist. Formality Ultra enables you to identify areas of ECO change, modify the design to implement the
ECO changes, and quickly verify only the areas of the design affected by the ECO modifications.
Example: Using Formality Ultra to Implement and Verify a Functional ECO

A section of the RTL description is shown below:
always @ (posedge clock)
begin
sink
<= pointer && remove;
end
assign
all_stop = |g_votes && (under || complete || sink);
assign
index = cycle && next && disp && flush && do_over &&
start_over && all_stop;
The required ECO change is to create a registered version of signal all_stop and use the registered
version (all_stop_clocked) in the assign statement of signal index. The RTL modifications to
implement the ECO are shown below. The areas that represent the ECO are highlighted.
always @ (posedge clock)
begin
sink
<= pointer && remove;
all_stop_clocked <= all_stop;
end
assign
all_stop = |g_votes && (under || complete || sink);
assign
index = cycle && next && disp && flush && do_over &&
start_over && all_stop_clocked;
Step 1: Creation of Supplemental SVF File

After verifying the RTL changes, the first step in the ECO flow is to modify the SVF generated by the original
synthesis so that it can be used in Formality with the post-ECO RTL. Since the original SVF file is derived from
the original RTL synthesis, the SVF file may need edits to make it compatible with the modified RTL. A script
(fm_eco_to_svf) is provided that produces the SVF information that reflects the changes from the original to
the post-ECO RTL source files.
In our example the RTL code is named timer.v.
$ fm_eco_to_svf rtl_orig/timer.v rtl_new/timer.v > eco_change.svf
The SVF provided in this step along with the original SVF will be used to run the verification of the post-ECO
RTL to original implementation netlist.
Step 2: Verification of Post-ECO RTL to Original Implementation

Now that the original SVF has been modified to work with the post-ECO RTL, a verification of the post-ECO
RTL to original implementation netlist is done. The Formality script below reads the ECO version of the RTL
and verifies against the original implementation netlist. This will be the starting point to find the areas of the
implementation design that are affected by the post-ECO RTL. The failing points are sent to a file failing_
points.rpt and a session file is saved. The session file will be used in subsequent runs to identify ECO
points of interest and modification of the implementation design.
# Post-ECO RTL vs. original gates
#
# Use the modified SVF file
set_svf eco_change.svf timer.svf
# Read designs into Formality
read_db library.db
read_verilog -r rtl_new/timer.v
set_top timer
read_ddc -i timer.ddc
set_top timer
# Find all failures and use low effort to run faster
set verification_failing_point_limit 0
set verification_effort_level low
verify
# Save information for later use in the flow
report_failing_points list > failing_points.rpt
save_session initial_ECO
In this example there is one failing point. Since the logic of the index signal has been modified in the
post-ECO RTL, a verification failure results as expected. The source of the failure is the introduction of the
registered version of signal all_stop. Below is the final transcript of the verification and the schematics of
the failing point.
ECO Implementation and Verification Using Formality Ultra
********************************* Verification Results *************************

Verification FAILED
ATTENTION: synopsys_auto_setup mode was enabled.
See Synopsys Auto Setup Summary for details.
---------------------------------------------------------Reference design: r:/WORK/timer
Implementation design: i:/WORK/timer
19 Passing compare points
1 Failing compare points
0 Aborted compare points
0 Unverified compare points
----------------------------------------------------------------------------Matched Compare Points BBPin Loop BBNet Cut Port DFF
LAT TOTAL
----------------------------------------------------------------------------Passing (equivalent) 0 0 0 0 17 2
0 19
Failing (not equivalent) 0 0 0 0 1 0
0 1
************************************************************************************
Step 3: Identification of ECO Location in the Implementation Netlist

The ECO change in the RTL implies that a new flip-flop needs to be added to the implementation netlist. In
order to add the new flip-flop to the netlist, we need to determine the signal in the implementation netlist that
corresponds to the all_stop signal in the RTL. This signal will become the D-input of the new flip-flop. The
find_equivalent_net command is used to find the corresponding net. To find an equivalent net using the
Formality GUI, the D-input of the RTL logic in the cone view of all_stop_clocked_reg is selected. The
schematic is shown below. Right-click in the GUI window and select ECO -> Find Equivalent Net.
The result of the find_equivalent_net command is shown below. Note the equivalent net browser showing
the equivalent nets and the net (n11) highlighted in yellow in the logic cone view. The net (n11) is the place that
will become the D-input of the new flip-flop to be inserted into the implementation view in Formality Ultra.
Step 4: Modification of the Implementation View

Now that the areas of interest have been identified, the next step is to modify the implementation design to
match the post-ECO RTL. Formality Ultra provides commands to edit the implementation design as well as
commands to highlight edits in the design schematics. The sequence of commands shown below will modify
the implementation design to replicate the ECO change.
current_instance i:/WORK/timer
create_cell all_stop_clocked_reg STN_FDPQ_1 \
-connections [list \
D=n11 \
CK=clock \
Q=[create_net -pins U32/B1]]
The create_cell command will create a flip-flop cell from the technology library (STN_FDPQ_1). The D input
will be connected to net n11, the CK input will be connected to the available net named clock, and the Q
output will be connected to a new net created by the create_net command. This new net will be connected
to pin U32/B1. Note that the name of the created cell (all_stop_clocked_reg) is used to aid in matching
with the register in the reference design. Using the Color Edits menu option of the ECO menu bar will highlight
the changes that have been made to the implementation design. This is very useful to confirm the changes are
as intended. Note the new register all_stop_clocked_reg and net FM_NET_1 (highlighted in orange) and
the modified nets n11, clock and the connection to U32/B1 (highlighted in yellow).
Step 5: Verification of ECO Modification

To check if the modifications to the implementation design are correct, Formality Ultra allows for a verification
of only the compare points affected by the ECO. This saves time since only a subset of the complete
design needs to be verified. To verify a subset of the compare points, the following set_verify_points
commands are used:
set_verify_points -file failing_points.rpt
set_verify_points [ find_compare_points -edits -list ]
The first set_verify_points command includes the failing points report generated by the verification
of the post-ECO RTL to the original implementation design. In this example there is one failing point. The
second set_verify_points command will add any compare points that were affected by ECO edits to the
implementation design. This will check that any edits did not affect previously passing points.
If the subset verification is successful, then a complete verification should be done to ensure total verification.
Step 6: Exporting Edit File to Other Tools

The edit commands that were used to implement the ECO can now be exported to downstream tools such
as DC and ICC. This will allow the ECO to be inserted in the original implementation design and complete the
design cycle.
Formality Ultra provides a write_edits command to create a DC/ICC compatible script.
The edit script produced by write_edits defines a variable called ROOT_PATH, which allows the user to set
the hierarchical path of the design in which ECO modifications will be made. This allows for differences in the
logical/physical hierarchy of the post-ECO design.
Summary
Formality Ultra provides advanced features to accelerate the manual ECO process. The primary features
include analysis, design modification, fast verification of the design with ECO modifications, and the ability to
export the ECO change file to implementation tools.
Synopsys, Inc. 700 East Middlefield Road Mountain View, CA 94043 www.synopsys.com
2013 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners.
10/13.AP.CS3603.

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White Paper

ECO Implementation and

Interactive Solution for ECO Implementation and Verification

Example: Using Formality Ultra to Implement and Verify a Functional ECO

Step 1: Creation of Supplemental SVF File

Step 2: Verification of Post-ECO RTL to Original Implementation

ECO Implementation and Verification Using Formality Ultra

********* Verification Results *

ECO Implementation and Verification Using Formality Ultra

Step 3: Identification of ECO Location in the Implementation Netlist

ECO Implementation and Verification Using Formality Ultra

Step 4: Modification of the Implementation View

Step 5: Verification of ECO Modification

ECO Implementation and Verification Using Formality Ultra

Step 6: Exporting Edit File to Other Tools

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