ON Semiconductor

Internally Compensated,
High Performance
Dual Operational Amplifiers

MC1458, C

The MC1458, C was designed for use as a summing amplifier,

integrator, or amplifier with operating characteristics as a function of
the external feedback components.
No Frequency Compensation Required
Short Circuit Protection
Wide Common Mode and Differential Voltage Ranges
Low Power Consumption
No LatchUp

DUAL
OPERATIONAL AMPLIFIERS
(DUAL MC1741)
SEMICONDUCTOR
TECHNICAL DATA

8
1

P1 SUFFIX
PLASTIC PACKAGE
CASE 626

MAXIMUM RATINGS (TA = +25C, unless otherwise noted.)

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC
VEE

+18
18

Vdc

Input Differential Voltage

VID

30

Input Common Mode Voltage (Note 1)

VICM

15

Output Short Circuit Duration (Note 2)

tSC

Continuous

Operating Ambient Temperature Range

TA

0 to +70

Storage Temperature Range

Tstg

55 to +125

Junction Temperature

TJ

150

8
1

D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO8)

NOTES: 1. For supply voltages less than 15 V, the absolute maximum

input voltage is equal to the supply voltage.
2. Supply voltage equal to or less than 15 V.

PIN CONNECTIONS

Output A
Inputs
A

Representative Schematic Diagram

VEE
VCC

1
2
3
4

VCC

Output B

B-

(Top View)

4.5 k

Noninverting
Input

39 k

25

ORDERING INFORMATION

30pF 7.5 k

Output

Inverting
Input

Device

50

Operating
Temperature Range

50 k

1.0 k

Semiconductor Components Industries, LLC, 2001

March, 2001 Rev. 2

50 k

50

MC1458CP1, P1

Package
SO8

MC1458CD, D
1.0 k

Inputs
B

TA = 0 to +70C

Plastic DIP

VEE

Publication Order Number:

MC1458/D

MC1458, C

ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, TA = 25C, unless otherwise noted. (Note 3))
MC1458

MC1458C

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Input Offset Voltage (RS 10 k)

VIO

2.0

6.0

2.0

1.0

mV

Input Offset Current

IIO

20

200

20

300

nA

Input Bias Current

IIB

80

500

80

700

nA

Input Resistance

ri

0.3

2.0

2.0

Input Capacitance

Ci

1.4

1.4

pF

Characteristic

Offset Voltage Adjustment Range

VIOR

15

15

mV

Common Mode Input Voltage Range

VICR

12

13

11

13

Large Signal Voltage Gain

(VO = 10 V, RL = 2.0 k)
(VO = 10 V, RL = 10 k)

AVOL
20

200

20

200

ro

75

75

Common Mode Rejection (RS 10 k)

CMR

70

90

60

90

dB

Supply Voltage Rejection (RS 10 k)

PSR

30

150

30

V/V

12
10

14
13

11
9.0

14
13

Output Resistance

V/mV

Output Voltage Swing

(RS 10 k)
(RS 2.0 k)

VO

Output Short Circuit Current

ISC

20

20

mA

Supply Currents (Both Amplifiers)

ID

2.3

5.6

2.3

8.0

mA

Power Consumption

PC

70

170

70

240

mW

Transient Response (Unity Gain)

(VI = 20 mV, RL 2.0 k, CL 100 pF) Rise Time
(VI = 20 mV, RL 2.0 k, CL 100 pF) Overshoot
(VI = 10 V, RL 2.0 k, CL 100 pF) Slew Rate

tTLH
os
SR

0.3
15
0.5

0.3
15
0.5

s
%
V/s

ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, TA = Thigh to Tlow, unless otherwise noted. (Note 3))*
MC1458

MC1458C

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Input Offset Voltage (RS 10 k)

VIO

7.5

12

mV

Input Offset Current (TA = 0 to +70C)

IIO

300

400

nA

Input Bias Current (TA = 0 to +70C)

IIB

800

1000

nA

Output Voltage Swing

(Rs 10 k)
(Rs 2 k)

VO

12
10

14
13

9.0

13

15

15

Characteristic

Large Signal Voltage Gain

(VO = 10 V, RL = 2 k)
(VO = 10 V, RL = 10 k)
*Tlow = 0C for MC1458, C
NOTE:

AVOL

V/mV

Thigh = +70C for MC1458, C

3. Input pins of an unused amplifier must be grounded for split supply operation or biased at least 3.0 V above V EE for single supply operation.

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2

MC1458, C
Figure 1. Burst Noise versus Source Resistance

Figure 2. RMS Noise versus Source Resistance

100

BW = 1.0 Hz to 1.0 kHz

en, INPUT NOISE (peak) ( V)

en, INPUT NOISE (peak) ( V)

1000

100

10

10

100

1.0 k

10 k

100 k

10

100

1.0

10 k

100 k

RS, SOURCE RESISTANCE ()

RS, SOURCE RESISTANCE ()

Figure 3. Output Noise versus Source Resistance

Figure 4. Spectral Noise Density

10
AV = 1000
1.0
100
10
0.1

1.0 M

140
en, INPUT NOISE ( nV/ Hz )

en, OUTPUT NOISE (rms mV)

1.0

0.1

1.0 M

BW = 1.0 Hz to 1.0 kHz

10

1.0

10

100

1.0 k

10 k

100 k

120

AV = 10, RS = 100 k

100
80
60
40
20
0

1.0 M

10

100

RS, SOURCE RESISTANCE ()

1.0 k

10 k

100 k

f, FREQUENCY (Hz)

Figure 5. Burst Noise Test Circuit

Positive
Threshold
Voltage

100 k

100 k
1.0 k

100 k

X 500

Operational Amplifier
Under Test

+
To Pass / Fail
Indicator

X2
Low Pass Filter
1.0 Hz to 1.0 kHz

Negative
Threshold
Voltage

The test time employed is 10 sec and the 20 V peak limit

refers to the operational amplifier input thus eliminating errors
in the closed loop gain factor of the operational amplifier .

Unlike conventional peak reading or RMS meters, this system

was especially designed to provide the quick response time
essential to burst (popcorn) noise testing.

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3

MC1458, C
Figure 7. Open Loop Frequency Response

28

120

24

100
A VOL , VOLTAGE GAIN (dB)

VO, OUTPUT VOLTAGE (Vpp )

Figure 6. Power Bandwidth

(Large Signal Swing versus Frequency)

20
16
12
(Voltage Follower)
THD < 5%

8.0
4.0
0

10

100

1.0 k
f, FREQUENCY (Hz)

10 k

80
60
40
20
0
-20

100 k

10

VO , OUTPUT VOLTAGE SWING (V)

15 V Supplies

100 k

11

12 V

9.0
9.0 V

7.0
5.0

6.0 V

3.0
100

200

500 700 1.0 k

2.0 k

-13

1.0 M

10 M

12 V

-9.0
-7.0

9.0 V

-5.0

6.0 V

-3.0
-1.0

5.0 k 7.0 k 10 k

15 V Supplies

-11

100

200

RL, LOAD RESISTANCE ()

100 F

+27 V
+24 V

20

+18 V

12

VCC

200 k

+15 V

8.0

+12 V

4.0

+9.0 V
+6.0 V
+5.0 V
1.0 2.0

50 k

50 k
200 k

3.0 4.0
5.0 6.0 7.0
RL, LOAD RESISTANCE (k)

5.0 k 7.0 k 10 k

10 k

1.0 k

Vin

+21 V

16

2.0 k

Figure 11. Single Supply Inverting Amplifier

28 +30 V Supply
24

500 700 1.0 k

RL, LOAD RESISTANCE ()

Figure 10. Output Voltage Swing versus

Load Resistance (Single Supply Operation)
VO, OUTPUT VOLTAGE SWING (Vpp )

10 k

-15

13

1.0 k

Figure 9. Negative Output Voltage Swing

versus Load Resistance

15
VO , OUTPUT VOLTAGE SWING (V)

100

f, FREQUENCY (Hz)

Figure 8. Positive Output Voltage Swing

versus Load Resistance

1.0

10

8.0

9.0

10

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4

100 F
MC1558

RL

MC1458, C
Figure 12. Noninverting Pulse Response

5.0 V/DIV

Output

Input

10 s/DIV

Figure 13. Transient Response Test Circuit

To Scope
(Output)
RL

CL

Figure 15. Open Loop Voltage Gain

versus Supply Voltage
105
100
AV , VOLTAGE GAIN (dB)

To Scope
(Input)

Figure 14. Unused OpAmp

95
90
85
80
75
70

2.0

4.0

6.0 8.0 10
12
14
16
VCC, |VEE|, SUPPLY VOLTAGES (V)

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5

18

20

MC1458, C
PACKAGE DIMENSIONS
P1 SUFFIX
PLASTIC PACKAGE
CASE 62605
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

B
1

DIM
A
B
C
D
F
G
H
J
K
L
M
N

F
A

NOTE 2

C
J

MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10

0.76
1.01

INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10

0.030
0.040

SEATING
PLANE

0.13 (0.005)

T A

D SUFFIX
PLASTIC PACKAGE
CASE 75107
(SO8)
ISSUE W
X

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

A
8

0.25 (0.010)

B
1

Y
G
C

X 45

SEATING
PLANE

0.10 (0.004)
H

D
0.25 (0.010)

Z Y

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6

DIM
A
B
C
D
G
H
J
K
M
N
S

MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0

8

0.25
0.50
5.80
6.20

INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0

8

0.010
0.020
0.228
0.244

MC1458, C

Notes

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MC1458, C

ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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8

MC1458/D