Memory examples
Chapter 5
Memories
Portions of this work are from the book, Digital Design: An Embedded
Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan
Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
Verilog
Example: Coefficient Multiplier
Compute function y ci x
Coefficient stored in flow-through SSRAM
12-bit unsigned integer index for i
x, y, ci 20-bit signed fixed-point
8 pre- and 12 post-binary point bits
Use a single multiplier
Multiply c x x
i
Digital Design Chapter 5 Memories
Verilog
Multiplier Datapath
Digital Design Chapter 5 Memories
Verilog
Multiplier Timing and Control
Digital Design Chapter 5 Memories
Verilog
Pipelined SSRAM
Data output also has a register
More suitable for high-speed systems
Access RAM in one cycle, use the data in
the next cycle
a1
a2
xx
xx
M(a2)
Digital Design Chapter 5 Memories
Verilog
Memories in Verilog
RAM storage represented by an array variable
reg [15:0] data_RAM [0:4095];
...
always @(posedge clk)
if (en)
if (wr) begin
data_RAM[a] <= d_in; d_out <= d_in;
end
else
d_out <= data_RAM[a];
Digital Design Chapter 5 Memories
Verilog
Example: Coefficient Multiplier
module scaled_square ( output reg signed [7:-12]
input
signed [7:-12]
input
[11:0]
input
input
y,
c_in, x,
i,
start,
clk, reset );
wire
c_ram_wr;
reg
c_ram_en, x_ce, mult_sel, y_ce;
reg signed [7:-12] c_out, x_out;
reg signed [7:-12] c_RAM [0:4095];
reg signed [7:-12] operand1, operand2;
parameter [1:0] step1 = 2'b00, step2 = 2'b01, step3 = 2'b10;
reg
[1:0] current_state, next_state;
assign c_ram_wr = 1'b0;
Digital Design Chapter 5 Memories
Verilog
Example: Coefficient Multiplier
always @(posedge clk) // c RAM - flow through
if (c_ram_en)
if (c_ram_wr) begin
c_RAM[i] <= c_in;
c_out
<= c_in;
end
else
c_out <= c_RAM[i];
always @(posedge clk) // y register
if (y_ce) begin
if (!mult_sel) begin
operand1 = c_out;
operand2 = x_out;
end
else begin
operand1 = x_out;
operand2 = y;
end
y <= operand1 * operand2;
end
Digital Design Chapter 5 Memories
Verilog
Example: Coefficient Multiplier
always @(posedge clk)
...
always @*
...
// State register
// Next-state logic
always @* begin
...
// Output logic
endmodule
Digital Design Chapter 5 Memories
Verilog
Multiport Memories
Multiple address, data and control
connections to the storage locations
Allows concurrent accesses
Scenario
Avoids multiplexing and sequencing
Data producer and data consumer
What if two writes to a location occur
concurrently?
Result may be unpredictable
Some multi-port memories include an arbiter
Digital Design Chapter 5 Memories
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Verilog
FIFO Memories
First-In/First-Out buffer
Connecting producer and consumer
Decouples rates of production/consumption
Producer
subsystem
Consumer
subsystem
FIFO
Implementation using
dual-port RAM
Circular buffer
Full: write-addr = read-addr
Empty: write-addr = read-addr
read
write
Digital Design Chapter 5 Memories
11
Verilog
FIFO Example
Design a FIFO to store up to 256 data items
of 16-bits each, using 256x 16-bit dual-port
SSRAM for the data storage. Assume the
FIFO will not be read when it is empty, not to
be written when it is full, and that the write
and read ports share a common clock.
Digital Design Chapter 5 Memories
12
Verilog
Example: FIFO Datapath
Equal = full or empty
Need to distinguish between these states How?
Digital Design Chapter 5 Memories
13
Verilog
Example: FIFO Control
Control FSM
filling when write without concurrent read
emptying when read without concurrent write
Unchanged when concurrent write and read
full = filling and equal
wr_en, rd_en
empty = emptying and equal
Digital Design Chapter 5 Memories
14
Verilog
Multiple Clock Domains
Need to resynchronize data that
traverses clock domains
Use resynchronizing registers
May overrun if sender's clock is faster
than receiver's clock
FIFO smooths out differences in data
flow rates
Latch cells inside FIFO RAM written with
sender's clock, read with receiver's clock
Digital Design Chapter 5 Memories
15
Verilog
Dynamic RAM (DRAM)
Data stored in a 1-transistor/1-capacitor cell
Write operation
Smaller cell than SRAM, so more per chip
But longer access time
pull bit-line high or low (0 or 1)
activate word line
Read operation
precharge bit-line to intermediate voltage
activate word line, and sense charge equalization
rewrite to restore charge
Digital Design Chapter 5 Memories
16
Verilog
DRAM Refresh
Charge on capacitor decays over time
Need to sense and rewrite periodically
Refresh each location
DRAMs organized into banks of rows
Typically every cell every 64ms
Refresh whole row at a time
Cant access while refreshing
Interleave refresh among accesses
Or burst refresh every 64ms
Digital Design Chapter 5 Memories
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Verilog
Read-Only Memory (ROM)
For constant data, or CPU programs
Masked ROM
Programmable ROM (PROM)
Data manufactured into the ROM
Use a PROM programmer
Erasable PROM (EPROM)
UV erasable
Electrically erasable (EEPROM)
Flash RAM
Digital Design Chapter 5 Memories
18
Verilog
Combinational ROM
A ROM maps address input to data output
This is a combinational function!
Specify using a table
Example: 7-segment decoder
Address
Content
Address
Content
0111111
1111101
0000110
0000111
1011011
1111111
1001111
1101111
1100110
1015
1000000
1101101
1631
0000000
Digital Design Chapter 5 Memories
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Verilog
Example: ROM in Verilog
module seven_seg_decoder ( output reg [7:1] seg,
input
[3:0] bcd,
input
blank );
always @*
case ({blank, bcd})
5'b00000: seg = 7'b0111111;
5'b00001: seg = 7'b0000110;
5'b00010: seg = 7'b1011011;
5'b00011: seg = 7'b1001111;
5'b00100: seg = 7'b1100110;
5'b00101: seg = 7'b1101101;
5'b00110: seg = 7'b1111101;
5'b00111: seg = 7'b0000111;
5'b01000: seg = 7'b1111111;
5'b01001: seg = 7'b1101111;
5'b01010, 5'b01011, 5'b01100,
5'b01101, 5'b01110, 5'b01111:
seg = 7'b1000000;
default: seg = 7'b0000000;
endcase
//
//
//
//
//
//
//
//
//
//
0
1
2
3
4
5
6
7
8
9
// "-" for invalid code
// blank
endmodule
Digital Design Chapter 5 Memories
20
Verilog
Flash RAM
Non-volatile, readable (relatively fast), writable
(relatively slow)
Storage partitioned into blocks
NOR Flash
Erase a whole block at a time, then write/read
Once a location is written, can't rewrite until erased
Can write and read individual locations
Used for program storage, random-access data
NAND Flash
Denser, but can only write and read block at a time
Used for bulk data, e.g., cameras, memory sticks
Digital Design Chapter 5 Memories
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Verilog
Summary
Memory: addressable storage locations
Read and Write operations
Asynchronous RAM
Synchronous RAM (SSRAM)
Dynamic RAM (DRAM)
Read-Only Memory (ROM) and Flash
Multiport RAM and FIFOs
Digital Design Chapter 5 Memories
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