Compact Flash

Viking Technology
COMPACT FLASH
Datasheet
Datasheet
PSFCF1XXXXDXX
Revision A4
www.vikingtechnology.com
01/09/2012
Viking Technology
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Ordering Information: Viking Compact Flash

Viking High Performance Compact Flash Ordering Information
Part Number
VRFCF10128Dx6
VRFCF10256Dx6
VRFCF10512Dx9
VRFCF11024Dx7
VRFCF12048DxG
VRFCF14096DxH
VRFCF18192DxK
VRFCF1016GDxK
VRFCF1032GDxN
Notes:
1.
Raw
Capacity
128MB
256MB
512MB
1GB
2GB
4GB
8GB
16GB
32GB
Unformatted
Capacity
(bytes)
127,401,984
254,803,968
531,062,784
1,046,126,592
2,044,256,256
4,100,898,816
8,183,734,272
16,438,173,700
32,782,417,920
SLC Device
Density
Form
Factor
1Gb
1Gb
2Gb
4Gb
8Gb
16Gb
32Gb
32Gb
64Gb
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
x is temperature: C = Commercial Temp, I = Industrial Temp
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PSFCF1XXXXDXX
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Table of Contents
1
INTRODUCTION
1.1
Features
1.2
Performance
1.3
CHS Parameters
1.4
Block Diagram
1.5
Mechanical Information
1.6
Interface
1.6.1 Host Interface
10
10
11
CONNECTOR PINS
2.1
Connector Pin Assignments
11
2.2
Pin Function Description
11
PRODUCT SPECIFICATIONS
14
3.1
Absolute Maximum Ratings
14
3.2
DC Operating Conditions and Characteristics
15
3.3
Environmental Specifications
16
3.4
Reliability & Retention
16
3.5
Capacitance
16
3.6
AC Characteristics
3.6.1 Power-on Timing
3.6.2 Attribute Memory Read Timing
3.6.3 Attribute Memory Write Timing
3.6.4 Common Memory Read Timing
3.6.5 Common Memory Write Timing
3.6.6 I/O Mode Read Timing
3.6.7 I/O Mode Write Timing
3.6.8 True IDE Mode PIO Read/Write Timing
3.6.9 True IDE Multiword DMA Read/Write Timing
3.6.10
Ultra DMA AC Characteristics
3.6.11
Ultra DMA Data Burst Timing Descriptions
Datasheet
PSFCF1XXXXDXX
Revision A4
16
16
18
18
20
21
22
23
24
25
26
27
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3.6.12
CF-ATA Command Support
28
3.7
Capacity Information
3.7.1 True IDE Mode
3.7.2 PCMCIA Mode (I/O and Memory Modes)
29
29
30
3.8
30
Identify Drive Parameter
3.9
SMART Support
3.9.1 SMART Enable Operations
3.9.2 SMART Disable Operations
3.9.3 SMART Enable/Disable Attribute Autosave
3.9.4 SMART Read Data
3.9.5 SMART Read Attribute Thresholds
3.9.6 SMART Return Status
3.9.7 SMART Read Remap Data
3.9.8 SMART Read Wear Level Data
33
34
34
34
36
39
40
41
41
CERTIFICATIONS AND COMPLIANCE
43
REFERENCES
43
REVISION HISTORY
43
Datasheet
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Table of Tables
Table 1-1: CF Card Read/Write Performance ________________________________________ 7
Table 1-2: CHS Parameters _____________________________________________________ 8
Table 2-1: Connector Pin Assignments____________________________________________ 11
Table 2-2: Pin Function Description ______________________________________________ 11
Table 3-1: Absolute Maximum Ratings ____________________________________________ 14
Table 3-2: DC Operating Conditions and Characteristics ______________________________ 15
Table 3-3: Environmental Specifications ___________________________________________ 16
Table 3-4: CF Card Reliability and Retention _______________________________________ 16
Table 3-5: Capacitance ________________________________________________________ 16
Table 3-6: Power-on Timing ____________________________________________________ 16
Table 3-7: Attribute Memory Read Timing__________________________________________ 18
Table 3-8: Attribute Memory Write Timing__________________________________________ 18
Table 3-9: Common Memory Read Timing _________________________________________ 20
Table 3-10:Common Memory Write Timing_________________________________________ 21
Table 3-11: I/O Mode Read Timing _______________________________________________ 22
Table 3-12: I/O Mode Write Timing _______________________________________________ 23
Table 3-13: True IDE Mode PIO Read/Write Timing (Modes 0-6)________________________ 24
Table 3-14: True IDE Multiword DMA Read/Write Timing (Modes 0-4)____________________ 25
Table 3-15: Ultra DMA AC Characteristics _________________________________________ 26
Table 3-16: Ultra DMA Data Burst Timing Descriptions _______________________________ 27
Table 3-17: CF-ATA Command Support ___________________________________________ 28
Table 3-18: True IDE Mode_____________________________________________________ 29
Table 3-19: PCMCIA Mode (I/O and Memory Modes) ________________________________ 30
Table 3-20: Identify Drive Parameter _____________________________________________ 30
Table 3-21: Identify Drive Parameter Table in PCMCIA mode showing word differences _____ 33
Table 3-22: Identify Drive Parameter Table in PCMCIA mode showing word differences _____ 33
Table 3-23: Supported SMART Commands determined by Feature Register value__________ 33
Table 4-1: Device Certifications _________________________________________________ 43
Table of Figures
Figure 1-1: Functional Block Diagram ______________________________________________ 8
Figure 1-2: Dimensions _________________________________________________________ 9
Figure 3-1: Power On RESET Timing _____________________________________________ 18
Datasheet
PSFCF1XXXXDXX
Revision A4
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1 Introduction
The Viking CompactFlash (CF) card is a multi-channel, high-performance
solution for a wide array of storage applications. Available in capacity ranges
from 128MB to 16GB with a standard CompactFlash interface, system designers
have an easy way to add small-form factor, reliable storage to any system at a
fraction of the size of a hard disk drive.
Vikings rugged industrial designed SSDs offer the highest flash storage
reliability and performance in harsh environments such as shock, vibration,
humidity, altitude, ESD, and extreme temperatures. Viking SSDs meet JEDEC
JESD22 standards and pass numerous qualifications including MIL-STDs and
NEBS.
Viking can also provide specialized services to OEMs designing customized
hardware and systems by offering:
Locked BOM control with customer product change notification (PCN)
Pre-installed software, custom software imaging and ID strings
Custom packaging and labeling
Comprehensive supply-chain management
Customer specified testing
30K volt ESD protection
Conformal coating
Localized Field Application Engineering for complete pre and post sale
technical support
1.1 Features
The main features of Viking CompactFlash memory controller are:
Dual channel flash interface
Full support for SLC NAND flash memories
Built-in ATA / PC card / CompactFlash Interface
Host data transfer rate in PIO mode 6 or MDMA mode 4 up to 25
MByte/sec
Host data transfer rate in UDMA mode 4 up to 66 MByte/s
Supports True-IDE mode
Patented power fail management
Embedded Reed-Solomon ECC, 4 symbols in a 512B sector
Advanced global wear leveling
Automatic power-down mode and sleep mode
Industrial and commercial temperature
Datasheet
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ESD protection
1.2 Performance
Table 1-1: CF Card Read/Write Performance
Parameter
Sequential Read
Sequential Write
Random Read
Random Write
Size
256K
256K
4K
4K
Value
up to 42 MB/s
up to 42 MB/s
up to 3098 IOPS
up to 23 IOPS
Note: 1) Measured using IOMETER 2008.

2) Performance may vary under extreme temperatures.
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1.3 CHS Parameters

Table 1-2: CHS Parameters
Capacity
128MB
256MB
512MB
1GB
2GB
4GB
8GB
16GB
32GB
Logical
Block
Addresses
(LBA)
248,832
497,664
1,037,232
2,043,216
3,992,688
8,009,568
15,983,856
32,105,808
64,028,160
Cylinders (C)
(standard)
Heads (H)
Sectors/Track
(S)
486
972
1,029
2,027
3,961
7,946
15,857
*31,851
*63520
16
16
16
16
16
16
16
16
16
63
63
63
63
63
63
63
63
63
Note: The unformatted capacity of the card may be less than the perceived or stated capacity on the label. Please use the
LBA count in this table for reference.
*16,383 is the max Cylinder size for True IDE mode. Use total LBA to calculate size when using True IDE mode.
1.4 Block Diagram

Figure 1-1: Functional Block Diagram
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1.5 Mechanical Information

Figure 1-2: Dimensions
Note: All dimensions are in inches.
Datasheet
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Note: All dimensions are in millimeters.
1.6 Interface
1.6.1 Host Interface
PCMCIA 2.1, PC Card ATA, CF 3.0, CF 4.1 standard compatible

ATA-6 standard compatible in True-IDE mode
Memory mapped or I/O operation
Fast ATA host-to-buffer transfer rates supporting PIO mode 6, MDMA
mode 4, UDMA mode 4 in True-IDE mode
Automatic sensing of PCMCIA or True-IDE host interface mode
Four integrated 8 Kbyte Sector Buffers and 256 Byte PCMCIA Attribute
Memory
PCMCIA Configuration Option Register, Card Configuration and Status
Register and Pin Replacement Register support
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2 Connector Pins
2.1 Connector Pin Assignments
Table 2-1: Connector Pin Assignments
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Signal Name
Mem / IO / True IDE
GND
D3
D4
D5
D6
D7
#CE1/#CE1/#CS0
A10
#OE/#ATA SEL
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP/#IOIS16/#IOCS16
#CD2
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal Name
Mem / IO / True IDE
#CD1
D11
D12
D13
D14
D15
#CE2/#CE2/#CS1
#VS1
#IORD
#IOWR
#WE
RDY/DREQ/HINT
VCC
CSEL
VS2
RESET/RESET/#RESET
#WAIT/#WAIT/IORDY
#INPACK
#REG
BVD2/#SPKR/#DASP
BVD1/#STSCHG/#PDIAG
D8
D9
D10
GND
2.2 Pin Function Description

Table 2-2: Pin Function Description
Signal
A0 ~ A10
Datasheet
PSFCF1XXXXDXX
Revision A4
PIN
Numbers
8, 10-12,
14-20
(Mode)
Function
(All)
Address
Type
(Note
1)
Description
Input
In I/O and Memory modes, these are the

Host Address lines that select the I/O port
address registers or the memory mapped
port address registers, and the control and
status registers. In True IDE mode, only A0
~ A2 are used to select the control, status
and data register; A3 ~ A10 are not used.
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(Mode)
Function
Type
(Note
1)
Signal
PIN
Numbers
#ATA SEL
BVD1 ~
BVD2
45, 46
CD1 ~ CD2
25, 26
(All)
Card Detect
Output
CE1 ~ CE2
7, 32
(I/O, Memory)
Card Enable
Input
ST,PU
CS0 ~ CS1
7, 32
(IDE)
Chip Select
Input
CSEL
39
(IDE)
Cable Select
Input
PU
D0 ~ D15
2-6, 2123, 2731, 47,

48
(All)
Host Data Bits
Input/
Output
DASP
45
DREQ
37
HINT
37
(IDE)
ATA Select
(Memory)
Battery
Voltage
Detect
(IDE)
Active/Slave
Present
(IDE)
DMA Request
(IDE)
Interrupt
Request
Input
Output
Input
PU
Grounded by host to enable True IDE

Mode.
Always asserted (high) since a battery is
not used in this card.
Internally grounded in card to signal host
that the card is fully inserted into the
socket.
Selects the card and indicates to the
controller whether a byte or word operation
is being performed. #CE2 always accesses
the odd byte of the word; #CE1 accesses
the even or odd byte of the word
depending on the status of AO and #CE2.
#CS0 selects the ATA Command Block
Registers; #CS1 selects the ATA Control
Block Registers.
Configures the drive as a Master or Slave.
If the signal is inactive (low), the drive is
configured as a Master. If the pin is open,
the drive is configured as a
slave.
These bi-directional signals carry the data,
commands, and status information
between the host and the controller.
Device active / Slave Present signal.
Output
DMA request
Output
Interrupt Request to the Host (active high).
INPACK
43
(I/O)
Input
Acknowledge
Output
IORDY
42
(IDE)
I/O Channel
Ready
Output
IOCS16
24
(IDE)
16 bit I/O
Output
Datasheet
PSFCF1XXXXDXX
Revision A4
Description
Asserted when the card is selected and

can respond to an I/O cycle at the address
on the bus. This signal is used by the host
to control the enable of any input data
buffers between the card and host system
data bus.
Active high I/O Channel Ready signal,
where a low signal indicates that the
controller is NOT ready and the host
should extend the cycle for the present
command.
Indicates a 16-bit transfer is in progress on
the host bus. Open collector output.
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Signal
PIN
Numbers
IOIS16
24
IORD
34
IOWR
35
(Mode)
Function
(I/O)
16 bit I/O
(I/O, IDE)
Input/Output
Read
(I/O, IDE)
Input/Output
Write
Type
(Note
1)
Output
Selects the 16-bit port. A low signal

indicates that a 16-bit port is being
addressed or an odd-byte-only operation
can be performed at the addressed
port.
Input
ST,PU
Clocks I/O data from the internal controller

to the card bus.
Input
ST,PU
Clocks I/O data from the card bus to the

internal controller.
OE
(I/O, Memory)
Output Enable
Input
ST,PU
PDIAG
46
(IDE)
Passed
Diagnostics
Output
PU
REG
44
(All)
Register
Memory
Select
Input
ST,PU
RESET
41
(I/O, Memory)
Reset
Input
PU
RESET
41
(IDE)
Reset
Input
PU
SPKR
45
STSCHG
46
VS1 ~ VS2
33, 40
WAIT
42
Datasheet
PSFCF1XXXXDXX
Revision A4
(I/O)
Speaker
(I/O)
Status
Changed
(All)
Voltage
Sense
(I/O, Memory)
Input/Output
Data Ready
Description
Output
Input /
Output
Output
Output
This input signal is used to enable Memory

Read data from the memory card. In
Memory mode it is used to read data and
the CIS and Configuration registers. In I/O
mode, this signal is used to read the CIS
and Configuration registers only.
Used between two drives to indicate that
the drive in Slave mode has passed
diagnostics.
In Memory mode, this input signal
distinguishes the register (attribute)
memory from the common memory. In I/O
mode, this signal must be asserted (low)
when the I/O address is on the bus. In True
IDE mode DMA Acknowledge is not used
in Compact Flash, and this signal should
be connected to VCC.
The controller is reset when this signal is
asserted (high), initializing the control and
status registers and aborting any command
in progress.
The controller is reset when this signal is
asserted (low), initializing the control and
status registers and aborting any command
in progress.
Always low; speaker not supported by the
card.
Indicates a change in RDY/#BSY or Write
Protect states.
VS1 is grounded to indicate 3.3V read
capability. VS2 is not used and not
connected.
In Memory and I/O modes, this output is
driven by the controller to signal the host to
insert a delay before completing a memory
or I/O cycle.
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Signal
PIN
Numbers
WE
36
WP
24
VCC
38
GND
50
(Mode)
Function
(I/O, Memory)
Write Enable
(Memory)
Write Protect
Voltage
Supply
Ground
Type
(Note
1)
Input
ST,PU
Output
Power
Gnd
Description
In Memory mode, strobes Memory Write
data into the card. In both Memory mode
and I/O mode, this signal is used for writing
the configuration register, in conjunction
with the #REG signal. Not used in IDE
mode, connect to VCC.
Indicates status of the cards Write Protect
switch. Not used on this card.
These pins supply 3.3V or 5V to the
Compact Flash.
These pins supply ground to the Compact
Flash.
Notes: 1. ST= Schmitt trigger input, PU= internal pullup, PD= internal pull down.
3 Product Specifications
3.1 Absolute Maximum Ratings
Table 3-1: Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
VCC
VIN
VOUT
-0.3 ~ 6.0
GND - 0.5 ~ VCC + 0.5
GND - 0.5 ~ VCC + 0.5
-40 to +85
V
V
V
c
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
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3.2 DC Operating Conditions and Characteristics

Recommended operating conditions (Voltages referenced to GND, TA = 0 to
70C)
Table 3-2: DC Operating Conditions and Characteristics
Parameter
Symbol
VCC
VCC
VIH
VIL
VOH
VOH
VOL
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Output low voltage
1 Flash
Device
2 Flash
Devices
4 Flash
Standby
Devices
Current
1 Flash
@
Device
5.0V,
25C
2 Flash
Devices
4 Flash
Devices
@
1 Flash
3.3V,
Device
25C
2 Flash
Devices
4 Flash
Operating
Devices
Current
1 Flash
@
Device
5.0V,
25C
2 Flash
Devices
4 Flash
Devices
Schmitt Trigger Input Low (3.3V/5V)
Schmitt Trigger Input High (3.3V/5V)
Pull-up resistance
Pull-down resistance
Min.
3.135
4.5
2.0
Typical
3.3
5.0
0.8
2.4
0.4
@
3.3V,
25C
Datasheet
PSFCF1XXXXDXX
Revision A4
Max.
3.465
5.5
0.5 + 0.05
0.5 + 0.10
0.5 + 0.20
ISTB
0.5 + .05
0.5 + 0.10
0.5 + 0.20
IOP
VTVT+
Rpu
Rpd
0.8
1.4
52.7
47.5
70 + 20
95 + 20
70 + 40
95 + 40
70 +
40.10
95 +
40.10
62.8 + 20
82.8 + 20
62.8 + 40
82.8 + 40
62.8 +
40.10
82.8 +
40.10
1.2
2.0
141
172
1.6
Unit
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
kohm
kohm
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3.3 Environmental Specifications

Table 3-3: Environmental Specifications
Parameter
Operating Temperature (Commercial
Temp):
Operating Temperature (Industrial
Temp):
Humidity (non-condensing):
Vibration (operating / non-operating)
Shock (operating / non-operating)
Altitude
Value
0 to 70c
-40 to 85c
5% to 95% non-condensing
20G peak, 20Hz-2000Hz, 4 cycles per direction (per
JEDEC JESD22 standard, method B103)
1,500G peak, 0.5ms pulse duration, five (5) pulses per
each of six (6) directions (per JEDEC JESD22 standard,
method B110)
Up to 80,000 ft.
3.4 Reliability & Retention

Table 3-4: CF Card Reliability and Retention
Parameter
Data Reliability
Data Retention
Value
Bit Error rate 10E-15
10 Years
3.5 Capacitance
Table 3-5: Capacitance
Parameter
Input capacitance
Output capacitance
Symbol
Cin
Cout
Min.
-
Max.
10
10
Unit
pF
pF
3.6 AC Characteristics
Input rise and fall time requirements: Input rise and fall time should be 10ns or
less.
3.6.1 Power-on Timing

Table 3-6: Power-on Timing
Parameter
Card Enable setup time
Datasheet
PSFCF1XXXXDXX
Revision A4
Symbol
tsu(VCC)
Min.
-
Max.
-
Unit
ms
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VCC rise time 10% to 90%

Host RESET Hi-z hold time
Host RESET width
Host RESET setup time
Datasheet
PSFCF1XXXXDXX
Revision A4
tpr
th(Hi-z
RESET)
tw(RESET)
tsu(RESET)
150
-
250
-
ms
ms
us
ms
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Figure 3-1: Power On RESET Timing
Optional (requires bill of

material change)
tsu(VCC) = 25ms
tpr = N/A
th(Hi-z RESET) = 5ms
tw(RESET) = 10us
tsu(RESET)
3.6.2 Attribute Memory Read Timing

Table 3-7: Attribute Memory Read Timing
Parameter
Read Cycle Time
Address Access Time
Card Enable Access Time
Output Enable Access Time
Output Disable Time from Cex
Output Disable Time from HOE
Address Setup Time
Output Enable Time from Cex
Output Enable Time from OE
Data Valid from Address Change
Symbol
tc(R)
ta(A)
ta(Cex)
ta(OE)
tdis(Cex)
tdis(OE)
tsu (A)
ten(Cex)
ten(OE)
tv(A)
Min.
300
Max.
300
300
150
100
100
30
5
5
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.6.3 Attribute Memory Write Timing

Table 3-8: Attribute Memory Write Timing
Symbol
Min.
Max.
Unit
Parameter
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Write Cycle Time

Write Pulse Width
Address Setup Time
Data Setup Time (-WE)
Data Hold Time
Write Recovery Time
Datasheet
PSFCF1XXXXDXX
Revision A4
tc(W)
tw(WE)
tsu(A)
tsu(D-WEH)
th(D)
trec(WE)
250
150
30
80
30
30
ns
ns
ns
ns
ns
ns
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3.6.4 Common Memory Read Timing

Table 3-9: Common Memory Read Timing
Cycle Time Mode
Parameter
Symbol
Output Enable
Access Time
Output Disable Time
from
Address Setup Time
Address Hold Time
CE Setup before OE
CE Hold following
OE
Wait Delay Falling
from OE
Data Setup for Wait
Release
Wait Width Time2

Notes:
1.
2.
ta(OE)
250 ns
Min
Max
(ns)
(ns)
125
tdis(OE)
tsu(A)
th(A)
tsu(CE)
th(CE)
120ns
Min Max
(ns) (ns)
60
100
30
20
0
20
100ns
Min Max
(ns) (ns)
50
60
15
15
0
15
80ns
Min
Max
(ns)
(ns)
45
50
10
15
0
15
45
10
10
0
10
tv(WTOE)
35
35
na1
tv(WT)
na1
tw(WT)
350
350
350
na1
-WAIT is not supported in this mode

The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are
in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card or CF+ Card to the system.
The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max
Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the
PCMCIA PC Card specification of 12s but is intentionally less in this specification.
Datasheet
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Page 20 of 43
3.6.5 Common Memory Write Timing

Table 3-10:Common Memory Write Timing
Cycle Time Mode
Parameter
Symbol
Data setup before
WE
Data hold following
WE
WE pulse Width
Address setup Time
CE setup before
WE
Write recovery time
Address holdtime
CE Hold following
WE
Wait delay falling from
WE
WE high from wait
release
Wait Width Time2

Notes:
1.
2.
tsu (DWEH)
th(D)
250 ns
Min
Max
(ns)
(ns)
80
120ns
Min
Max
(ns)
(ns)
50
100ns
Min Max
(ns) (ns)
40
80ns
Min
Max
(ns)
(ns)
30
30
15
10
10
tw(WE)
tsu(A)
tsu(CE)
150
30
0
70
15
0
60
10
0
55
10
0
trec(WE)
th(A)
Th(CE)
30
20
20
15
15
15
15
15
15
15
15
10
na1
tv(WT-WE)
tv(WT)
tw(WT)
0
350
na1
0
350
350
na1
-WAIT is not supported in this mode

The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are
in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT
signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width
time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card
specification of 12s but is intentionally less in this specification.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 21 of 43
3.6.6 I/O Mode Read Timing

Table 3-11: I/O Mode Read Timing
Cycle Time Mode
Parameter
Symbol
Data delay after IORD
Data hold following
IORD
IORD width time
Address setup before
IORD
Address hold following
IORD
CE setup before IORD
CE hold following
IORD
REG setup before
IORD
REG hold following
IORD
INPACK delay falling
from IORD
INPACK delay rising
from IORD
IOIS16 delay falling
from address3
IOIS16 delay rising
from address3
WAIT delay falling
from IORD3
Data delay from WAIT
rising3
WAIT width time3
Notes:
1.
2.
3.
td(IORD)
th(IORD)
250ns
Min Max
(ns) (ns)
100
0
120ns
Min Max
(ns) (ns)
50
5
100ns
Min Max
(ns) (ns)
50
5
80ns
Min Max
(ns) (ns)
45
5
tw(IORD)
tsuA(IORD)
165
70
70
25
65
25
55
15
thA(IORD)
20
10
10
10
tsuCE(IORD)
thCE(IORD)
5
20
5
10
5
10
5
10
tsuREG(IORD)
thREG(IORD)
tdfINPACK(IOR
D)
tdrINPACK(IOR
D)
tdfIOIS16(ADR)
45
na1
na1
na1
45
na1
na1
na1
35
na1
na1
na1
tdrIOIS16(ADR)
35
na1
na1
na1
tdWT(IORD)
35
35
35
na2
td(WT)
na2
td(WT)
350
350
350
na2
-IOIS16 and -INPACK are not supported in this mode.

-WAIT is not supported in this mode.
Maximum load on -WAIT, -INPACK and -IOIS16 is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total
load. All times are in nanoseconds. Minimum time from -WAIT high to -IORD high is 0 nsec, but minimum IORD width shall still be met. Dout signifies data provided by the CompactFlash Storage Card or CF+ Card to
the system. Wait Width time meets PCMCIA PC Card specification of 12s but is intentionally less in this
specification.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 22 of 43
3.6.7 I/O Mode Write Timing

Table 3-12: I/O Mode Write Timing
Cycle Time Mode
Parameter
Symbol
Data setup after
IOWR
Data hold following
IOWR
IOWR width time
Address setup
before IOWR
Address hold
following IOWR
CE setup before
IOWR
CE hold following
IOWR
REG setup before
IOWR
REG hold following
IOWR
IOIS16 delay falling
from address3
IOIS16 delay rising
from address3
WAIT delay falling
from IOWR3
IOWR high from
wait high3
WAIT width time3
Datasheet
PSFCF1XXXXDXX
Revision A4
tsu(IOWR)
250ns
Min
Max
(ns)
(ns)
60
120ns
Min
Max
(ns)
(ns)
20
100ns
Min Max
(ns) (ns)
20
80ns
Min Max
(ns) (ns)
15
th(IOWR)
30
10
tw(IOWR)
tsuA(IOWR)
165
70
70
25
65
25
55
15
thA(IOWR)
20
20
10
10
tsuCE(IOWR)
thCE(IOWR)
20
20
10
10
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
35
na1
na1
na1
tdrIOIS16(ADR)
35
na1
na1
na1
tdWT(IOWR)
35
35
35
na2
tdrIOWR(WT)
td(WT)
0
350
na2
0
350
350
na2
01/09/2012
Viking Technology
Page 23 of 43
3.6.8 True IDE Mode PIO Read/Write Timing

Table 3-13: True IDE Mode PIO Read/Write Timing (Modes 0-6)
Mode
0
Mode
1
Mode
2
Mode
3
Mode
4
Mode
5
Mode
6
Notes
Cycle Time (min)

Address valid to -IORD/IOWR (min)
600
70
383
50
240
30
180
30
120
25
100
15
80
10
-IORD/-IOWR (min)
-IORD/-IOWR (min)
t2
Register (8 bit)
-IORD/-IOWR
t2i
recovery time (min)
-IOWR data setup
t3
(min)
-IOWR data hold
t4
(min)
-IORD data setup
t5
(min)
-IORD data hold
t6
(min)
T6 -IORD data tristate
Z (max)
Address valid to t7 IOCS16 assertion
(max)
Address valid to t8 IOCS16 released
(max)
-IORD/-IOWR to
t9
address valid hold
Read Data Valid to
tR IORDY active (min),
D if IORDY initially low
after tA
tA IORDY Setup time
IORDY Pulse Width
tB
(max)
IORDY assertion to
tC
release (max)
165
29
125
290
100
290
80
80
70
70
65
65
55
55
1
1
70
25
25
20
60
45
30
30
20
20
15
30
20
15
10
10
50
35
20
20
20
15
10
30
30
30
30
30
20
20
90
50
40
n/a
n/a
n/a
n/a
60
45
30
n/a
n/a
n/a
n/a
20
15
10
10
10
10
10
35
35
35
35
35
1250
1250
1250
1250
1250
n/a5
n/a5
n/a5
n/a5
n/a5
n/a5
Parameter
t0
t1
t2
Notes: All timings are in ns.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 24 of 43
1.
2.
3.
4.
5.
t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command
recovery time or command inactive time. The actual cycle time equals the sum of the actual command active
time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The
minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation
can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the
devices identify device data. A CompactFlash Storage Card implementation shall support any legal host
implementation.
This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer
driven by the CompactFlash Storage Card (tri-state).
The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive
then the host shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash
Storage Card is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met
and tRD is not applicable. If the CompactFlash Storage Card is driving IORDY negated at the time tA after the
activation of -IORD or -IOWR, then tRD shall be met and t5 is not applicable.
t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
IORDY is not supported in this mode.
3.6.9 True IDE Multiword DMA Read/Write Timing

Table 3-14: True IDE Multiword DMA Read/Write Timing (Modes 0-4)
Parameter
tO
tD
tE
tF
tG
tH
tI
tJ
tKR
tKW
tLR
tLW
tM
tN
tZ
Notes:
1.
Cycle time (ns)

-IORD / -IOWR asserted width
(min)
-IORD data access (max)
-IORD data hold (min)
-IORD / IOWR data setup (min)
-IOWR data hold (min)
DMACK to -IORD / -IOWR
setup (min)
-IORD / -IOWR to DMACK
hold (min)
-IORD negated width (ns)
-IOWR negated width (ns)
-IORD to DMARQ delay (max)
-IOWR to DMARQ delay (max)
CE(1:0) valid to IORD / IOWR
CE(1:0) hold
-DMACK
Mode
0
(ns)
480
215
Mode
1
(ns)
150
80
Mode
2
(ns)
120
70
Mode
3
(ns)
100
65
Mode
4
(ns)
Note
80
55
1
1
150
5
100
20
0
60
5
30
15
0
50
5
20
10
0
50
5
15
5
0
45
5
10
5
0
20
50
215
120
40
50
15
20
50
50
40
40
30
10
25
25
25
35
35
25
10
25
25
25
35
35
10
10
25
20
20
35
35
5
10
25
1
1
t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the
minimum command recovery time or command inactive time for input and output cycles respectively. The actual
cycle time equals the sum of the actual command active time and the actual command inactive time. The three
timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement is greater
than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host implementation
can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is equal to or greater
than the value reported in the devices identify device data. A CompactFlash Storage Card implementation shall
support any legal host implementation.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 25 of 43
3.6.10
Ultra DMA AC Characteristics
Table 3-15: Ultra DMA AC Characteristics

Symbol
t2CYCTYP (min)
tCYC (min)
t2CYC (min)
tDS (min)
tDH (min)
tDVS (min)
tDVH (min)
tCS (min)
tCH (min)
tCVS (min)
tCVH (min)
tZFS (min)
tDZFS (min)
tFS (max)
tLI (min)
tLI (max)
tMLI (min)
tUI (min)
tAZ (max)
tZAH (min)
tZAD (min)
tENV (min)
tENV (max)
tRFS (max)
tRP (min)
tIORDYZ (max)
tZIORDY (min)
tACK (min)
tSS (min)
UDMA0
(ns)
UDMA1
(ns)
UDMA2
(ns)
UDMA3
(ns)
UDMA4
(ns)
240
112
230
15.0
5.0
70.0
6.2
15.0
5.0
70.0
6.2
0
70.0
230
0
150
20
0
10
20
0
20
70
75
160
20
0
20
50
160
73
153
10.0
5.0
48.0
6.2
10.0
5.0
48.0
6.2
0
48.0
200
0
150
20
0
10
20
0
20
70
70
125
20
0
20
50
120
54
115
7.0
5.0
31.0
6.2
7.0
5.0
31.0
6.2
0
31.0
170
0
150
20
0
10
20
0
20
70
60
100
20
0
20
50
90
39
86
7.0
5.0
20.0
6.2
7.0
5.0
20.0
6.2
0
20.0
130
0
100
20
0
10
20
0
20
55
60
100
20
0
20
50
60
25
57
5.0
5.0
6.7
6.2
5.0
5.0
6.7
6.2
0
6.7
120
0
100
20
0
10
20
0
20
55
60
100
20
0
20
50
Measure
location
(see
Note2)
Sender
Note3
Sender
Recipient
Recipient
Sender
Sender
Device
Device
Host
Host
Device
Sender
Device
Note4
Note4
Host
Host
Note5
Host
Device
Host
Host
Sender
Recipnt
Device
Device
Host
Sender
Notes:
1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement
location column. For example, in the case of tRFS, both STROBE and -DMARDY transitions are measured at
the sender connector.
3) The parameter tCYC shall be measured at the recipients connector farthest from the sender.
4) The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an
incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing
response shall be measured at the same connector.
5) The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but
must release the bus to allow for a bus turnaround.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 26 of 43
3.6.11
Ultra DMA Data Burst Timing Descriptions
Table 3-16: Ultra DMA Data Burst Timing Descriptions

Name
Comment
t2CYCTYP Typical sustained average two cycle time

Cycle time allowing for asymmetry and clock variations (from
tCYC
STROBE edge to STROBE edge)
Two cycle time allowing for clock variations (from rising edge to
t2CYC
next rising edge or from falling edge to next falling edge of
STROBE)
Data setup time at recipient (from data valid until STROBE
tDS
edge)
Data hold time at recipient (from STROBE edge until data may
tDH
become invalid)
Data valid setup time at sender (from data valid until STROBE
tDVS
edge)
Data valid hold time at sender (from STROB3E edge until data
tDVH
may become invalid)3
tCS
CRC word setup time at device
tCH
CRC word hold time device
CRC word valid setup time at host (from CRC valid until tCVS
DMACK negation)
CRC word valid hold time at sender (from -DMACK negation
tCVH
until CRC may become invalid)
Time from STROBE output released-to-driving until the first
tZFS
transition of critical timing.
Time from data output released-to-driving until the first
tDZFS
transition of critical timing.
First STROBE time (for device to first negate DSTROBE from
tFS
STOP during a data in burst)
tLI
Limited interlock time
tMLI
Interlock time with minimum
tUI
Unlimited interlock time
Maximum time allowed for output drivers to release (from
tAZ
asserted or negated)
tZAH
Minimum delay time required for output
tZAD
Drivers to assert or negate (from released)
Envelope time (from -DMACK to STOP and -HDMARDY during
tENV
data in burst initiation and from DMACK to STOP during data
out burst initiation)
Datasheet
PSFCF1XXXXDXX
Revision A4
Notes
2, 5
2, 5
3
3
2
2
3
3
1
1
1
01/09/2012
Viking Technology
Page 27 of 43
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
Ready-to-final-STROBE time (no STROBE edges shall be sent

this long after negation of -DMARDY)
Ready-to-pause time (that recipient shall wait to pause after
negating -DMARDY)
Maximum time before releasing IORDY
Minimum time before driving IORDY
Setup and hold times for -DMACK (before assertion or
negation)
Time from STROBE edge to negation of DMARQ or assertion
of STOP (when sender terminates a burst)
6
4, 6
Notes:
1. The parameters tUI, tMLI (in Figure 36: Ultra DMA Data-In Burst Device Termination Timing and Figure 37: Ultra
DMA Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks,
i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.
tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum.
tLI is a limited time-out that has a defined maximum.
2. 80-conductor cabling (see 4.3.8.4) shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in
modes greater than 2.
3. Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector
where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these
timing measurements are not valid in a normally functioning system.
4. For all timing modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on
IORDY- giving it a known state when released.
5. The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration
with a single device located at the end of the cable. This could result in the minimum values for tDS and tDH for mode
5 at the middle connector being 3.0 and 3.9 ns respectively.
6. This parameter applies to True IDE mode operation only.
3.6.12
CF-ATA Command Support
Table 3-17: CF-ATA Command Support

No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Command
Check Power Mode
Erase Sector
Execute Drive Diagnostic
Flush Cache
Format Track
Identify Drive
Idle
Idle Immediate
Initialize Drive Parameters
Media Lock
Media Unlock
NOP
Read Buffer
Read DMA
Read Multiple
Read Long
Read Native Max Address
Read Sector(s)
Read Verify Sector(s)
Datasheet
PSFCF1XXXXDXX
Revision A4
Code
E5h, 98h
C0h
90h
E7h
50h
ECh
E3h, 97h
E1h, 95h
91h
DEh
DFh
00h
E4h
C8h, C9h
C4h
22h, 23h
F8h
20h, 21h
40h, 41h
FR
--------------------
SC
-Y
--Y
-Y
-Y
----Y
Y
--Y
Y
SN
-Y
-----------Y
Y
Y
-Y
Y
CY
-Y
--Y
--------Y
Y
Y
-Y
Y
DR
Y
Y
-Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
-Y
--Y
---Y
----Y
Y
Y
-Y
Y
LBA
-Y
--Y
--------Y
Y
Y
-Y
Y
01/09/2012
Viking Technology
Page 28 of 43
No.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Command
Recalibrate
Request Sense
Security Disable Password
Security Erase Prepare
Security Erase Unit
Security Freeze Lock
Security Set Password
Security Unlock
Seek
Set Feature
Set Max Address
Set Multiple Mode
Set Sleep Mode
SMART
Standby
Standby Immediate
Translate Sector
Write Buffer
Write DMA
Write Long
Write Multiple
Write Multiple w/o Erase
Write Sector(s)
Write Sector(s) w/o Erase
Write Verify
Code
1Xh
03h
F6h
F3h
F4h
F5h
F1h
F2h
7Xh
EFh
F9h
C6h
E6h, 99h
B0h
E2h, 96h
E0h, 94h
87h
E8h
CAh, CBh
32h, 33h
C5h
CDh
30h, 31h
38h
3Ch
FR
--------Y
----Y
------------
SC
---------Y
Y
Y
-Y
Y
-Y
-Y
-Y
Y
Y
Y
Y
SN
---------Y
Y
-----Y
-Y
Y
Y
Y
Y
Y
Y
CY
---------Y
Y
--Y
--Y
-Y
Y
Y
Y
Y
Y
Y
DR
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
---------Y
Y
-----Y
-Y
Y
Y
Y
Y
Y
Y
LBA
---------Y
Y
-----Y
-Y
Y
Y
Y
Y
Y
Y
Notes: Abbreviations in this table:
FR: Features Register
SC: Sector Count Register (00h FFh; 00h means 256 sectors
SN: Sector Number Register
CY: Cylinder Low/ High Register
DR: Drive bit of Drive/Head Register
HD: Head Number (0-15) of Drive/ Head Register
LBA: Logic Block Address Mode Support
--: Not used for this command
Y: Used for this command
3.7 Capacity Information

3.7.1 True IDE Mode
Table 3-18: True IDE Mode
Card Size
Cylinders
(Note 1)
Head
Sector
Total Sectors
(Note 2, 3)
128MB
256MB
512MB
1GB
2GB
4GB
486
972
1029
2027
3961
7946
16
16
16
16
16
16
32
32
63
63
63
63
248,832
497,664
1,037,232
2,043,216
3,992,688
8,009,568
Datasheet
PSFCF1XXXXDXX
Revision A4
Usable
Capacity
(bytes)
127,401,984
254,803,968
531,062,784
1,046,126,592
2,044,256,256
4,100,898,816
01/09/2012
Viking Technology
Page 29 of 43
8GB
16GB
32GB
Notes:
1.
2.
3.
15857
16383 *
16383 *
16
16
16
63
63
63
15,983,856
32,105,808
64,028,160
8,183,734,272
16,438,173,700
32,782,417,920
16,383 is the max Cylinder size for True IDE mode. Use total sectors to calculate size.
Total sectors remaining after deducting firmware and spare block overhead.
Available data capacity is dependent on format and partition type.
3.7.2 PCMCIA Mode (I/O and Memory Modes)

Table 3-19: PCMCIA Mode (I/O and Memory Modes)
Card Size
128MB
256MB
512MB
1GB
2GB
4GB
8GB
16GB
32GB
Notes:
1.
2.
Cylinders
(Note 1)
486
972
1029
2027
3961
7946
15857
31851
63520
Head
Sector
16
16
16
16
16
16
16
16
16
32
32
63
63
63
63
63
63
63
Total Sectors
(Note 2, 3)
248,832
497,664
1,037,232
2,043,216
3,992,688
8,009,568
15,983,856
32,105,808
64,028,160
Usable Capacity
(bytes)
127,401,984
254,803,968
531,062,784
1,046,126,592
2,044,256,256
4,100,898,816
8,183,734,272
16,438,173,700
32,782,417,920
Total sectors remaining after deducting firmware and spare block overhead.
Available data capacity is dependent on format and partition type.
3.8 Identify Drive Parameter

An example of the parameter information received from the CF Card when
invoking the Identify Drive command (ECh) is listed in table below:
Table 3-20: Identify Drive Parameter
Word
Address
0
1
2
3
4
5
6
7-8
9
10 - 19
20
21
22
23 - 26
27 - 46
Datasheet
PSFCF1XXXXDXX
Revision A4
Default
Value
045AH
XXXXH
0000H
00XXH
0000H
0200H
XXXXH
XXXXH
0000H
XXXXH
0002H
0001H
0004H
XXXXH
XXXXH
Bytes
2
2
2
2
2
2
2
4
2
20
2
2
2
8
40
Data Field Type Information

General configuration bit-significant information
Default number of cylinders
Reserved
Default number of heads
Number of unformatted bytes per track
Number of unformatted bytes per sector
Default number of sectors per track
Number of sectors per CF Card
Reserved
Serial Number in ASCII (20 characters)
Buffer type (dual-ported multi-sector)
Buffer size in 512 byte increments
# of ECC bytes passed on Read/Write Long commands
Firmware revision (8 ASCII characters)
Model Number in ASCII (40 characters)
01/09/2012
Viking Technology
Page 30 of 43
Word
Address
47
48
49
50
51
52
53
54
55
56
57 - 58
59
60 - 61
62
63
64
65
66
67
68
69 - 79
80
81
Default
Value
8001H
0000H
0F00H
4001H
0200H
0000H
0007H
XXXXH
XXXXH
XXXXH
XXXXH
010XH
XXXXH
0000H
0X0XH
0003H
0078H
0078H
0078H
0078H
0000H
0020H
0000H
82
740BH
83
84
5004H
4000H
2
2
85
740XH
86
87
88
89
90
91
92
93
94 127
128
1004H
4000H
XXXXH
0000H
0000H
0000H
XXXXH
XXXXH
0000H
0XXXH
2
2
2
2
2
2
2
2
72
2
129
XX00H
XXXXH
848AH
045AH
2
2
130
133
134
135
Datasheet
PSFCF1XXXXDXX
Revision A4
Bytes
2
2
2
2
2
2
2
2
2
2
4
2
4
2
2
2
2
2
2
2
22
2
2
Maximum 1 sector on Read/Write Multiple command

Double Word not supported
Capabilities: DMA, LBA, IORDY supported
Capabilities: device specific standby timer minimum
PIO data transfer cycle timing mode 2
DMA data transfer cycle timing mode not supported
Data Fields 54 58, 64 70, and 88 are valid
Number of Current Logical Cylinders
Number of Current Logical Heads
Number of Current Logical Sectors Per Track
Current Capacity in Sectors
Multiple sector setting is valid
Total number of sectors addressable in LBA Mode
Single word DMA transfer not implemented
Multiword DMA transfer mode
Advanced PIO modes supported (modes 3 and 4)
Minimum multiword DMA cycle time, 0 if no MDMA
Recommended multiword DMA cycle time, 0 if no MDMA
Minimum PIO cycle time without flow control
Minimum PIO cycle time with flow control
Reserved
Major version number, ATA-5 support
Minor version number, not reported
Command set: NOP, READ BUFFER, WRITE BUFFER, host
protected area, power management feature set, Security
Mode feature set, SMART feature set
Command set: FLUSH CACHE, CFA feature set
Command set/feature supported extension
Command set enabled: NOP, READ BUFFER, WRITE
BUFFER, host protected area, power management feature
set, Security Mode feature set enabled/disabled, SMART
feature set enabled/disabled
Command set enabled: FLUSH CACHE, CFA feature set
Command set/feature default
UDMA mode
Time for Security Erase Unit not specified
Time for Enhanced Security Erase Unit not specified
Reserved
Master Password Revision Code
Hardware Reset Result
Reserved
Security Status
Write Protect Status. Bit 15 = permanent write protect, no
more spare blocks available
Firmware date string
General Configuration word for PCMCIA mode
General Configuration word for True-IDE mode
01/09/2012
Viking Technology
Page 31 of 43
Word
Address
136
141
142
147
148
153
154
159
160
161
162
163
164
165
254
255
Datasheet
PSFCF1XXXXDXX
Revision A4
Default
Value
Bytes
XXXXH
12
XXXXH
12
XXXXH
12
0000H
12
A064H
0000H
0000H
XXXXH
001BH
2
2
2
2
2
0000H
180
XXA5H

Firmware file name
Preformat file name
Anchor program file name
Reserved
CFA Power Mode: no power level 1, max 100mA
Reserved
Key Management Schemes: CPRM not supported
CFA advanced modes: supported and enabled bits
CFA advanced modes: 80ns I/O and Memory supported
Reserved
Integrity Word
01/09/2012
Viking Technology
Page 32 of 43
Table 3-21: Identify Drive Parameter Table in PCMCIA mode showing word
differences
Word
Address
0
49
63
65
66
93
163 164
Default
Value
848AH
0E00H
0000H
0000H
0000H
0000H
0000H
Bytes
2
2
2
2
2
2
4

General configuration bit-significant information
Capabilities: LBA, IORDY supported
Multi Word DMA transfer mode not supported
Minimum Multi Word DMA cycle time
Recommended Multi Word DMA cycle time
Hardware Reset Result not supported
CFA advanced modes: not supported
Table 3-22: Identify Drive Parameter Table in PCMCIA mode showing word
differences
Word
Address
Default
Value
Bytes
83
86
160-164
5000H
1000H
0000H
2
2
10

Command set: FLUSH CACHE
Command set enabled: FLUSH CACHE
Reserved
3.9 SMART Support

The Viking Firmware supports the following SMART commands, determined by
the Feature Register value.
Table 3-23: Supported SMART Commands determined by Feature Register
value
Value
D0h
D1h
D2h
D8h
D9h
DAh
E0h
E1h
Command
SMART Read Data
SMART Read Attribute Thresholds
SMART Enable/Disable Attribute Autosave
SMART Enable Operations
SMART Disable Operations
SMART Return Status
SMART Read Remap Data
SMART Read Wear Level Data
SMART commands with Feature Register values not mentioned in the above
table are not
supported, and will be aborted.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 33 of 43
3.9.1 SMART Enable Operations

COMMAND CODE | B0h with a Feature Register value of D8h
PROTOCOL | Non-data.
INPUTS |
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
D8h
4Fh
C2h
1
D
B0h
NORMAL OUTPUTS | None required.

ERROR OUTPUTS | Aborted if the signature in the Cylinder registers is invalid.
DESCRIPTION | This command enables access to the SMART capabilities of the
firmware. The state of SMART (enabled or disabled) is preserved across power
cycles.
3.9.2 SMART Disable Operations

INPUTS |
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
D9h
4Fh
C2h
1
D
B0h

ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, or if SMART is not enabled.
DESCRIPTION | This command disables access to the SMART capabilities of
the firmware. The state of SMART (enabled or disabled) is preserved across
power cycles.
3.9.3 SMART Enable/Disable Attribute Autosave

INPUTS |
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 34 of 43
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
3
D2h
00h or F1h
4Fh
C2h
1
D
B0h

DESCRIPTION | This command is effectively a no-operation as the data for the
SMART functionality is always available and kept current in the firmware.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 35 of 43
3.9.4 SMART Read Data

PROTOCOL | PIO data in.
INPUTS |
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
D0h
4Fh
C2h
1
D
B0h

DESCRIPTION | This command returns one sector of SMART data. The data
structure returned is:
Offset
0..1
2..361
362
363
364..365
366
367
368..369
370
371
372
373
374..385
386..387
388..391
392..395
396
397
398..510
511
Value
0004h
00h
00h
0000h
00h
00h
0003h
00h
00h
00h
00h
00h
0002h
00h
Description
SMART structure version
Attribute entries 1 to 30 (12 bytes each)
Off-line data collection status (no off-line data collection)
Self-test execution status byte (self-test completed)
Total time to complete off-line data collection
Off-line data collection capability (no off-line data collection)

SMART capabilities
Error logging capability (no error logging)
Short self-test routine recommended polling time

Extended self-test routine recommended polling time
Reserved
SMART Version
Firmware Commit counter
Firmware Wear Level Threshold
Global Wear Leveling active
Global Bad Block Management active
Data structure checksum
There are six attributes that are defined for the firmware. These return their data
in the attribute section of the SMART data, using a 12 byte data field.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 36 of 43
The field at offset 386 gives a version number for the contents of the SMART
data structure. For the controller, only version 2 is defined.
The byte at offset 396 is 0 if the wear leveling has not yet started its global
operation and 1 if the global wear leveling has started. This happens when the
most used chip has reached the erase count threshold defined in the Erase
Count Attribute.
The byte at offset 397 is 0 if the bad block management is still working chip local,
and 1 if the global bad block management has started. This happens when one
of the flash chips runs out of spare blocks, in this case spare blocks from
different flash chips are used.
3.9.4.1 Spare Block Count Attribute
This attribute gives information about the amount of available spare blocks.
Offset
0
1..2
3
Value
196
0003h
4..5
6..7
8..9
10..11
Description
Attribute ID Reallocation Count
Flags Pre-fail type, attribute value is updated during normal operation
Attribute value. The value returned here is the percentage of remaining
spare blocks summed over all flash chips, i.e. (100 x current spare
blocks / initial spare blocks)
Initial number of spare blocks of the flash chip with the lowest current
number of spare blocks
Current number of spare blocks of the flash chip with the lowest current
number of spare blocks
Sum of the initial number of spare blocks for all flash chips
Sum of the current number of spare blocks for all flash chips
3.9.4.2 Erase Count Attribute

This attribute gives information about the amount of flash block erases that have
been performed.
Offset
0
1..2
3
4..11
Value
229
000Xh
Description
Attribute ID Erase Count Usage (vendor specific)
Flags Pre-fail or Advisory type, attribute value is updated during
normal operation
Attribute value. The value returned here is an estimation of the
remaining card life, in percent, based on the number of flash block
erases compared to the target number of erase cycles per block.
Estimated total number of block erases
This attribute is used for the SMART Return Status command. If the attribute
value field is less than the erase count threshold, the SMART Return Status
command will indicate a threshold exceeded condition.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 37 of 43
3.9.4.3 Total ECC Errors Attribute

This attribute gives information about the total number of ECC errors that have
occurred on flash read commands. This attribute is not used for the SMART
Return Status command.
Offset
0
1..2
Value
203
0002h
3
4..7
8..11
64h
Description
Attribute ID Number of ECC errors
Flags Advisory type, attribute value is updated during normal
operation
Attribute value. This value is fixed at 100.
Total number of ECC errors (correctable and uncorrectable)
3.9.4.4 Correctable ECC Errors Attribute

This attribute gives information about the total number of correctable ECC errors
that have occurred on flash read commands. This attribute is not used for the
SMART Return Status command.
Offset
0
1..2
Value
204
0002h
3
4..7
8..11
64h
Description
Attribute ID Number of corrected ECC errors
operation
Total number of ECC errors (correctable and uncorrectable)
3.9.4.5 Total Number of Reads Attribute

This attribute gives information about the total number of flash read commands.
This can be useful for the interpretation of the number of correctable or total ECC
errors. This attribute is not used for the SMART Return Status command.
Offset
0
1..2
Value
232
0002h
3
4..11
64h
Datasheet
PSFCF1XXXXDXX
Revision A4
Description
Attribute ID Number of Reads
operation
Total number of flash read commands
01/09/2012
Viking Technology
Page 38 of 43
3.9.4.6 UDMA CRC Errors Attribute

This attribute gives information about the total number of UDMA CRC errors that
have occurred on flash read commands. This attribute is not used for the SMART
Return Status command.
Offset
0
1..2
Value
199
0002h
3
4..7
8..11
64h
Description
Attribute ID UDMA CRC error rate
operation
Total number of UDMA CRC errors
3.9.5 SMART Read Attribute Thresholds

INPUTS |
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
D1h
4Fh
C2h
1
D
B0h

DESCRIPTION | This command returns one sector of SMART attribute
thresholds. The data structure returned is:
Offset
0..1
2..361
362..379
380..510
511
Value
0004h
0002h
00h
00h
Description
SMART structure version
Attribute threshold entries 1 to 30 (12 bytes each)
Reserved
Data structure checksum
3.9.5.1 Spare Block Count Attribute Threshold

Offset
0
1
2..11
Datasheet
PSFCF1XXXXDXX
Revision A4
Value
196
00h
Description
Attribute ID Reallocation Count
Factory Programmed Spare Block Count Threshold
Reserved
01/09/2012
Viking Technology
Page 39 of 43
3.9.5.2 Erase Count Attribute Threshold

Offset
0
1
2..11
Value
229
00h
Description
Attribute ID Erase Count Usage
Factory Programmed Erase Count Threshold
Reserved
3.9.5.3 Total ECC Errors Attribute Threshold

Offset
0
1
2..11
Value
203
00h
00h
Description
Attribute ID Number of ECC errors
No threshold for the Total ECC Errors Attribute
Reserved
3.9.5.4 Correctable ECC Errors Attribute

Offset
0
1
2..11
Value
204
00h
00h
Description
Attribute ID Number of corrected ECC errors
No threshold for the Correctable ECC Errors Attribute
Reserved
3.9.5.5 Total Number of Reads Attribute

Offset
0
1
2..11
Value
232
00h
00h
Description
Attribute ID Number of Reads
No threshold for the Total Number of Reads Attribute
Reserved
3.9.5.6 UDMA CRC Errors Attribute

Offset
0
1
2..11
Value
199
00h
00h
Description
Attribute ID UDMA CRC error rate
No threshold for the UDMA CRC Errors Attribute
Reserved
3.9.6 SMART Return Status

COMMAND CODE | B0h with a Feature Register value of DAh
INPUTS |
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Datasheet
PSFCF1XXXXDXX
Revision A4
DAh
4Fh
C2h
1
01/09/2012
Viking Technology
Page 40 of 43
Command
B0h
NORMAL OUTPUTS | Returns a status indication as described below.

DESCRIPTION | This command checks the device reliability status. If a threshold
exceeded condition exists for either the Spare Block Count attribute or the Erase
Count attribute, the device will set the Cylinder Low register to F4h and the
Cylinder High register to 2Ch. If no threshold exceeded condition exists, the
device will set the Cylinder Low register to 4Fh and the Cylinder High register to
C2h.
3.9.7 SMART Read Remap Data

COMMAND CODE | B0h with a Feature Register value of E0h
INPUTS |
Register
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
E0h
01h
4Fh
C2h
1
D
B0h

invalid, if the Sector Count is not 1, or if SMART is not enabled.
DESCRIPTION | This command returns one sector of spare block information.
The information is the initial number of blocks per flash chip available for bad
block remap, and the current number of blocks per flash chip available for bad
block remap. The layout of the returned sector is:
Offset
0..31
32..63
64..511
Description
Initial number of replacement blocks for chips 0..15, 2 bytes per entry
Current number of replacement blocks for chips 0..15, 2 bytes per entry
3.9.8 SMART Read Wear Level Data

COMMAND CODE | B0h with a Feature Register value of E1h
INPUTS |
Register
Features
Sector Count
Datasheet
PSFCF1XXXXDXX
Revision A4
E1h
04h
01/09/2012
Viking Technology
Page 41 of 43
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
4Fh
C2h
1
D
B0h

invalid, if the Sector Count is not 4, or if SMART is not enabled.
DESCRIPTION | This command will return four sectors of information regarding
the status of the wear leveling. The information returned is the distribution of the
blocks into the 1024 possible wear level classes. For each of the wear level
classes, the number of blocks that have this class is returned in the data sectors.
The layout of the returned sectors is, with n the sector number from 0 to 3:
Offset
0..1
2..3
508..509
510..511
Description
Number of flash blocks that have wear level class 256*n+0

i.e. the first sector returns the information for wear level classes 0 to 255, the
second sector returns the information for wear level classes 256 to 511, and so
on.
A block moves from one wear level class into the next when it reaches the
number of erases that is specified as the factory programmed Wear Level
Threshold. A common threshold number is 4095, this means that blocks in wear
level class 0 have seen 0 to 4095 erases, blocks in wear level class 1 have seen
4096 to 8191 erases, and so on. Using this information, statements about the
wear of the card, and of the estimated remaining life can be made. The useful
range of wear level classes is 0 to 1022, class 1023 has blocks that are not
subject to wear leveling, like the Anchor block.
Datasheet
PSFCF1XXXXDXX
Revision A4
01/09/2012
Viking Technology
Page 42 of 43
4 Certifications and Compliance

Table 4-1: Device Certifications
Certification/Compliance
CE Compliant
RoHS
China RoHS
FCC
Description
Indicates conformity with the essential health and safety requirements
set out in European Directives Low Voltage Directive and EMC
directive.
EN 55022:2006+A1:2007
EN 55024:1998+A1:2001+A2:2003
EN 61000-4-2:2009
EN 61000-4-3:2008
EN 61000-4-8:2001
Restriction of Hazardous Substance Directive
Restriction of Hazardous Substance Directive, China
ANSI C63.4-2002, Part 15, Subpart B Class B
5 References
CF+ and CompactFlash Specification Revision 4.1
6 Revision History
Date
2/11/10
8/10/10
9/1/10
11/23/10
Revision
A
A1
A2
A3
Description
Initial Release
Added 32GB capacity information
Updated formatting, updated introduction section and footer
Fixed miscellaneous omissions.
Updated Read/Write performance table for 40Mhz internal clock
1/11/12
Datasheet
PSFCF1XXXXDXX
Revision A4
A4
Add new logo and company name
01/09/2012
Viking Technology
Page 43 of 43

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Viking Technology

Ordering Information: Viking Compact Flash

x is temperature: C = Commercial Temp, I = Industrial Temp

Connector Pin Assignments

Pin Function Description

Absolute Maximum Ratings

DC Operating Conditions and Characteristics

Reliability & Retention

CF-ATA Command Support

Identify Drive Parameter

CERTIFICATIONS AND COMPLIANCE

Note: 1) Measured using IOMETER 2008.

1.3 CHS Parameters

1.4 Block Diagram

1.5 Mechanical Information

Note: All dimensions are in inches.

Note: All dimensions are in millimeters.

PCMCIA 2.1, PC Card ATA, CF 3.0, CF 4.1 standard compatible

2.2 Pin Function Description

In I/O and Memory modes, these are the

2-6, 2123, 2731, 47,

Grounded by host to enable True IDE

Interrupt Request to the Host (active high).

Asserted when the card is selected and

Selects the 16-bit port. A low signal

Clocks I/O data from the internal controller

Clocks I/O data from the card bus to the

This input signal is used to enable Memory

3.2 DC Operating Conditions and Characteristics

3.3 Environmental Specifications

3.4 Reliability & Retention

3.6.1 Power-on Timing

VCC rise time 10% to 90%

Figure 3-1: Power On RESET Timing

Optional (requires bill of

3.6.2 Attribute Memory Read Timing

3.6.3 Attribute Memory Write Timing

Write Cycle Time

3.6.4 Common Memory Read Timing

Wait Width Time2

-WAIT is not supported in this mode

3.6.5 Common Memory Write Timing

Wait Width Time2

-WAIT is not supported in this mode

3.6.6 I/O Mode Read Timing

-IOIS16 and -INPACK are not supported in this mode.

3.6.7 I/O Mode Write Timing

3.6.8 True IDE Mode PIO Read/Write Timing

Cycle Time (min)

Notes: All timings are in ns.

3.6.9 True IDE Multiword DMA Read/Write Timing

Cycle time (ns)

Ultra DMA AC Characteristics

Table 3-15: Ultra DMA AC Characteristics

Ultra DMA Data Burst Timing Descriptions

Table 3-16: Ultra DMA Data Burst Timing Descriptions

t2CYCTYP Typical sustained average two cycle time

Ready-to-final-STROBE time (no STROBE edges shall be sent