VL7301
VL7301
02
LESSON PLAN
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Unit : I
Semester: III
LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 01 of 06
9
Syllabus:
Introduction to testing Faults in Digital Circuits Modeling of faults Logical Fault
Models Fault detection Fault Location Fault dominance Logic simulation Types of
simulation Delay models Gate Level Event driven simulation.
Objective: To know the various types of faults and also to study about fault detection and
dominance.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
1.
50m
BB
2.
50m
1,4
BB
3.
50m
1,4
BB
4.
50m
BB
5.
50m
BB
6.
50m
BB
7.
50m
BB
8.
Delay models
50m
BB
9.
50m
BB
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Unit : II
Semester: III
LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 02 of 06
Syllabus:
Test generation for combinational logic circuits Testable combinational logic circuit
design Test generation for sequential circuits design of testable sequential circuits.
Objective: To know the concepts of test generation for combinational and sequential circuits.
Session
No.
10.
11.
12.
13.
14.
Topics to be covered
Test Generation for combinational logic circuits One-dimensional Path sensitization and Boolean
Difference
Test Generation for combinational logic circuits D-Algorithm
Test Generation for combinational logic circuits PODEM
Testable combinational logic circuit design Reed-Muller Expansion Technique
Testable combinational logic circuit design Three level OR-AND-OR design and Syndrometestable design
CAT I
15.
16.
Time
Ref
Teaching
Method
50m
2,4
BB
50m
2,5
BB/PPT
50m
BB/PPT
50m
BB/PPT
50m
BB/PPT
50m
2,5
BB/PPT
50m
2,5
BB
90m
17.
50m
BB
18.
50m
BB
DOC/LP/01/28.02.02
LESSON PLAN
LP VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Date: 23/06/14
Unit : III
Branch : M.E (AE)
Semester: III Page 03 of 06
UNIT III DESIGN FOR TESTABILITY
Syllabus:
Design for Testability Ad-hoc design generic scan based design classical scan based
design system level DFT approaches.
Objective: To understand the concepts of test generation method - DFT.
Session
No.
19.
20.
21.
22.
23.
24.
25.
26.
27.
Topics to be covered
Testability - Controllability and Observability
Adhoc design for testability techniques - Test points,
Initialization, Monostable Multivibrators
Adhoc design for testability techniques - Oscillator
and clocks, Partitioning counters and shift registers
Adhoc design for testability techniques - Partitioning
of Large combinational circuits, Logical redundancy,
Global feedback paths
Generic scan based design - Full serial integrated
scan
Generic scan based design - Isolated serial scan and
Nonserial scan
Classical scan based design
Classical scan based design - Level-Sensitive Scan
Design (LSSD)
System-level DFT approaches - system level busses,
system-level scan paths
Time
Ref
Teaching
Method
50m
1,3
BB
50m
1,4
BB
50m
1,4
BB
50m
1,4
BB
50m
PPT
50m
PPT
50m
PPT/ICT
50m
PPT
50m
PPT
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Unit : IV
Semester: III
LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 04 of 06
Syllabus:
Built-In self Test test pattern generation for BIST Circular BIST BIST Architectures
Testable Memory Design Test Algorithms Test generation for Embedded RAMs.
Objective: To study the concepts of test generation method - BIST.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
28.
50m
1,6
BB/ICT
29.
50m
BB
CAT II
90m
30.
50m
1,4
BB
31.
Circular BIST
50m
1,5
BB
50m
1,5
BB
50m
BB
32.
33.
34.
50m
BB
35.
Test Algorithms
50m
BB
36.
50m
BB
DOC/LP/01/28.02.02
LESSON PLAN
LP VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Date: 23/06/14
Unit : V
Branch : M.E (AE)
Semester: III Page 05 of 06
UNIT V FAULT DIAGNOSIS
Syllabus:
Logical Level Diagnosis Diagnosis by UUT reduction Fault Diagnosis for
Combinational Circuits Self-checking design System Level Diagnosis.
Objective: To understand the fault diagnosis method.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
37.
50m
BB
38.
50m
BB
39.
50m
1,5
BB
50m
BB
50m
BB
50m
BB
40.
41.
42.
43.
50m
BB
44.
50m
BB
45.
50m
BB
CAT III
90m
DOC/LP/01/28.02.02
LESSON PLAN
LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 06 of 06
Semester: III
1
I II
Unit
2
I II
3
I
4
II
II
5
I II
6
I II
II
III
7
I II
8
I II
9
I II
10
I II
IV
11
I II
12
II
REFERENCES:
CAT III
CAT I
CAT IIsystems and Testable Design,
1. M.Abramovici, M.A.Breuer
and A.D. Friedman, Digital
Prepared by
Approved by
Name
Ms.R.Kousalya
Dr.S.Ganesh Vaidyanathan
Designation
Assistant Professor
HoD - EC
Date
23/06/2014
23/06/2014
Signature