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VL7301

The document outlines a lesson plan for a course on testing of VLSI circuits. It includes 5 units that will be covered over 12 weeks, with topics, objectives, and time allotted for each session. Testing methods like fault modeling, test generation, design for testability, built-in self-test, and fault diagnosis are discussed. References for the course are also provided.

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Saranya Ramaswamy
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78 views6 pages

VL7301

The document outlines a lesson plan for a course on testing of VLSI circuits. It includes 5 units that will be covered over 12 weeks, with topics, objectives, and time allotted for each session. Testing methods like fault modeling, test generation, design for testability, built-in self-test, and fault diagnosis are discussed. References for the course are also provided.

Uploaded by

Saranya Ramaswamy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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DOC/LP/01/28.02.

02
LESSON PLAN
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Unit : I

Branch : M.E (AE)

Semester: III

UNIT I TESTING AND FAULT MODELLING

LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 01 of 06
9

Syllabus:
Introduction to testing Faults in Digital Circuits Modeling of faults Logical Fault
Models Fault detection Fault Location Fault dominance Logic simulation Types of
simulation Delay models Gate Level Event driven simulation.
Objective: To know the various types of faults and also to study about fault detection and
dominance.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

1.

Introduction to testing - Need for testing

50m

BB

2.

Faults in Digital Circuits

50m

1,4

BB

3.

Faults Modeling - Logical fault models

50m

1,4

BB

4.

Fault Detection - Combinational and Sequential circuits

50m

BB

5.

Fault Location - Combinational and Sequential circuits

50m

BB

6.

Fault Dominance - Combinational and Sequential circuits

50m

BB

7.

Logic simulation - Types of simulation

50m

BB

8.

Delay models

50m

BB

9.

Gate level Event-driven simulation

50m

BB

DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Unit : II

Branch : M.E (AE)

Semester: III

LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 02 of 06

UNIT II TEST GENERATION

Syllabus:
Test generation for combinational logic circuits Testable combinational logic circuit
design Test generation for sequential circuits design of testable sequential circuits.
Objective: To know the concepts of test generation for combinational and sequential circuits.
Session
No.
10.
11.
12.
13.
14.

Topics to be covered
Test Generation for combinational logic circuits One-dimensional Path sensitization and Boolean
Difference
Test Generation for combinational logic circuits D-Algorithm
Test Generation for combinational logic circuits PODEM
Testable combinational logic circuit design Reed-Muller Expansion Technique
Testable combinational logic circuit design Three level OR-AND-OR design and Syndrometestable design
CAT I

15.
16.

Test generation for sequential circuits - Iterative


Combinational circuits
Test generation for sequential circuits - State
Table verification

Time

Ref

Teaching
Method

50m

2,4

BB

50m

2,5

BB/PPT

50m

BB/PPT

50m

BB/PPT

50m

BB/PPT

50m

2,5

BB/PPT

50m

2,5

BB

90m

17.

Design of testable sequential circuits

50m

BB

18.

Design of testable sequential circuits - Scan-path


technique

50m

BB

DOC/LP/01/28.02.02
LESSON PLAN

LP VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Date: 23/06/14
Unit : III
Branch : M.E (AE)
Semester: III Page 03 of 06
UNIT III DESIGN FOR TESTABILITY

Syllabus:
Design for Testability Ad-hoc design generic scan based design classical scan based
design system level DFT approaches.
Objective: To understand the concepts of test generation method - DFT.
Session
No.
19.
20.
21.
22.
23.
24.
25.
26.
27.

Topics to be covered
Testability - Controllability and Observability
Adhoc design for testability techniques - Test points,
Initialization, Monostable Multivibrators
Adhoc design for testability techniques - Oscillator
and clocks, Partitioning counters and shift registers
Adhoc design for testability techniques - Partitioning
of Large combinational circuits, Logical redundancy,
Global feedback paths
Generic scan based design - Full serial integrated
scan
Generic scan based design - Isolated serial scan and
Nonserial scan
Classical scan based design
Classical scan based design - Level-Sensitive Scan
Design (LSSD)
System-level DFT approaches - system level busses,
system-level scan paths

Time

Ref

Teaching
Method

50m

1,3

BB

50m

1,4

BB

50m

1,4

BB

50m

1,4

BB

50m

PPT

50m

PPT

50m

PPT/ICT

50m

PPT

50m

PPT

DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Unit : IV

Branch : M.E (AE)

Semester: III

LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 04 of 06

UNIT IV SELF TEST AND TEST ALGORITHMS

Syllabus:
Built-In self Test test pattern generation for BIST Circular BIST BIST Architectures
Testable Memory Design Test Algorithms Test generation for Embedded RAMs.
Objective: To study the concepts of test generation method - BIST.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

28.

Introduction to BIST concepts

50m

1,6

BB/ICT

29.

Test pattern generation for BIST - Exhaustive


testing, Pseudorandom testing, Pseudoexhaustive
testing

50m

BB

CAT II

90m

30.

Test pattern generation for BIST - Logical


segmentation, Constant-weight patterns,
Identification of test signal inputs, Physical
segmentation

50m

1,4

BB

31.

Circular BIST

50m

1,5

BB

50m

1,5

BB

50m

BB

32.
33.

BIST Architecture - CSBL, BEST, RTS, LOCST,


STUMPS
BIST Architecture - CBIST, CEBS, RTD, SST,
CATS, BILBO

34.

Testable Memory Design

50m

BB

35.

Test Algorithms

50m

BB

36.

Test generation for Embedded RAMs

50m

BB

DOC/LP/01/28.02.02
LESSON PLAN

LP VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS
Date: 23/06/14
Unit : V
Branch : M.E (AE)
Semester: III Page 05 of 06
UNIT V FAULT DIAGNOSIS

Syllabus:
Logical Level Diagnosis Diagnosis by UUT reduction Fault Diagnosis for
Combinational Circuits Self-checking design System Level Diagnosis.
Objective: To understand the fault diagnosis method.

Session
No.

Topics to be covered

Time

Ref

Teaching
Method

37.

Logical level diagnosis - basic concepts

50m

BB

38.

Diagnosis by UUT reduction

50m

BB

39.

Fault Diagnosis for Combinational Circuits

50m

1,5

BB

50m

BB

50m

BB

50m

BB

40.
41.
42.

Self Checking design - multiple bit errors, Checking


circuits and self-checking
Self Checking design - self-checking checkers,
Parity-check function
Self Checking design - Totally self-checking m/n
code and equality checkers, Berger code checker

43.

Self Checking Combinational circuits

50m

BB

44.

Self Checking sequential circuits

50m

BB

45.

System level Diagnosis

50m

BB

CAT III

90m

DOC/LP/01/28.02.02
LESSON PLAN

LP VL7301
LP Rev. No: 00
Date: 23/06/14
Page 06 of 06

Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS


Branch : M.E. (Applied Electronics)

Semester: III

Course Delivery Plan:


Week

1
I II

Unit

2
I II

3
I

4
II

II

5
I II

6
I II

II

III

7
I II

8
I II

9
I II

10
I II

IV

11
I II

12
II

REFERENCES:
CAT III

CAT I
CAT IIsystems and Testable Design,
1. M.Abramovici, M.A.Breuer
and A.D. Friedman, Digital

Jaico Publishing House, 2002.


2. P.K. Lala, Fault Tolerant and Fault Testable Hardware Design, Academic Press, 2012.
3. P.K. Lala, Digital Circuit Testing and Testability, Academic Press, 2002.
4. M.L.Bushnell and V.D.Agrawal, Essentials of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2002.
5. A.L.Crouch, Design Test for Digital ICs and Embedded Core Systems, Prentice Hall
International, 2002.
6. http://nptel.ac.in/courses/106103016/30

Prepared by

Approved by

Name

Ms.R.Kousalya

Dr.S.Ganesh Vaidyanathan

Designation

Assistant Professor

HoD - EC

Date

23/06/2014

23/06/2014

Signature

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