VLSIDesigncourse Templete
VLSIDesigncourse Templete
VLSIDesigncourse Templete
Semester: 6
Hours: 4+1
Demonstrate the knowledge of different VLSI fabrication processes and CMOS Logic
Design.
Course Contents:
Topics
Lecture Hours
UNIT I Introduction:
Introduction to VLSI Design
Introduction to IC Technology
MOS,
PMOS, NMOS
CMOS production process
BiCMOS production process
1
1
1
1
2
2
gm , gds ,
nMOS inverter
Bi-CMOS inverters
Latch-up
10
Contacts and transistors layout diagrams for NMOS & CMOS inverters
Transistor switches
Realization of gates
Scaling factors
Limitations of scaling
Limitations of scaling
PLA
PAL
FPGAs
CPLDs
Standard cells
1
1
2
2
Learning resources:
Text books;
1. Essentials of VLSI Circuits and Systems- Kamran Eshraghian, Douglas and A Pucknell, PHI.
PrivateLimited, 2005.
2 Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 1999.
References:
1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P. Uyemura,
ThomsonLearning,2005.
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
4. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
5. VLSI Technology S.M. SZE, 2nd Edition, TMH, 2003.
6. Fundamentals of Logic Design with VHDL Stephen. Brown and ZvonkoVranesic, TMH, 2005
Additional Resources:
1. http://nptel.ac.in/
Gain knowledge of different VLSI fabrication processes and CMOS Logic Design.
Table: Mapping of course outcomes with program outcomes (CO/ Competency PO Matrix):
COS
/POS
CLO 1
CLO 2
CLO 3
CLO 4
CLO 5
CLO 6
COs
CLO/ Competency
CLO 1
Instructional Methods
CLO 3
parameters and
M1, M3, M7,M9
circuit performance.
CLO 4
CLO 5
CLO 6
Weightage(Marks)
15
25
10
15
25
10
Best of two
75