NMI

Short for Non-Maskable Interrupt, NMI is the highest-priority interrupt capable of interrupting
all software and non-vital hardware devices. The NMI is not commonly used and usually only
used to verify if a serious error has occurred or stop all operations because of a failure. For
example, when you press Ctrl+Alt+Del when the computer freezes or stops responding a NMI is
sent to the CPU.
Tip: Unlike a INTR or interrupt, the NMI cannot be interrupted by any other interrupt.
Difference between maskable and non-maskable interrupt?
the interrupt which can be ignored by the processor ,while performing its operations
are called maskable interrupts. generally maskable interrupts are the interrupts that
comes from the pheripheral devices.
where as the non maskable interrupts are the interrupts which cannot be ignored.
generally these type of interrupts are specified to be software interrupts.
the examples of maskable are: mouseclick,memoryread etc
the examples of non_maskable are:powerfailure,software corruptedetc

What is a non-maskable interrupt?

What is a non-maskable interrupt (NMI) and what is its role?
The basic idea is that a processor can mask or block interrupt requests to have the processor
perform a task. A processor will typically not do this unless it gets really bogged down or busy. A
non-maskable interrupt is used for very high priority tasks that you don't want the processor to be
able to mask when it gets bogged down.

Interrupts in 8085 Microprocessor

First of all i want

Interrupt???????

to

discuss

that

what

is

Interrupt is a mechanism by which an I/O or an instruction

can suspend the normal execution of processor and get
itself serviced. Generally, a particular task is assigned to
that interrupt signal. In the microprocessor based system
the interrupts are used for data transfer between the
peripheral devices and the microprocessor. The processor
will check the interrupts always at the 2nd T-state of last
machine cycle.
Interrupt Service Routine(ISR):-A small program or a
routine
that
when
executed
services
the corresponding interrupting source is called as
an ISR.
Maskable/Non-Maskable Interrupt:-An interrupt that can
be disabled by writing some instruction is known as
Maskable Interrupt otherwise it is called Non-Maskable
Interrupt.
There are two types
8085 Microprocessor:

of

interrupts

used

in

1.Hardware Interrupts
2.Software Interrupts
There are 6 pins available in 8085 for interrupt:
TRAP
RST 7.5
RST6.5
RST5.5
INTR
INTA
Execution of Interrupts:When there is an interrupt requests to the Microprocessor
then after accepting the interrupts Microprocessor send
the INTA (active low) signal to the peripheral. The vectored
address of particular interrupt is stored in program counter.
The processor executes an interrupt service routine (ISR)
addressed in program counter.

Software Interrupts in 8085.....(Interrupt Contd..)

Software Interrupts:A software interrupts is a particular instructions that can be

inserted into the desired location in the rpogram. There are
eight Software interrupts in 8085 Microprocessor. From
RST0 to RST7.

RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7

They allow the microprocessor to transfer program control

from the main program to the subroutine program. After

completing the subroutine program, the program control

returns back to the main program.

We can calculate the vector address of these interrupts

using the formula given below:

Vector Address = Interrupt Number *

8
So we can find simply vector address. For Example:

RST2:

vector address=2*8

= 16

RST1:

vector address=1*8

= 08

RST3:

vector address=3*8

= 24

Vector address table for the software interrupts:

Hardware Interrupts in 8085......(Interrupts Contd)........

Hardware Interrupt:As i have already discussed that there are 6 interrupt

pins in
the
microprocessor
used as
Hardware
Interrrupts given below:
TRAP
RST7.5
RST6.5
RST5.5
INTR
INTA is not an
Microprocessor

interrupt.

INTA is
for

used

by the
sending

the acknowledgement. TRAP has highest priority

and RST7.5 has second highest priority and so on.
The Vector address of these interrupts are given below:

1.TRAP:-It is non maskable edge and level triggered

interrupt. TRAP has the highest priority and vectores
interrupt. Edge and level triggered means that the TRAP
must go high and remain high until it is acknowledged. In
case of sudden power failure, it executes a ISR and send
the data from main memory to backup memory.
As we know that TRAP can not be masked but it can be
delayed using HOLD signal.
This interrupt transfers the microprocessor's control to
location 0024H.
How a TRAP interrupt may be masked???
TRAP interrupts can only be masked by reseting the
microprocessor. There is no other way to mask it.

2.RST7.5:-It has the second highest priority. It is maskable

and edge level triggered interrupt. The vector address of
this interrupt is 003CH. Edge sensitive means input goes
high and no need to maintain high state until it is
recognized.
How It may be masked??
It can also be reset or masked by reseting microprocessor.
It can also be resetted by DI instruction.
3.RST6.5 and RST5.5:-These are level triggered and
maskable interrupts. When RST6.5 pin is at logic 1, INTE
flip-flop is set. RST 6.5 has third highest priority and RST
5.5 has fourth highest priority.
It can be masked by giving DI and SIM instructions or by
reseting microprocessor.

4.INTR:-It is level triggered and maskable interrupt. It has

the lowest priority. It can be disabled by reseting the
microprocessor or by DI and SIM instruction.

The following sequence of events occurs when INTR

signal goes high:
1. The 8085 checks the status of INTR signal during
execution of each instruction.
2. If INTR signal is high, then 8085 complete its current
instruction and sends active low interrupt acknowledge
signal, if the interrupt is enabled.
3.On receiving the instruction, the 8085 save the address
of next instruction on stack and execute received
instruction.

Architecture of 8085
This

is

the

functional

block

diagram

This
is
al Block Diagram of 8085 Microprocessor.

of

the

the

8085

Microprocessor.

function

Acumulator:-It is a 8-bit register which is used to perform airthmetical and logical operation. It
stores the output of any operation. It also works as registers for i/o accesses.

Temporary Register:-It is a 8-bit register which is used to hold the data on which the
acumulator is computing operation. It is also called as operand register because it provides
operands to ALU.

Registers:-These are general purposes registers. Microprocessor consists 6 general purpose

registers of 8-bit each named as B,C,D,E,H and L. Generally theses registers are not used for
storing the data permanently. It carries the 8-bits data. These are used only during the execution
of the instructions.
These registers can also be used to carry the 16 bits data by making the pair of 2 registers. The
valid register pairs available are BC,DE HL. We can not use other pairs except BC,DEand HL.
These registers are programmed by user.

ALU:-ALU performs the airthmetic operations and logical operation.

Flag Registers:-It consists of 5 flip flop which changes its status according to the result stored
in an accumulator. It is also known as status registers. It is connected to the ALU.
There are five flip-flops in the flag register are as follows:
1.Sign(S)
2.zero(z)
3.Auxiliary carry(AC)
4.Parity(P)
5.Carry(C)
The bit position of the flip flop in flag register is:

All of the three flip flop set and reset according to the stored result in the accumulator.
1.Sign- If D7 of the result is 1 then sign flag is set otherwise reset. As we know that a number
on the D7 always desides the sign of the number.
if D7 is 1: the number is negative.
if D7 is 0: the number is positive.

2.Zeros(Z)-If the result stored in an accumulator is zero then this flip flop is set otherwise it is
reset.

3.Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output then it is set otherwise it is
reset.

4.Parity(P)-If the no of 1's is even in the output stored in the accumulator then it is set otherwise
it is reset for the odd.

5.Carry(C)-If the result stored in an accumulator generates a carry in its final output then it is set
otherwise it is reset.

Instruction registers(IR):-It is a 8-bit register. When an instruction is fetched from memory then
it is stored in this register.

Instruction Decoder:- Instruction decoder identifies the instructions. It takes the informations
from instruction register and decodes the instruction to be performed.

Program Counter:-It is a 16 bit register used as memory pointer. It stores the memory address
of the next instruction to be executed. So we can say that this register is used to sequencing the
program. Generally the memory have 16 bit addresses so that it has 16 bit memory.

The program counter is set to 0000H.

Stack Pointer:-It is also a 16 bit register used as memory pointer. It points to the memory
location called stack. Generally stack is a reserved portion of memory where information can be
stores or taken back together.

Timing and Control Unit:-It provides timing and control signal to the microprocessor to perform
the various operation.It has three control signal. It controls all external and internal circuits. It
operates with reference to clock signal.It synchronizes all the data transfers.
There are three control signal:
1.ALE-Airthmetic Latch Enable, It provides control signal to synchronize the components of
microprocessor.
2.RD- This is active low used for reading operation.
3.WR-This is active low used for writing operation.

There are three status signal used in microprocessor S0, S1 and IO/M. It changes its status
according the provided input to these pins.

Serial Input Output Control-There are two pins in this unit. This unit is used for serial data
communication.

Interrupt Unit-There are 6 interrupt pins in this unit. Generally an external hardware is
connected to these pins. These pins provide interrupt signal sent by external hardware to
microprocessor and microprocessor sends acknowledgement for receiving the interrupt signal.
Generally
INTA
is
used
for
acknowledgement.

Register

Section:-Many

registers

has

been

used

It consists of PIPO (Parallel Input Parallel Output) register.

8085 Bus Structure

There are three buses in Microprocessor:
1.Address Bus
2.Data Bus
3.Control Bus

in

microprocessor.

1.Address Bus:-Genearlly, Microprocessor has 16 bit address bus. The bus over
which the CPU sends out the address of the memory location is known as Address
bus. The address bus carries the address of memory location to be written or to be
read from.
The address bus is unidirectional. It means bits flowing occurs only in one direction,
only from microprocessor to peripheral devices.
We can find that how much memory location it can using the formula 2^N. where N
is the number of bits used for address lines.

here,

2^16 = 65536bytes or 64Kb

So we can say that it can access upto 64 kb memory location.

Q.>If a processor has 4 GB memory then how many address lines are required to
access this memory?
Ans: 4GB= 4 * 1GB
4 = 2^2
1GB = 2^30
4GB = 2^2 * 2^30 = 2^32
So 32 address lines are required to access the 4 GB memory.

2.Data Bus:-8085 Microprocessor has 8 bit data bus. So it can be used to carry the
8 bit data starting from 00000000H(00H) to 11111111H(FFH). Here 'H' tells the

Hexadecimal Number. It is bidirectional. These lines are used for data flowing in
both direction means data can be transferred or can be received through these
lines. The data bus also connects the I/O ports and CPU. The largest number that
can appear on the data bus is 11111111.
It has 8 parallel lines of data bus. So it can access upto 2^8 = 256 data bus lines.

3.Control Bus:-The control bus is used for sending control signals to the memory
and I/O devices. The CPU sends control signal on the control bus to enable the
outputs of addressed memory devices or I/O port devices.
Some of the control bus signals are as follows:
1.Memory read
2.Memory write
3.I/O read
4.I/O write.

Microcomputers and Microprocessor

Microcomputer:-Microcomputers are much smaller

computer. They operate still more slowly and they work
with still smaller data words (typically 4 bits, 8 bits, 16 bits
or 32 bits).
They can address few thousands to
few million memory location. One of the important feature
of microcompter is that the CPU is usually a single IC
called as a microprocessor.
Difference b/w Microprocessor and microcomputer:

1. A microprocessor has a CPU to which we have to add

ROM, RAM and ports to make a microcomputer.
2.Application of microcomputer are from sewing machine,
washing machine and other domestic appliances to
computer added design system.
3.Intel 8051 is a microcomputer which is actually a single
chip computer.

Pin Diagram of 8085 Microprocessor with Description

8085 is a general purpose microprocessor having 40 pins and works on single power
supply. To study the pin diagram we group
the signals into 5 categories:
1.Power Supply
2.Clock Signals
3.Interrupt Signals
4.Address and Data bus
5.Control and Status signals
6.Serial I/O Port
7.DMA Request Signals

Power Supply Signal and clock signal:

VCC:-Vcc is to be connected to +5V power supply.
Vss:-Ground reference
X1 and X2:- This pin is used for providing the clock frequency to the
microprocessor. Generally Crystal oscillator or LC oscillator is used to generate the
frequency. The frequency generated here is internally divided into two.As we know
that the basic operating timing frequency of the microprocessor is 3 MHz so
6 MHz frquency is applied.

Serial Input Output port:SID and SOD:-These pins are used for serial data communication.

Interrupt Signal:-

Pin 6 to 11:- These pins are used for interrupt signals. Generally and external
devices are connected here which requests the microprocessor to perform a
particular task.
There are 5 pins for hardware interruptsTRAP, RST7.5, RST 6.5, RST5.5 and INTR
INTA is used for acknowledgement. Microprocessor sends the acknowledgement to
external devices through the INTA pin.

Address Bus and DATA Buses:AD0-AD7:-These are multiplexed address and data bus. So it can be used to carry
the lower order 8 bit address as well as the data. Generally these lines are
demultiplexed using the Latch.
During the opcode fetch operation, in the first clock cycle the lines deliever the
lower order address bus A0-A7.
In the subsequent IO/M read or write it is used as data bus D0-D7. CPU can read or
write data through these lines.
A8-A15:- These are address bus used to address the memory location.

Continue to Pin Diagram and its description

Control And Status Signal:S0 and S1:-It is used for the status signal in microprocessor.
ALE(Airthmetic Latch Enable):-This signal is used to capture the lower address
presented on multiplexed address and data bus.
RD:-This is active low input generally
used for reading operation.
WR:-This is active low input used for writing operation.
IO/M:-This pin is used to select the memory or input-output through which we want
to communicate the data.
READY:-As we know that memory and input -output have slower response than
microprocessor. So a microprocessor may now be able to handle further data till it
completes the present job. So it is in waiting state. As it completes the present job it
sets the READY pin. Microprocessor enters into wait state while READY pin is
disabled.
RESET IN:-This is active low input. This pin is used to reset the microprocessor. An
active low signal applied to this pin reset the program counter inside the
microprocessor. The busses are tristated.

RESETOUT:-If we want to reset the external devices connected to the

microprocessor then a signal applied to this pin resets the external devices.

DMA Request Signal:

HOLD and HLDA:-HOLD is an active high input signal used by the other controller
to request microprocessor about use of address, data and control signal. The HOLD
and HLDA signal are used for direct memory access(DMA). DMA controller receives a
requests from a device and in turn issues the HOLD signal to the microprocessor.
The processor releases the system bus and then acknowledges the HOLD signal
with HLDA signal. The DMA transfer thus begins.

How to Demultiplex Address and Data Bus

Generally, 74LS373 Latch IC is used for latching the address issued by
Microprocessor.
It has 8-latches(D-flip flop).

Address will
appear on AD0-AD7 lines.
ALE will go high and forcing enable G pin of Latch. This will make the latch
transparent. It means whatever will be input, will be output. Presently input address
is A0-A7.Therefore output is A0-A7.
When ALE=0, then AD0-AD7 will now be used as data bus.

Representation of signals in Timing Diagram

1.Clock Signals:-As we know that the microprocessor operates with reference to clock signals
provided to it. At pins X1 and X2 we provide clock signals and this frequency is divided by two.
This frewuency is called as the operating frequency.

2.Single Line Signal:-The status of single line will be either LOW or HIGH. But the change from
one state to another state is not possible in zero time.

3.Multiple Line Signals:-In Microprocessor we have multiple lines. These signals are also
called as bus signals. If a single line changes occure then we have to show a crossing to
indicate change in contents.

Memory Interfacing in 8085 Microprocessor.

Memory Interfacing:-As we know that any system which

process digital data needs the facility for storing the
data. Interfacing is a technique to be used for connecting
the Microprocessor to Memory.
Now a days Semiconductor memories are used for storing
purpose. There are some of the advantages of the
semiconductor memory.

Small size
High speed
Better reliability
Low cost
Generally, RAM or ROM is used for memory interfacing.
Memory:-A memory is a digital IC which stores the data in
binary form.
Memory Size:-The number of location and number of bits
per word will vary from memory to memory. For example,
If a particular memory chip is capable of storing M words
with each word having N-bits. Then the size of the memory
will be M N.
Interfacing a ROM memory of 4096*8 with 8085
Microprocessor:Given memory size = 4096 * 8
4096 =2^12.
So 12 lines will be used for interfacing. A0 to A11

In this system A0 to A11 lines of Microprocessor will be

connected to the address lines of the memory. and D0 to
D7 of the 8085 microprocessor will be connected to the
data bus of the memory.
As we know that the it is EPROM, so only RD pin is
connected to the microprocessor. There is not the facility
for writing data.
In case if you are using RAM then you have to connect
one more pin for writing operation.

As you can see that there is a pin named CS. Generally

this pin is used for Selction for the chip in case of two or
more than memory chip.
Latch has been used to separate the data and address
bus.
Memory Interfacing Using RAM and ROM both with 8085
Microprocessor

Interfacing RAM and ROM both at a time with 8085:

Here ROM with 32 kb and RAM with 64kb has been used.
32kb = 32768bytes is equal to
2^15
and
64kb = 65536bytes is equal to 2^16
So it is clear that 15 address lines are required for
interfacing of ROM and 16 address lines are required for
interfacing of RAM. As we know that there are only 16
address lines in 8085 Microprocessor. But we need 16+15

= 31 lines.
Think!!!!!!!!
How it may be possible???
Solution of interfacing using RAM and ROM both at a time.

As we know that a data is stored only in one memory

location and we also know that
a data is received or transmittted through only one
memory at a time. It means only one memory will be
processing at a time. So RAM and ROM are connected to
the same address lines. As you can see in the figure that a
NOT gate has been used here. It will select only one
memory at a time.
A0 to A14 pins is connected to ROM and A0 to A15 pins is

connected to RAM. Pin A15 has been used for selecting

the memory either it will use RAM or ROM.
How To Interface The 8085 Microprocessor?
A microprocessor has to be interfaced with various peripherals to perform various functions.
Let's discuss about the Interfacing techniques in detail.

Introduction

We know that a microprocessor is the CPU of a computer. A microprocessor can perform some
operation on a data and give the output. But to perform the operation we need an input to enter
the data and an output to display the results of the operation. So we are using a keyboard and
monitor as Input and output along with the processor. Microprocessors engineering involves a lot
of other concepts and we also interface memory elements like ROM, EPROM to access the
memory.

Interfacing Types

There are two types of interfacing in context of the 8085 processor.

Memory Interfacing.
I/O Interfacing.
Memory Interfacing:
While executing an instruction, there is a necessity for the microprocessor to access memory
frequently for reading various instruction codes and data stored in the memory. The interfacing
circuit aids in accessing the memory.
Memory requires some signals to read from and write to registers. Similarly the
microprocessor transmits some signals for reading or writing a data.
But what is the purpose of interfacing circuit here?
The interfacing process involves matching the memory requirements with the microprocessor
signals. The interfacing circuit therefore should be designed in such a way that it matches the
memory signal requirements with the signals of the microprocessor. For example for carrying out
a READ process, the microprocessor should initiate a read signal which the memory requires to
read a data. In simple words, the primary function of a memory interfacing circuit is to aid the
microprocessor in reading and writing a data to the given register of a memory chip.

I/O Interfacing:
We know that keyboard and Displays are used as communication channel with outside world. So
it is necessary that we interface keyboard and displays with the microprocessor. This is called I/O
interfacing. In this type of interfacing we use latches and buffers for interfacing the keyboards
and displays with the microprocessor.
But the main disadvantage with this interfacing is that the microprocessor can perform only one
function. It functions as an input device if it is connected to buffer and as an output device if it is
connected to latch. Thus the capability is very limited in this type of interfacing.

Programmable Peripheral Devices

Programmable peripheral devices were introduced by Intel to increase the overall performance of
the system. These devices along with I/O functions, they perform various other functions such as
time delays, counters and interrupt handling. These devices are nothing but a combination of
many devices on a single chip. A programmable device can be set up to perform specific function
by writing a code in the internal register. As this code controls the function of the device its
called control word and internal register in which it is stored is called Control Register.
INTEL developed some peripheral devices for processors like 8085/8086/8088. The peripheral
devices includes
8255 Parallel Communication Interface (PPI)

8251 Serial communication Interface (USART- Universal Synchronous/Asynchronous

Receiver/Transmitter)
8257 DMA Controller
8279 Keyboard/Display Controller
8259 Programmable Interrupt controller
8254 Programmable Timer
Types of Communication Interface

There are two ways in which a microprocessor can connect with outside world or other memory
systems.
Serial Communication Interface
Parallel Communication interface
Serial Communication Interface:
In serial communication interface, the interface gets a single byte of data from the
microprocessor and sends it bit by bit to other system serially (or) the interface receives data bit
by bit serially from the external systems and converts the data into a single byte and transfers it
to the microprocessor.
Parallel Communication Interface:
This interface gets a byte of data from microprocessor and sends it bit by bit to the other systems
in simultaneous (or) parallel fashion. The interface also receives data bit by bit simultaneously
from the external system and converts the data into a single byte and transfers it to
microprocessor.
Consider that we have a microprocessor interfaced to both I/O device and also a memory chip.
Now how to select between the two devices according to the requirement?
For this purpose an address decoding circuit is used. An address decoding circuit aids in selecting
the required I/O device or a memory chip.

Comparison of 8085 and 8086

There are some of the difference mentioned below:

1.Size:8085 is 8 bit microprocessor whereas 8086 is 16 bit
microprocessor.
2.Address Bus:8085 has 16 bit address bus and 8086 has 20 bit addres
bus.
3.Memory:8085 can access upto 2^16 = 64 Kb of memory whereas
8086 can access upto
2^20 = 1 MB of memory.
4.Instruction Queue:8085 doesn't have an instruction queue whereas 8086 has
instruction queue.
5.Pipelining:8085 does not support pipelined architechture whereas
8086 supports pipelined architechture.
6.Multiprocessing Support:8085 does not support multiprocessing support whereas
8086 supports.

7.I/O:8085 can address 2^8 = 256 I/O's and 8086 can access
2^16 = 65,536 I/O's
8.Airthmetic Support:8085 only supports integer and decimal whereas 8086
supports integer, decimal and ASCII arithmetic.
9.Multiplication and Division:8085 doesn't support whereas 8086 supports.
10. Operating Modes:8085 supports only single operating mode whereas 8086
operates in two modes.
11.External Hardware:8085 requires less external hardware whereas 8086
requires more external hardware.
12.Cost:The cost of 8085 is low and 8086 is high.
13.Memory Segmentation:In 8085, memory space is not segmented but in 8086,
memory space is segmented.

Interrupts in 8085

Interrupt is signals send by an external device to the processor, to request the

processor to perform a particular task or work.

Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.

The processor will check the interrupts always at the 2nd T-state of last machine
cycle.

If there is any interrupt it accept the interrupt and send the INTA (active low) signal
to the peripheral.

The vectored address of particular interrupt is stored in program counter.

The processor executes an interrupt service routine (ISR) addressed in program

counter.

It returned to main program by RET instruction.

Types of Interrupts:

It supports two types of interrupts.

Hardware

Software

Software interrupts:

The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.

The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.

Interrupt number * 8 = vector address

for RST 5,5 * 8 = 40 = 28H

Vector address for interrupt RST 5 is 0028H

The Table shows the vector addresses of all interrupts.

Hardware Interrupts

Hardware interrupts:

An external device initiates the hardware interrupts and placing an appropriate

signal at the interrupt pin of the processor.

If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP

(2) RST 7.5

(3) RST 6.5

(4) RST 5.5

(5) INTR

TRAP:

This interrupt is a non-maskable interrupt. It is unaffected by any mask or

interrupt enable.

TRAP bas the highest priority and vectored interrupt.

TRAP interrupt is edge and level triggered. This means hat the TRAP must go high
and remain high until it is acknowledged.

In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.

The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first and then
TRAP is recognized).

There are two ways to clear TRAP interrupt.

1. By resetting microprocessor (External signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:

The RST 7.5 interrupt is a maskable interrupt.

It has the second highest priority.

It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.

Maskable interrupt. It is disabled by,

1. DI instruction

2. System or processor reset.

3. After reorganization of interrupt.

Enabled by EI instruction.

RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay
high until it recognized.

Maskable interrupt. It is disabled by,

1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt.

Enabled by EI instruction.

The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:
INTR is a maskable interrupt. It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt.

Enabled by EI instruction.

Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply
the address of ISR.

It has lowest priority.

It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain
high state until it recognized.

The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low
interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction OPCODE on
the data bus. In the case of multibyte instruction, additional interrupt acknowledge
machine cycles are generated by the 8085 to transfer the additional bytes into the
microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and
execute received instruction
SIM & RIM Interrupts

SIM and RIM for interrupts:

The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5
using SIM instruction.

The status of these interrupts can be read by executing RIM instruction.

The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM
instruction.

The format of the 8-bit data is shown below

The status of pending interrupts can be read from accumulator after executing RIM
instruction.

When RIM instruction is executed an 8-bit data is loaded in accumulator, which can
be interpreted as shown in fig.