IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 9, NO.

3, MAY 1994

297

Design of High-Efficiency
RF Class-D Power Amplifier
Sayed-Am El-Hamamsy, Member, IEEE

I. INTRODUCTION

LASS-D RF power amplifiers have been in use for a long

time. Because of the switching nature of this amplifier,
it has achieved efficiencies of 80% at low power (10 to 100
W) and of 70% at higher power (100 to 500 W). However,
the theoretical efficiency of a Class-D amplifier is 100%.
The reason for the lower efficiency in practice has been the
increased switching losses associated with the RF operation.
Early papers on Class-D amplifiers neglected the effect of these
switching losses [l], [2]. In this paper, the losses in an rf
switching power amplifier and their frequency dependence are
described. The losses analyzed are the switching, conduction,
and gate drive losses. The last of these are usually ignored
in lower frequency applications, but must be accounted for
at the frequencies of interest in this paper (> 10 MHz).
Expressions are derived to predict the efficiency of a Class-D
power amplifier.
In recent years, Class-D circuits operating with zero-voltage
switching using the dead time have been introduced [3]-[5].
However, none of these papers describe the design equations
or give the conditions for zero-voltage switching. At rf the
available dead time is very short therefore the design space is
more restricted. In this paper, the circuit is analyzed to predict
the proper magnitude of the dead time and the load current
to allow zero-voltage switching of the devices. There are also
issues related to the control of that dead-time with a reasonable
accuracy when the dead-time is in nanoseconds. Using a square
wave gate drive to do the timing quickly becomes very difficult
as the switching frequency gets to the megahertz range and
above. A method whereby the amplitude of the sinusoidal gate
voltage controls the dead time is described [6]. The design
equations for the zero-voltage switching Class-D circuit are
derived.
A 30&W, 13.56-MHz, Class-D circuit is designed in the
traditional manner to illustrate the magnitude of the different
types of loss. A circuit using the ZVS equations developed in
this paper is designed. An experimental circuit is built using
standard IRF540 devices in TO220 packages. That circuit
does not meet its performance goals because of the package
inductance. A new low inductance half-bridge package is
introduced to solve this problem. Techniques for circuit layout
and power measurements for rf applications are also presented
in the experimental section. A low loss gate drive circuit is also
Manuscript received July 8, 1991; revised January 18, 1994.
The author is with General Electric Corporate Research and Development,
Schenectady, NY 12301 USA.
IEEE Log Number 9402444.

presented using a Class-E circuit to provide the drive power.

The experimental results confirm the accuracy of the design
equations derived in this paper.
11. LOSSESIN SWITCHING POWER AWLIFIERS

In contrast to the traditional Class A, B, and C amplifiers,

switched-mode power amplifiers such as the Class-D amplifier
have a theoretical efficiency of 100%. Thus, if one assumes
that the switching devices are ideal (i.e.. have zero resistance
when on, infinite resistance when off, no associated parasitic
capacitance or inductance, and zero transition times), then the
losses in the amplifier are zero. In the other amplifiers, inherent
losses caused by the linear mode operation of the devices make
the theoretical efficiency much less than 100%. However,
such ideal devices and components do not exist, so one must
contend with some losses in the switching power amplifiers.
In this section, the losses in switching power amplifiers are
discussed with emphasis on the, effect of operation at radio
frequencies.
A . Conduction Losses

Conduction losses include all the power dissipation caused

by the resistances associated with the semiconductor devices,
the inductors, and the capacitors. The conduction losses in the
semiconductor are not affected by the operation at higher frequencies, primarily because the skin depth in semiconductors
at the frequencies of interest are large relative to the size of
the device.
Therefore, the operating frequency has no direct impact on
conduction losses within the semiconductor devices. However,
the skin effect adversely affects the losses in inductors, capacitors, and in all conductors carrying large rf currents. At the
frequencies of interest, multilayered ceramic capacitors exist
that exhibit very low loss at frequencies up to hundreds of
megahertz. Similarly, proper design of inductors and of all
connections that carry large currents can reduce the losses
resulting from the skin effect. In general, one should use wide,
flat, and short connections to reduce losses as well as to reduce
the effect of parasitic lead inductances.

B. Turn-On Switching Losses

At the tum-on instant, the device has a high voltage across
its output terminals and no current. The voltage starts to fall
from its initial value and the current starts to rise toward its
final value. If this voltage fall is not instantaneous, there is
a crossover period when both the current and the voltage are

0885-8993/94$04.00 0 1994 IEEE

298

nonzero. A significant amount of energy can be dissipated

during this time [7], [8]. The power dissipation due to this
mechanism is proportional to the length of the crossover
period. It is also proportional to the switching frequency
as the energy loss occurs every switching cycle. This loss
mechanism is negligible in a Class-D circuit as the tum-on
occurs essentially at a zero-current crossing.
A more important loss mechanism that occurs at the tumon transition is due to the discharge of the energy stored
in the output capacitor of the semiconductor power devices.
This capacitance is intrinsic to the device, a result of the
existence of PN junctions. For example in a MOSFET, the
output capacitance, Cos,, is formed by the drain-to-drain
capacitances. Even in an idealized system-that is, one with
zero resistance and zero switching times-this discharge loss
cannot be eliminated.
The device capacitances are nonlinear and vary with the
drain-to-source voltage. In order to simplify the analysis, the
nonlinearity of the device capacitances is ignored in this paper.
The capacitance is assumed to be fixed and the value of CO,,
at a drain-to-source voltage of 25 V is used. The effect of
the nonlinearity can be accounted for and will be the topic
of a future paper. In a Class-D circuit, (Fig. 3), there are two
devices that switch on and off altemately. If the first device is
off, then the voltage across it is equal to the rail voltage V&
and the energy stored in the output capacitor CO,,is

This energy is being dissipated once in every cycle of the

switching frequency; therefore, the discharge power loss is

Simultaneously, the capacitor of the second device is charged

through the resistance of the first device to the rail voltage. As
we assume the output capacitances are fixed, then the charging
process dissipates an amount of energy equal to the amount of
energy being stored. Thus, the tum-on loss in a Class-D circuit
at every switching transition will be twice the loss in (2). As
there are two switching transitions per cycle, the total tum-on
losses in a Class-D circuit is four times the loss in (2). This
loss mechanism can easily be the dominant one, especially in
cases where the voltage across the device is relatively large,
i.e., 50 V or more. A calculation of the tum-on switching
losses is presented for a practical circuit in Section 111. As
mentioned above, the output capacitances of the power devices
are intrinsic in the structure of the devices, and cannot be
reduced to zero. Thus, the only practical means for reducing
this power loss would be to achieve zero-voltage switching.

C . Turnoff Switching Losses

The same type of crossover power loss that occurs at tumon also occurs at tumoff. In contrast to the turn-on period,
there is no capacitor voltage discharge loss. However, there
is a dual type of loss caused by the current flowing in
parasitic inductors. At turnoff, the current is flowing through
the leads and wire bonds into the device. In general, parasitic

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 9, NO. 3, MAY 1994

inductances are associated with these leads. The amount of

energy stored in these inductances is equal to

EL = 1/2L'I

(3)

where L is the parasitic inductance value and I is the current

flowing at the tumoff instant. The power loss from this energy
discharge is also proportional to the switching frequency and
is given by

PL = 1/2L I 2 f s .

(4)

In contrast to the capacitive discharge losses, in which the

device capacitances are not under the control of the circuit
designer, the inductive discharge losses can be reduced by
proper design of the circuit layout or by using low lead
inductance packages.
D . Gate Drive Losses
At low frequencies, MOSFET's consume very little gate
drive power, which is one of their most interesting features.
However, as the frequency increases, the power dissipation
caused by charging and discharging the gate capacitance
becomes significant. For the sake of simplifying the analysis,
the gate circuit is represented by a series RC circuit [Fig.
l(a)]. Because of the Miller feedback effect of the gate-drain
capacitance and the variation of the device capacitances with
voltage, the gate charge required to turn on a device is the
best way to correctly predict the gate drive requirements [9].
The gate drive power requirement is dependent on the type
of drive being used. We will examine two types of gate
drives: a square-wave gate drive and a sinusoidal resonant
gate drive. The two drive schemes will have different losses
for a given peak gate voltage and switching speed. The peak
current requirements of each system are also different.
In the case of a square-wave drive, the input voltage is a
square wave but the input current is a pair of pulses [Fig. l(b)].
The total charge required by the gate (given by the hatched
area under the gate current in Fig. l(b) and the peak voltage
across the gate determines the amount of energy stored in the
gate capacitance as follows:

Egate = 1 /2VgsQ g

(5)

where Qg is the charge required to raise the gate voltage to

Vgs.Note that Qg is obtained from the device data sheets
and that it includes the amount of charge stored in the gatedrain capacitor as well as the gate-source capacitor. As the
gate is being charged through a resistor, the same amount
of energy is dissipated in that resistor during the charging
process. Similarly, when the gate is discharged, the stored
energy is dissipated resistively. Therefore, the loss associated
with tuming the device on and off per cycle is two times Egater
and the power loss is given by

Pg

zz

VgsQgfs.

(6)

The peak current required to switch an MOSFET is dependent on the desired switching speed. The time constant 7 of

EL-HAMAMSY: DESIGN OF HIGH-EFFICIENCY RF CLASS-D POWER AMPLIFIER

299

c
1
7-

1
T

'g

cis

/vg

Fig. 2. (a) The simplified equivalent circuit of a resonant gate drive circuit.
(b) The input current and the voltage across the gate capacitor.

(b)

be calculated from the required gate charge Qg as follows:

Ig =

Fig. 1. (a) The simplified equivalent circuit of the gate and gate drive circuit.
(b) The input voltage waveform, u g , the voltage across the gate capacitor,
e g 8 , and the input current waveform, 2,.

Qg

(9)

cos (w,t) dt
-

Qg Ws

(10)

the RC network determines the length of time to, it takes the

gate capacitance to charge up to Vgs. Typically, it takes a total
time equal to 47 to fully charge a capacitor. Therefore, for a
gate capacitance Cis,, one can calculate a desired value of gate
resistance R, and gate drive circuit resistance Rd as follows:

Note that V, is only equal to the peak voltage of the sine

wave when tonis equal to a quarter of the switching time t,.
The peak gate current under this condition is then equal to

The value of Cis,used here is the value at V d , = 0, which

gives a worst-case scenario for the gate and drive resistances.
The peak current in the gate drive circuit is then given by

The peak voltage capability of the gates of the MOSFET will

then clearly limit how fast one can switch the device with a
resonant sinusoidal gate drive. The peak voltage across the
gate of the device is given by

sin (w,ton) *

v,,

V9Speak - sin (w,t,,)

Note that the power requirement for the gate drive with a
square-wave voltage is independent of the switching speed,
and the switching speed is ultimately limited by the gate
resistance. Thus, there is an intrinsic limit to how fast the
gate can be charged, which becomes a factor as the frequency
of operation increases.
The sinusoidal resonant gate drive requirements and power
losses require a different calculation (Fig. 2). The input voltage
waveform is sinusoidal and if one ignores the nonlinearity of
the input gate capacitance, the current is also sinusoidal. Thus,
the peak current needed to charge the gate from zero to Vg,in
a time ton,with a sinusoidal gate drive of frequency fz can

(12)
*

Because the gate capacitance is being resonated by the resonant inductor Ld in Fig. 2(a), the reactive impedance of the
gate circuit is considered negligible. Thus, the required input
voltage is equal to

and the power dissipation is

The above equations yield approximate values because the

nonlinearity of the device capacitance and the Miller effect
have not been taken into account. In contrast to the squarewave gate drive, the sinusoidal resonant gate drive is not

300

limited in switching speed by the gate resistance, yet the power

requirement is proportional to the resistances. One can reduce
the time it takes to reach a certain gate voltage by increasing
V, to increase the peak current Ig,subject to the condition that
the peak voltage across the gate capacitance does not exceed
its rated capability. The power losses in the gate drive can
be reduced by reducing the drive resistance. This is because
in a resonant configuration, the energy stored in the gate gets
stored for a half cycle in the resonant inductor and is recovered
during the next half cycle, but with square-wave switching, the
energy is always resistively dissipated.
In general, the square-wave gate drive has much more severe
requirements than the resonant gate drive. The gate drive
devices must be very fast, and must be capable of sourcing
or sinking large currents. For example, to charge a 2000pF capacitor in 10 ns to 10 V, total gate drive resistance
must be equal to 1 . 2 5 0 ; thus, the peak current required is
8 A. In order to compare a square-wave gate drive with
a sinusoidal gate drive, we need to assume an operating
frequency because the required peak gate current increases
with frequency. The maximum current in a sinusoidal drive
scheme would then occur at the highest operating frequency.
The highest operating frequency, for a given switching time, is
when that switching time is equal to a quarter of the full cycle.
Otherwise, the device never reaches either the fully on or the
fully off condition. Thus, the maximum operating frequency
given a 10-ns switching time is 25 MHz. Under this worst-case
condition, the peak gate drive current required is 3.14 A for the
aforementioned example. Thus, the peak current requirement
of the sinusoidal resonant gate drive is always less than that of
the square-wave gate drive for a given switching time. Another
advantage of the sinusoidal gate drive is that the design of the
gate drive transformers is much simpler. In a sinusoidal gate
drive, the transformer is a narrowband transformer; the squarewave drive requires a broadband transformer. Similarly, all
lead inductances and leakage inductances in the gate drive
circuit can be absorbed into the resonant inductor Ld, but they
have to be minimized for the square-wave drive.

111. TRADITIONAL DESIGNOF CLASS-DPOWER AMPLIFIER

A voltage-switching Class-D circuit consists of a pair of
power devices in a cascade connection (Fig. 3). The devices
are switched on and off altemately. The input dc voltage is
connected to the drain of the top device and the source of the
lower device is connected to ground. The devices are driven
via a three-winding transformer with appropriate polarities on
the output so that the same drive is used for both devices.
The midpoint between the two devices is connected to the
load circuit. In this discussion, the load network is assumed to
be a series RLC network. The traditional design assumes that
the RLC resonant frequency is the switching frequency of the
devices [ 11. Therefore, because the devices switch altemately,
the voltage at the midpoint (w,) is a square wave voltage of
amplitude equal to v d c , if the devices are assumed to be ideal.
Since the load network is a tuned circuit that provides little
impedance to the fundamental component of the voltage w,
and high impedance to the higher harmonics, one can assume,

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 9, NO. 3, MAY 1994

Fig. 3. Voltage-switching Class-D power amplifier.

with a reasonable Q(-10) that the current flowing is the one

driven by the fundamental component of the input voltage.
Because the voltage is a square wave, its Fourier expansion
is given by
U,(&)

[:+ 5

=vdc -

- sin (ut)

2
+sin ( 3 u t ) .. . .
37r
As the impedance of the RLC series load at resonance is equal
to R L , the current is given by
2vdc

i L ( u t ) = -sin (ut).
7rRL
Each of the devices carries the current during one half of the
switching cycle, so (16) determines the peak device current.
The output power is then given by
2
Po = --.

7r2

v:c
RL

(17)

We will design a 300-W Class-D amplifier operating at

13.56 MHz from a 75-V dc input voltage. From the design
equations (16) and (17), we get the following values for the
load resistance and the device peak current:
R L = 3.80 I L = 12.56 A.
A suitable MOSFET for the above design is the IRF 540,
which is a 100-V, 28-A device. The efficiency of that Class-D
design can be predicted using the expressions for the different
types of losses from Section 11. Let us assume for the sake of
simplicity that the inductors and capacitors in the circuit are
ideal and do not contribute to the losses.
The conduction losses are therefore the losses in the devices.
The IRF 540 has an on-resistance, Rdson,equal to 0.085 0.
Since each device carries the load current for half a cycle, the
conduction losses per device are

The devices are switching on and off at zero current, which

reduces the inductive discharge losses and the crossover losses
to zero. The only switching losses that remain are the capacitive discharge losses. As mentioned in Section 11-B, the losses

EL-HAMAMSY: DESIGN OF HIGH-EFFICIENCY RF CLASS-D POWER AMPLIFIER

per device ae equal to twice the losses given by (2). The output
capacitance of the device is equal to 500 pF (at v d s = 25 V),
thus the discharge losses are

301

The gate charge required to tum on an IRF 540 is 39 nC for

a gate voltage of 10 V, so from (6), the gate drive losses with
a square-wave drive are

At the end of this on-period, the lower device turns off

and the current flow in the capacitors, charging the lower
one and discharging the upper one [Fig. 4(d)]. In traditional
circuits, a lossless partial discharge of the capacitor occurs that
reduces the energy in the capacitor at the tum-on instant, which
reduces the switching loss. Hence, a finite-time switching
transition enables the circuits to achieve a higher efficiency
than expected.

Therefore, the overall efficiency for the traditional design is

A . Analysis of Zero-Voltage Switching

in Class-D Power Ampl$er

300

[300

+ 2(38.14) + 2(3.35) + 2(5.3)] = 0.76.

Clearly, the losses are dominated by the switching losses in

the above design. These switching losses are usually neglected
in the traditional analysis, and only the conduction losses
are taken into account [l]. In practice, one can expect even
worse performance as the devices, each of which is dissipating
47 W, will operate at a high junction temperature and the
on-resistance would go up by as much as 70 to 80% [lo].
However, in practice the measured efficiency is better than
the predicted efficiency [ll]. In fact, as we will show in the
next section, there is a lossless discharge mechanism in ClassD circuits (caused by the nonideal switching of the devices)
that in general improves the efficiency of actual circuits.
This lossless discharge mechanism can be used in Class-D
circuits to achieve ideal zero-voltage switching and thus totally
eliminate the discharge losses [41, [51.

It is possible to control the dead time, the peak current in the

devices, and the load phase angle relative to the fundamental
component of the voltage to achieve zero-voltage switching
and to eliminate the switching losses totally. The following
analysis refers to the waveforms in Fig. 5, which have a
slightly shifted time origin to simplify the analysis. During
the transition period the voltage at the midpoint is given by

v c ( t )= -

IL

cos (w,t - 4 ) d t .

(21)

The midpoint voltage reaches its minima at the zero-current

crossing. To achieve zero-voltage switching, the end of the
dead time should coincide with the current voltage crossing
and the amplitude of the current should be sufficient to make
the voltage minima equal to zero. Therefore, the zero-voltage
switching condition can be written as

where

is equal to

Iv. ZERO-VOLTAGE SWITCHING CLASS-DPOWER AWLIFIER

To explain the higher efficiencies achieved in practice in

Class-D circuits the switching transition between the devices
needs to be examined carefully. Fig. 4 shows the four different
switching networks that occur during a switching cycle and
the midpoint voltage and load current during those periods.
The previous analysis has assumed an instantaneous transition
between the devices. However, in practice, a dead time occurs
during the period when one device has tumed off before the
other has tumed on.
Before the switching instant, one device is on and is
conducting the load current in the direction shown in Fig. 4(a)
and the midpoint voltage is equal to Vd,. (Note: to simplify the
analysis, we shall assume that the forward drop of the devices
is negligible.) The top device is then tumed off while the
lower device is still off. During this transition period (or dead
time), if the resonant load circuit phase is lagging, the current
continues to flow through the capacitances of the devices [Fig.
4(b)]. The current discharges the capacitor of one device while
it charges the capacitor of the other device. If one assumes
that the output capacitances of the devices are equal then the
current is equally divided between them. At the end of the
transition period, the second device tums on, the midpoint
voltage goes to zero, and the current reverses direction in the
load [Fig. 4(c)].

The integral is solved to give

Before proceeding with the analysis it is important to see

what happens if the above condition is unsatisfied. If the dead
time is too short [Fig. 6(a)] or too long [Fig. 6(b)], the voltage
will not be at zero and a certain loss would occur. Similarly,
if the current amplitude is too low to discharge the voltage,
some discharge loss results [Fig. 6(c)]. On the other hand, if
the current is too large, the voltage crosses zero twice [Fig.
6(d)] and reverses polarity across the device. This situation
is potentially destructive because the negative voltage forward
biases the MOSFET body diode and tums it on. As the reverse
recovery time of the body diode is of the order of 100 ns,
it will short out the other device when it tums on and the
device will fail. It should be pointed out that the optimum
operating point is broad compared with the peak current value.
The current level needed to make the voltage go negative is so
high that the device will probably fail because of too high of a
conduction loss long before the diode failure occurs. However,
it is important to keep the different failure mechanisms in mind
when designing an actual circuit.

302

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 9, NO. 3, MAY 1994

Fig. 4. The four switching networks that appear during a full switching cycle in a Class-D circuit. (a) The top device, Q1, is conducting, and the bottom
one, 4 2 , is off. (b) The first transition period occurs when Ql is turned off while 4 2 remains off. (c) 4 2 is turned on while Ql remains off. (d) The same
as (b), except that Q2 is turned off and the current flow is reversed in the capacitor.

For the purpose of calculating the power output, it is

simpler to assume that the voltage at the midpoint between
the devices is trapezoidal. In reality, the voltage across the
capacitors falls sinusoidally under the action of the resonant
load current during the dead time, as described by (21).
However, the difference between the fundamental components
in both cases is relatively small. The angle 4,for a trapezoidal
voltage waveform, is the phase angle between the current and
the fundamental component of the voltage waveform. The
midpoint voltage is then equal to

vdc

= 2-

n-4

sin (4).

(26)

The power delivered to the load is then given by

Po = 1/2&.1L cos (4).

(27)

Substituting for Vcf from (26) in (27) yields

V d C
Po = -IL

n-4

sin (4)cos (4)

= 1 / 2 -v1dLc

n-4

sin (24).

(28)
(29)

EL-HAMAMSY: DESIGN OF HIGH-EFF'ICIENCY RF CLASS-D POWER AMPLIFIER

303

I
Fig. 5. Waveforms of the midpoint voltage vc, the fundamental component
of the midpoint voltage ucf,and the load current ZL.

vc

400 v

Fig. 7. V I curves satisfying the zero-voltage switching condition for a

power output of 3000 W at 13.56 MHz for the IRF 540 (boxes) and the
IRF (530 (crosses) power MOSFET's. The safe operating areas (SOA) of the
two devices are superimposed on the graph (thick lines).

VC

"C

"C

(C)

1,
2

(4

Fig. 6. Four possible nonoptimal switching situations. (a) The dead time
is too short. (b) The dead time is too long. (c) The current is too low to
fully discharge the capacitance. (d) The current is too high, which causes the
voltage across the device to switch polarity.

Substituting the value of V& that satisfies the zero voltage

condition (24) into (29) yields the equation for the load current:

Equations (30) and (24) give the required dc input voltage

and the load current for a given power output, frequency
of operation, dead time, and device output capacitance for
zero-voltage switching of the devices. Therefore, given the
output power and the frequency of operation, one can generate
a family of VI curves, parameterized by C,,,,. Each point
on these curves satisfies the power output requirement under
optimum, i.e., zero-voltage, switching condition at a specific
dead time.
Fig. 7 shows such a plot of the VI curves for two commercial
devices. By superimposing the safe operating area (SOA) of
the devices on the curves, one can determine whether or not a
particular device is suited for the particular design conditions.
As can be seen, the IRF 540 is suitable for the 300-W circuit
at 13.56 MHz. The value of the dead time remains to be
determined. This can be done graphically by either plotting the

input dc voltages versus the dead time or the current versus

the dead time (Fig. 8). In the case of the IRF 540 devices, a
suitable dead time is 12 ns, which places the operating point
at about 72 V and 15 A. This is a reasonable distance from
both the maximum current and voltage ratings of the device.
The control of the dead time is a matter of practical
importance. At these frequencies, precisely controlled square
waves are difficult to generate, and to control the dead time to
an accuracy of 1 ns could be very expensive. As mentioned
earlier, a square-wave gate drive scheme would require the
design of a well-matched broadband system, which is much
more difficult to do than designing a single frequency matched
system. In the next section, a sinusoidal drive scheme in which
the dead time is controlled by the amplitude of the gate voltage
is introduced and some of its limitations are discussed.

B. Sinusoidal Gate Drive With Dead-Time Control

MOSFET's have a threshold gate voltage level below which
they are off. In the case of power switching MOSFET's, such
as the Intemational Rectifier Hexfets, the transition from off
to on occurs very fast once the threshold is crossed. This
property of the devices allows us to use a sinusoidal input
voltage to control the dead time between the two devices. The
gate voltages are sinusoids out of phase by 180' (Fig. 9). The
gate voltage of one device will cross the threshold to turn that
device off while the gate voltage across the other device is
still below threshold. Thus, during this crossover period the
two devices are off, which is the desired state. Knowing the
threshold voltage of the devices, one can determine the gate
drive voltage required for a specific dead time.
The voltage across the gate source capacitance is

V,,(t) = V,, sin(w,t).

The gate voltage is equal to the threshold voltage V, at time

304

IEEE TRANSACHONS ON POWER ELECTRONICS, VOL. 9, NO. 3, MAY 1994

vt

vgsl' Vgsz

72 v

0
12 ns

5 ns

t,

1s

Fig. 9. Two sinusoids out of phase by 180,showing the threshold voltage,

Vt, of the device and the resulting dead time.

25 ns

(a)

L rfc

40 A

CS

LS

'L

Fig. 10. Circuit diagram of Class-E zero-voltage switching circuit.

15 A

0
5 ns

12 ns

25 ns

t,
(b)

Fig. 8. (a) The curve of input dc voltage versus dead time for the same
devices as in Fig. 7. (b) The curve of device peak current versus dead time
for the same devices. The chosen operating point for the IRF 540 is also
shown.

t d / 2 , which gives

V, = v,, sin (ws

$)

(32)

, which can be rewritten as

v,

v,,=

sin (w,

2)

(33)

'

Thus (33) gives the required gate voltage for a given dead
time. However, it is important to first examine the range of
dead times achievable using this gate drive scheme. In order
to do this, it is easier to rearrange (33) as follows:
td

2
=w2 sin-'

($).

(34)

The first limitation is that the peak gate voltage of the devices
is usually limited to 20 V. This sets a limit to how short the
dead time can be

(35)

At 13.56 MHz and assuming V, = 3.5 V, the minimum dead

time is equal to 4.1 ns. The other limit to the dead time occurs
when the gate source voltage becomes too low to turn on the
device properly. As a matter of good design practice the gate
voltage should not be lower than about 6.5 V. Thus, the largest
dead time one can achieve is slightly higher than 13 ns. The
dependence of the dead time on the amplitude of the gate
drive voltage makes the control circuit design very simple and
economical. However, it does limit the range of dead times
over which one can operate the circuit.
The dead time chosen for the circuit design with the IRF 540
was 12 ns. This requires a gate source voltage of 7.2 V. From
the data sheets for the IRF 540, the required gate charge for
the above gate voltage is 30 nC. From (1 1) the gate current is
then equal to 26 A. The gate resistance of the IRF 540 is equal
to 1 R. Thus, the drive power requirement for this design is
equal to 3.27 W per device. The total gate drive requirement,
however, must include the efficiency of the gate drive circuit.
The gate drive losses are not an insignificant portion of the
total losses. The value of the gate resistance is beyond the
circuit designer's control, so the best one can do is to generate
that gate drive as efficiently as possible. Fortunately, highefficiency resonant circuits exist to generate this gate drive.
The simplest circuit (because it uses a single transistor) is a
Class-E circuit (Fig. 10) [12]. It is also possible to use a ClassD circuit whose two devices would have much smaller drive
requirements so they can be driven directly from the crystal
oscillator circuit.
The design equations for the Class-E circuit have been
derived for different operating conditions in [ 131-[ 151. These
can be used to design the driver for the Class-D circuit,
keeping in mind that the output in the driver case is not
the power to the gate resistance but the voltage across the

EL-HAMAMSY: DESIGN OF HIGH-EFFICIENCY RF CLASS-D POWER AMPLIFIER

305

24

Current
Viewing
Resistor

Fig. 11. Circuit diagram of experimental Class-D 300-W power amplifier.

gate capacitance. One other consideration is the transformer

connection. The two gates could be driven from a single
transformer, with two secondaries connected with opposite
polarities to give the 180" phase shift between the two gate
voltages. This has the obvious advantage of using only one
gate drive transformer. However, this advantage may be fully
offset by the need to eliminate a positive feedback mechanism
that results in increased losses. The ringing in the drain circuit
of the conducting device is coupled into the gate of the
other device by way of the Miller feedback capacitor and the
gate drive transformer windings. The gate drive modulation
increases the amplitude of the ringing, which completes the
feedback loop. The increased ringing implies large circulating
currents in the devices that cause additional conductive losses.
Therefore, it may be preferable to drive the gates through two
transformers with series-connected primaries or with parallelconnected primaries. The choice would affect the reflected
load into the primary and it is the reflected load that needs
to be used in the Class-E circuit design. The detailed design
of the gate drive circuit is beyond the scope of this paper and
therefore will not be given here.
v . EXPERIMENTAL
VERIFICATION OF RESULTS
An experimental circuit based on the design equations given
in the preceding section was built and tested (Fig. 11). The
design point chosen for the IRF 540 with an 11.5 ns dead
time gives an input voltage of 72.5 V and a load current of
15.3 A peak. The load phase angle is $ = 28" and the load
resistance for 300 W is then equal to
2PO
RL = __
= 2.55R.
IL

(36)

The load-phase angle is used to give the value of the load

reactance
1
X L = w,L, - -= RL tan ($).
(37)
w,

c,

A reasonable value of Q for the load circuit is 10. Therefore,

the series inductor has to be equal to

L , = Q-RL = 0.3pH.
W,

(38)

Copper
Chilled
Plate

Resistors
each side

Copper Clad
PC Board
for Low Inductance
Parallel Connection

Water Inlet
and Outlet

Fig. 12. The load resistance used for calorimetry.

The required series capacitance needed to provide the proper

phase angle can now be calculated from equation 37:

C, = 486 pF.

(39)

The load resistance was obtained by paralleling 36 8 0 4 25W resistors in TO3 packages. These resistors were mounted
on two annular copper chilled plates welded to a 1/8 in.
copper tube for water cooling (Fig. 12). The resistors are all
connected in parallel using a smaller ring made of doublesided printed circuit board. Each side of the board forms
one terminal of the load resistor. The whole assembly is
placed in a thermally insulating enclosure with openings for
the water inlet and outlet and for the electrical terminals.
Other circuit resistances, such as the series resistance of the
inductor (0.2fl) and the current viewing resistor ( O.lR),
provided the additional resistance needed to reach 2.5 0.
The water inlet and outlet temperatures were measured with
thermocouples to provide a calorimetric measurement of the
power delivered to the loads. The calorimeter was calibrated at
dc at a fixed rate of water flow to give the dissipated power in
the load versus the differential voltage on the inlet and outlet
thermocouples.
The series capacitance was provided by the parallel combination of four 100-pF Murata Erie capacitors and a 0- to 100pF variable multiple plate air capacitor. The Murata capacitors
are glass-encapsulated multilayered ceramic capacitors with an

EL-HAMAMSY: DESIGN OF HIGH-EFFICIENCY RF CLASS-D POWER AMPLIFIER

--

Connector
for Gate Drive

307

2.4 ns

20 nsldiv

202.4 ns

GateDriw
Transformers

Fig. 15. Printed circuit board layout for Class-D power amplifier using the
low-inductance packages.

viewing resistor of 0.152 is placed in series with the load

20 nsldiv
202.4 ns
resistor in the ground return to measure load current. A 2.4 ns
Tektronix 11402 digital scope is used to measure the voltage Fig. 16. The midpoint voltage, load current, and instantaneous power waveand the current and to multiply them. The average of the forms for the Class-D power amplifier operating at an output power of 298
instantaneous power is then taken as a reading of the power w.
delivered to the load. The scope and probes are calibrated
with a standard 50-52 water load. The length of the coaxial source voltage was 7 V peak, which agrees very well with the
cable connecting the current viewing resistor to the scope is value calculated from (33). This drive voltage is relatively
chosen to give the correct phasing of current versus voltage, as low, yet increasing it lowers the efficiency of the circuit.
measured by the voltage probe at the operating frequency. The Increasing the gate drive reduces the on-losses and increases
measurements obtained by calorimetry are corrected to account the output power but lowers the overall efficiency because of
for the resistances that are outside the calorimeter load. This the increased switching losses. Similarly, making the current
is done by multiplying the power obtained from the thermal phase smaller or larger also decreases the efficiency. This is a
measurement by the ratio of the total load resistance with the direct confirmation of the correctness of the analysis performed
resistance of the water load. This ratio is equal to 2A2.2.
in this paper.
The scope measurements and the calorimetry measurements
The nongate drive related power loss in the devices is equal
agree to within 1 W out of 300 W. The thermal measurement to 18.2 W. The device on-resistances are rated as 85 mR with
is time-consuming to make since one must wait until the load a 10-V gate drive. At the current levels under consideration
reaches thermal stability, in addition to the constant need for and with a 7-V gate drive Rdson is approximately the same
clearing the water lines of bubbles formed in the load as as with a 10-V drive. The operating temperature of the device
the water is heated. Therefore, since the initial measurements is calculated based on a heat sink temperature of 70" C, a
prove the accuracy and reliability of the scope measurements, junction-to-case thermal resistance of 1 K/W and a case-toonly these are recorded. However, the thermal measurements heat-sink thermal resistance of 0.84 K/W to be 96" C (The
are done every so often as a further check. The power case is 15.3" C higher than the heat sink and the junction is
measurements also agree with the calculated power budget 11" C higher than the case). Thus, the on-resistance of the
and the measurement of device heat sink temperature rise.
device is 1.5 times higher than the 25" C value, which makes
Fig. 16 shows the midpoint voltage, the load current, and it equal to 0.12852. The conduction losses are then equal to
the instantaneous power waveforms of the circuit running off 15.15 W for the two devices. Hence, the power losses are
a dc input voltage of 73.1 V with an input current of 4.33 A. accounted for by the gate drive and conduction losses, except
The output power is measured to be equal to 298.2 W. The for 3 W which could be due to the remaining high-frequency
drain efficiency (does not include gate drive) is then equal to ringing across the devices, or even to some residual switching
94.2%. The total power dissipated in the gate drive circuit is losses. The power budget indicates that the switching losses
9.6 W. Therefore, the overall efficiency is 91.4%. The gate- are, in fact, very small.

308

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 9, NO. 3, MAY 1994

VI. CONCLUSIONS
power amplifier at rf is identified as being the discharge
of the parasitic output capacitance of the power
A
method for eliminating it by introducing a dead time between
the devices is proposed. A resonant gate drive scheme is
introduced that allows fine control of the dead time between
the devices at low cost by use of the amplitude of the gate
drive Use Of a high-efficiency circuit (such as the
circuit or a low-power Class-D circuit), makes this gate drive
scheme very efficient.
The full design equations for very high efficiency ClassD power amplifiers are developed. These design equations
satisfy simultaneously the output power requirement and the
lossless discharge of the output capacitance of the devices.
A low-inductance half-bridge package is designed for operation at rf. This package may be used at lower frequencies
where the ringing or the current spikes caused by parasitic
inductances are undesirable. Thus, use of such a package in
conjunction with a zero-voltage transition resonance switching
method should help to reduce the cost of lower frequency
switching converters by eliminating the need for snubbers
and simplifying the design of EM1 filters. An experimental
circuit has been built to test the concept. The test circuit is
operated at 13.56 MHz with a 300-W output at more than
90% efficiency. This Ombination
Of power level, Operating
frequency, and efficiency is not attainable without the use
Of zero-voltage switching
circuits based On the
concepts described in this paper have been built and tested at
different frequencies and power levels. The agreement between
the prediction and the theory in all the circuits was always very
good, making this a powerful, robust approach.

REFERENCES
Engineering. New York: Wiley, 1980.
[2] F. H. Raab, Get broadband, dual-mode operation with this FET power
amplifier, Electronic Design News, Oct. 20, 1978.
[3] M. Boidin, H. Fwh, and P. Proudlock, The design, construction and
evaluation of a new generation H. F. 40 kW dc converter, Proc. Power
Conversion International Con$. 1984.
[4] B. carsten, A hybrid series-pardlel resonant converter for high frequencies and power levels, Proc. High Frequency Power Conversion
Conf., Apr. 1987, pp. 41-47.
[5] F. M, Magalhaes, F. T, Dickens, G, R, Wester, and N, G, Ziesse,
Zero-voltage switched resonant half-bridge high-voltage d c 4 c converter, Pro;. High Frequency Power Conversion-Conf., May 1988, pp.
332-343.
[6] S. A. El-Hamamsy and G. Jernakoff, Driver for a high-efficiency,highfrequency Class-D power amplifier, U.S. Patent No. 5,023,566, June
11, 1991.
[7] S. Clemente, B. R. Pelly, and A. Isidori, Understanding HEXFET
switching performance, Application Note 947, Internat. Rectifier
HEXFET Data Book, 1985 edition.
[8] M. F. Schlecht and L. F. Casey, A comparison of the square-wave and
quasi-resonant topologies, Proc. IEEE Appl. Power Electronics Conf.,
Mar. 1987, pp. 124-134.
[9] K. Gauen, Gate charge explains HF effects of MOSFET parasitic
capacitances,Power Conversion and Intelligent Motion Magazine, Mar.
1989.
[lo] International Rectifier HEXFET Power Mosfet Databook, 1985 ed.
[ 111 H. 0. Granberg, Applying power MOSFETs in Class D/E RF power
amplifier design, RF Design Magazine, June 1985.
[I21 N. 0. Sokal and A. D. Sokal, Class E-A new class of high-efficiency
tuned single-ended switching power amplifiers, IEEE J . Solid-Stare
Cir., vol.SC-10, no. 3, June 1975.
[I31 F. H. Raab, Idealized operation of the Class E tuned power amplifier,
IEEE Trans, Circ, Sysr,, vol. CAS-24, no. 12, Dec. 1977,
Effects of circuit variations on the Class E tuned power ampli[14] -,
fier, IEEE J. SoIid-Srate Circuits, vol. SC-13, no. 2, Apr. 1978.
[15] M. K, Kazimierczuk and K. hczko, Exact analysis of Class E tuned
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Syst., vol. CAS-34, no. 2, Feb. 1987.

ACKNOWLEDGMENT

Many people contributed to make this work possible. In

particular, the authors thanks go to J. Borowiec and R.
Thomas for constructing the circuits, building the calorimetry
setup, and calibrating it, and to G . Jemakoff for designing the
gate drive circuit and for helping get started on the project.
He also thanks C. Neugebauer, A. Yerman, C. Korman, W.
Burdick, and the technicians of the Advanced Assemblies
Group for their help in designing, building and testing the
low inductance packages. The author would also like to
acknowledge the many helpful discussions with V. Roberts and
J. Anderson whenever faced with particularly thomy problems.

Sayed-Amr El-Hamamsy (S85-M86) was born

in 1956 in Cairo, Egypt. He received the B.Sc. degree in electrical engineering from Cairo University,
Cairo, Egypt, in 1979, the M.S. and Ph.D. degrees
from the California Institute of Technology in 1981
and 1986, respectively.
Since 1986 he has been working at the G.E.
Corporate Research and Development center in Schenectady, NY. His research interests are in ballasts for discharge lamps, in particular electrodeless
lamps (both high intensity discharge and fluorescent
lamps), high power factor ballasts for compact fluorescent lamps, magnetics
modeling, radio frequency power amplifiers. He is the holder of twenty-four
U.S. patents and has several patent applications pending.